diff --git a/arch/arc/lib/start.S b/arch/arc/lib/start.S
index 90ee7e0fe4..b2ba768309 100644
--- a/arch/arc/lib/start.S
+++ b/arch/arc/lib/start.S
@@ -10,6 +10,22 @@
 #include <asm/arcregs.h>
 
 ENTRY(_start)
+	; Non-masters will be halted immediately, they might be kicked later
+	; by platform code right before passing control to the Linux kernel
+	; in bootm.c:boot_jump_linux().
+	lr 	r5, [identity]
+	lsr	r5, r5, 8
+	bmsk	r5, r5, 7
+	cmp	r5, 0
+	mov.nz	r0, r5
+	bz	.Lmaster_proceed
+	flag	1
+	nop
+	nop
+	nop
+
+.Lmaster_proceed:
+
 	/* Setup interrupt vector base that matches "__text_start" */
 	sr	__ivt_start, [ARC_AUX_INTR_VEC_BASE]
 
diff --git a/board/synopsys/axs10x/axs10x.c b/board/synopsys/axs10x/axs10x.c
index a5e774b2cf..e6b69da3da 100644
--- a/board/synopsys/axs10x/axs10x.c
+++ b/board/synopsys/axs10x/axs10x.c
@@ -7,6 +7,7 @@
 #include <common.h>
 #include <dwmmc.h>
 #include <malloc.h>
+#include <asm/arcregs.h>
 #include "axs10x.h"
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -61,16 +62,32 @@ void smp_kick_all_cpus(void)
 {
 /* CPU start CREG */
 #define AXC003_CREG_CPU_START	0xF0001400
-
 /* Bits positions in CPU start CREG */
 #define BITS_START	0
-#define BITS_POLARITY	8
+#define BITS_START_MODE	4
 #define BITS_CORE_SEL	9
-#define BITS_MULTICORE	12
 
-#define CMD	(1 << BITS_MULTICORE) | (1 << BITS_CORE_SEL) | \
-		(1 << BITS_POLARITY) | (1 << BITS_START)
+/*
+ * In axs103 v1.1 START bits semantics has changed quite a bit.
+ * We used to have a generic START bit for all cores selected by CORE_SEL mask.
+ * But now we don't touch CORE_SEL at all because we have a dedicated START bit
+ * for each core:
+ *     bit 0: Core 0 (master)
+ *     bit 1: Core 1 (slave)
+ */
+#define BITS_START_CORE1	1
 
-	writel(CMD, (void __iomem *)AXC003_CREG_CPU_START);
+#define ARCVER_HS38_3_0	0x53
+
+	int core_family = read_aux_reg(ARC_AUX_IDENTITY) & 0xff;
+	int cmd = readl((void __iomem *)AXC003_CREG_CPU_START);
+
+	if (core_family < ARCVER_HS38_3_0) {
+		cmd |= (1 << BITS_CORE_SEL) | (1 << BITS_START);
+		cmd &= ~(1 << BITS_START_MODE);
+	} else {
+		cmd |= (1 << BITS_START_CORE1);
+	}
+	writel(cmd, (void __iomem *)AXC003_CREG_CPU_START);
 }
 #endif