Merge git://git.denx.de/u-boot-x86

- Edison switch to CONFIG_OF_SEPARATE.
- Tangier initial ACPI support for PMIC device.
- TSC timer driver update to support native calibration.
- Fixes to 64-bit U-Boot proper.

arch/x86/cpu/i386/call64.S

@@ -79,6 +79,10 @@ lret_target:
 	mov	%eax, %eax		/* Clear bits 63:32 */
 	jmp	*%eax			/* Jump to the 64-bit target */
 
+.globl call64_stub_size
+call64_stub_size:
+	.long	. - cpu_call64
+
 	.data
 	.align	16
 	.globl	gdt64

arch/x86/cpu/i386/cpu.c

@@ -462,6 +462,7 @@ int cpu_has_64bit(void)
 		has_long_mode();
 }
 
+#define PAGETABLE_BASE		0x80000
 #define PAGETABLE_SIZE		(6 * 4096)
 
 /**
@@ -522,33 +523,21 @@ int cpu_jump_to_64bit_uboot(ulong target)
 	typedef void (*func_t)(ulong pgtable, ulong setup_base, ulong target);
 	uint32_t *pgtable;
 	func_t func;
+	char *ptr;
 
-	/* TODO(sjg@chromium.org): Find a better place for this */
+	pgtable = (uint32_t *)PAGETABLE_BASE;
-	pgtable = (uint32_t *)0x1000000;
-	if (!pgtable)
-		return -ENOMEM;
 
 	build_pagetable(pgtable);
 
-	/* TODO(sjg@chromium.org): Find a better place for this */
+	extern long call64_stub_size;
-	char *ptr = (char *)0x3000000;
+	ptr = malloc(call64_stub_size);
-	char *gdt = (char *)0x3100000;
+	if (!ptr) {
+		printf("Failed to allocate the cpu_call64 stub\n");
+		return -ENOMEM;
+	}
+	memcpy(ptr, cpu_call64, call64_stub_size);
 
-	extern char gdt64[];
-
-	memcpy(ptr, cpu_call64, 0x1000);
-	memcpy(gdt, gdt64, 0x100);
-
-	/*
-	 * TODO(sjg@chromium.org): This manually inserts the pointers into
-	 * the code. Tidy this up to avoid this.
-	 */
 	func = (func_t)ptr;
-	ulong ofs = (ulong)cpu_call64 - (ulong)ptr;
-	*(ulong *)(ptr + 7) = (ulong)gdt;
-	*(ulong *)(ptr + 0xc) = (ulong)gdt + 2;
-	*(ulong *)(ptr + 0x13) = (ulong)gdt;
-	*(ulong *)(ptr + 0x117 - 0xd4) -= ofs;
 
 	/*
 	 * Copy U-Boot from ROM

arch/x86/include/asm/arch-tangier/acpi/southcluster.asl

@@ -320,6 +320,93 @@ Device (PCI0)
             })
         }
     }
+
+    Device (IPC1)
+    {
+        Name (_ADR, 0x00130000)
+
+        Method (_STA, 0, NotSerialized)
+        {
+            Return (STA_VISIBLE)
+        }
+
+        Device (PMIC)
+        {
+            Name (_ADR, Zero)
+            Name (_HID, "INTC100E")
+            Name (_CID, "INTC100E")
+            Name (_DDN, "Basin Cove PMIC")
+            Name (_DEP, Package ()
+            {
+                IPC1
+            })
+
+            Method (_STA, 0, NotSerialized)
+            {
+                Return (STA_VISIBLE)
+            }
+
+            Method (_CRS, 0, Serialized)
+            {
+                Name (RBUF, ResourceTemplate()
+                {
+                    /*
+		     * Shadow registers in SRAM for PMIC:
+		     *   SRAM	PMIC register
+		     *   --------------------
+		     *   0x00-	Unknown
+		     *   0x03	THRMIRQ (0x04)
+		     *   0x04	BCUIRQ (0x05)
+		     *   0x05	ADCIRQ (0x06)
+		     *   0x06	CHGRIRQ0 (0x07)
+		     *   0x07	CHGRIRQ1 (0x08)
+		     *   0x08-	Unknown
+		     *   0x0a	PBSTATUS (0x27)
+		     *   0x0b-	Unknown
+		     */
+                    Memory32Fixed(ReadWrite, 0xFFFFF610, 0x00000010)
+                    Interrupt(ResourceConsumer, Level, ActiveHigh, Shared, ,, ) { 30 }
+                    Interrupt(ResourceConsumer, Level, ActiveHigh, Shared, ,, ) { 23 }
+                    Interrupt(ResourceConsumer, Level, ActiveHigh, Shared, ,, ) { 52 }
+                    Interrupt(ResourceConsumer, Level, ActiveHigh, Shared, ,, ) { 51 }
+                    Interrupt(ResourceConsumer, Level, ActiveHigh, Shared, ,, ) { 50 }
+                    Interrupt(ResourceConsumer, Level, ActiveHigh, Shared, ,, ) { 27 }
+                    Interrupt(ResourceConsumer, Level, ActiveHigh, Shared, ,, ) { 49 }
+                })
+                Return (RBUF)
+            }
+
+            OperationRegion (PMOP, 0x8D, Zero, 0x0100)
+            Field (PMOP, DWordAcc, NoLock, Preserve)
+            {
+                SEL1,   32,
+                SEL2,   32,
+                VCCL,   32,
+                VNNL,   32,
+                AONL,   32,
+                CNTC,   32,
+                CNTN,   32,
+                AONN,   32,
+                CNT1,   32,
+                CNT2,   32,
+                CNT3,   32,
+                FLEX,   32,
+                PRG1,   32,
+                PRG2,   32,
+                PRG3,   32,
+                VLDO,   32,
+            }
+
+            Name (AVBL, Zero)
+            Method (_REG, 2, NotSerialized)
+            {
+                If ((Arg0 == 0x8D))
+                {
+                    AVBL = Arg1
+                }
+            }
+        }
+    }
 }
 
 Device (FLIS)

configs/edison_defconfig

@@ -25,7 +25,7 @@ CONFIG_CMD_EXT4=y
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
-CONFIG_OF_EMBED=y
+CONFIG_OF_SEPARATE=y
 CONFIG_DEFAULT_DEVICE_TREE="edison"
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_CPU=y

doc/README.fdt-control

@@ -122,13 +122,14 @@ the U-Boot image (including u-boot.bin). This is suitable for debugging
 and development only and is not recommended for production devices.
 
 If CONFIG_OF_SEPARATE is defined, then it will be built and placed in
-a u-boot.dtb file alongside u-boot.bin. A common approach is then to
+a u-boot.dtb file alongside u-boot-nodtb.bin. A common approach is then to
 join the two:
 
-	cat u-boot.bin u-boot.dtb >image.bin
+	cat u-boot-nodtb.bin u-boot.dtb >image.bin
 
 and then flash image.bin onto your board. Note that U-Boot creates
-u-boot-dtb.bin which does the above step for you also. If you are using
+u-boot-dtb.bin which does the above step for you also. Resulting
+u-boot.bin is a copy of u-boot-dtb.bin in this case. If you are using
 CONFIG_SPL_FRAMEWORK, then u-boot.img will be built to include the device
 tree binary.
 

drivers/timer/tsc_timer.c

@@ -19,8 +19,59 @@
 
 #define MAX_NUM_FREQS	9
 
+#define INTEL_FAM6_SKYLAKE_MOBILE	0x4E
+#define INTEL_FAM6_ATOM_GOLDMONT	0x5C /* Apollo Lake */
+#define INTEL_FAM6_SKYLAKE_DESKTOP	0x5E
+#define INTEL_FAM6_ATOM_GOLDMONT_X	0x5F /* Denverton */
+#define INTEL_FAM6_KABYLAKE_MOBILE	0x8E
+#define INTEL_FAM6_KABYLAKE_DESKTOP	0x9E
+
 DECLARE_GLOBAL_DATA_PTR;
 
+/*
+ * native_calibrate_tsc
+ * Determine TSC frequency via CPUID, else return 0.
+ */
+static unsigned long native_calibrate_tsc(void)
+{
+	struct cpuid_result tsc_info;
+	unsigned int crystal_freq;
+
+	if (gd->arch.x86_vendor != X86_VENDOR_INTEL)
+		return 0;
+
+	if (cpuid_eax(0) < 0x15)
+		return 0;
+
+	tsc_info = cpuid(0x15);
+
+	if (tsc_info.ebx == 0 || tsc_info.eax == 0)
+		return 0;
+
+	crystal_freq = tsc_info.ecx / 1000;
+
+	if (!crystal_freq) {
+		switch (gd->arch.x86_model) {
+		case INTEL_FAM6_SKYLAKE_MOBILE:
+		case INTEL_FAM6_SKYLAKE_DESKTOP:
+		case INTEL_FAM6_KABYLAKE_MOBILE:
+		case INTEL_FAM6_KABYLAKE_DESKTOP:
+			crystal_freq = 24000;	/* 24.0 MHz */
+			break;
+		case INTEL_FAM6_ATOM_GOLDMONT_X:
+			crystal_freq = 25000;	/* 25.0 MHz */
+			break;
+		case INTEL_FAM6_ATOM_GOLDMONT:
+			crystal_freq = 19200;	/* 19.2 MHz */
+			break;
+		default:
+			return 0;
+		}
+	}
+
+	return (crystal_freq * tsc_info.ebx / tsc_info.eax) / 1000;
+}
+
 static unsigned long cpu_mhz_from_cpuid(void)
 {
 	if (gd->arch.x86_vendor != X86_VENDOR_INTEL)
@@ -350,6 +401,10 @@ static void tsc_timer_ensure_setup(bool early)
 	if (!gd->arch.clock_rate) {
 		unsigned long fast_calibrate;
 
+		fast_calibrate = native_calibrate_tsc();
+		if (fast_calibrate)
+			goto done;
+
 		fast_calibrate = cpu_mhz_from_cpuid();
 		if (fast_calibrate)
 			goto done;