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powerpc/85xx: Add TWR-P10xx board support
TWR-P1025 Specification: ----------------------- Memory subsystem: 512MB DDR3 (on board DDR) 64Mbyte 16bit NOR flash One microSD Card slot Ethernet: eTSEC1: Connected to Atheros AR8035 GETH PHY eTSEC3: Connected to Atheros AR8035 GETH PHY UART: Two UARTs are routed to the FDTI dual USB to RS232 convertor USB: Two USB2.0 Type A ports I2C: AT24C01B 1K Board EEPROM (8 bit address) QUICC Engine: Connected to DP83849i PHY supply two 10/100M ethernet ports QE UART for RS485 or RS232 PCIE: One mini-PCIE slot Signed-off-by: Michael Johnston <michael.johnston@freescale.com> Signed-off-by: Xie Xiaobo <X.Xie@freescale.com> [yorksun: Fixup include/configs/p1_twr.h] Signed-off-by: York Sun <yorksun@freescale.com>
This commit is contained in:
Xie Xiaobo
York Sun
parent
d05bfd0586
commit
49f5befafd
7 changed files with 1180 additions and 0 deletions
52
board/freescale/p1_twr/Makefile
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52
board/freescale/p1_twr/Makefile
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@ -0,0 +1,52 @@
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#
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# Copyright 2013 Freescale Semiconductor, Inc.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(BOARD).o
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COBJS-y += $(BOARD).o
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COBJS-y += ddr.o
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COBJS-y += law.o
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COBJS-y += tlb.o
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SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS-y))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(obj).depend $(OBJS) $(SOBJS)
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$(call cmd_link_o_target, $(OBJS))
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clean:
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rm -f $(OBJS) $(SOBJS)
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distclean: clean
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rm -f $(LIB) core *.bak .depend
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk
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sinclude $(obj).depend
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#########################################################################
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71
board/freescale/p1_twr/ddr.c
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71
board/freescale/p1_twr/ddr.c
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@ -0,0 +1,71 @@
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/*
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* Copyright 2013 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* Version 2 as published by the Free Software Foundation.
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*/
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#include <common.h>
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#include <asm/mmu.h>
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#include <asm/immap_85xx.h>
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#include <asm/processor.h>
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#include <asm/fsl_ddr_sdram.h>
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#include <asm/fsl_ddr_dimm_params.h>
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#include <asm/io.h>
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#include <asm/fsl_law.h>
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/* Fixed sdram init -- doesn't use serial presence detect. */
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phys_size_t fixed_sdram(void)
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{
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sys_info_t sysinfo;
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char buf[32];
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size_t ddr_size;
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fsl_ddr_cfg_regs_t ddr_cfg_regs = {
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.cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
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.cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
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.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
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#if CONFIG_CHIP_SELECTS_PER_CTRL > 1
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.cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS,
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.cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG,
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.cs[1].config_2 = CONFIG_SYS_DDR_CS1_CONFIG_2,
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#endif
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.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3,
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.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0,
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.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1,
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.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2,
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.ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
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.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
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.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1,
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.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2,
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.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
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.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL,
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.ddr_data_init = CONFIG_SYS_DDR_DATA_INIT,
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.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL,
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.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
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.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
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.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
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.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
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.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
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.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL,
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.ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
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.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
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.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
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};
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get_sys_info(&sysinfo);
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printf("Configuring DDR for %s MT/s data rate\n",
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strmhz(buf, sysinfo.freqDDRBus));
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ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
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fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0);
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if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
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ddr_size, LAW_TRGT_IF_DDR_1) < 0) {
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printf("ERROR setting Local Access Windows for DDR\n");
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return 0;
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};
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return ddr_size;
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}
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32
board/freescale/p1_twr/law.c
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32
board/freescale/p1_twr/law.c
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@ -0,0 +1,32 @@
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/*
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* Copyright 2013 Freescale Semiconductor, Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/fsl_law.h>
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#include <asm/mmu.h>
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struct law_entry law_table[] = {
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SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_64M, LAW_TRGT_IF_LBC),
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SET_LAW(CONFIG_SYS_SSD_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC)
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};
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int num_law_entries = ARRAY_SIZE(law_table);
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297
board/freescale/p1_twr/p1_twr.c
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297
board/freescale/p1_twr/p1_twr.c
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@ -0,0 +1,297 @@
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/*
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* Copyright 2013 Freescale Semiconductor, Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <command.h>
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#include <hwconfig.h>
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#include <pci.h>
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#include <i2c.h>
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#include <asm/processor.h>
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#include <asm/mmu.h>
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#include <asm/cache.h>
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#include <asm/immap_85xx.h>
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#include <asm/fsl_pci.h>
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#include <asm/fsl_ddr_sdram.h>
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#include <asm/io.h>
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#include <asm/fsl_law.h>
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#include <asm/fsl_lbc.h>
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#include <asm/mp.h>
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#include <miiphy.h>
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#include <libfdt.h>
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#include <fdt_support.h>
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#include <fsl_mdio.h>
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#include <tsec.h>
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#include <ioports.h>
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#include <asm/fsl_serdes.h>
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#include <netdev.h>
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#define SYSCLK_64 64000000
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#define SYSCLK_66 66666666
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unsigned long get_board_sys_clk(ulong dummy)
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{
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ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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par_io_t *par_io = (par_io_t *) &(gur->qe_par_io);
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unsigned int cpdat_val = 0;
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/* Set-up up pin muxing based on board switch settings */
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cpdat_val = par_io[1].cpdat;
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/* Check switch setting for SYSCLK select (PB3) */
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if (cpdat_val & 0x10000000)
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return SYSCLK_64;
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else
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return SYSCLK_66;
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return 0;
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}
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#ifdef CONFIG_QE
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#define PCA_IOPORT_I2C_ADDR 0x23
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#define PCA_IOPORT_OUTPUT_CMD 0x2
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#define PCA_IOPORT_CFG_CMD 0x6
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const qe_iop_conf_t qe_iop_conf_tab[] = {
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#ifdef CONFIG_TWR_P1025
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/* GPIO */
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{1, 0, 1, 0, 0},
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{1, 18, 1, 0, 0},
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/* GPIO for switch options */
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{1, 2, 2, 0, 0}, /* PROFIBUS_MODE_SEL */
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{1, 3, 2, 0, 0}, /* SYS_CLK_SELECT */
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{1, 29, 2, 0, 0}, /* LOCALBUS_QE_MUXSEL */
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{1, 30, 2, 0, 0}, /* ETH_TDM_SEL */
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/* QE_MUX_MDC */
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{1, 19, 1, 0, 1}, /* QE_MUX_MDC */
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/* QE_MUX_MDIO */
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{1, 20, 3, 0, 1}, /* QE_MUX_MDIO */
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/* UCC_1_MII */
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{0, 23, 2, 0, 2}, /* CLK12 */
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{0, 24, 2, 0, 1}, /* CLK9 */
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{0, 7, 1, 0, 2}, /* ENET1_TXD0_SER1_TXD0 */
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{0, 9, 1, 0, 2}, /* ENET1_TXD1_SER1_TXD1 */
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{0, 11, 1, 0, 2}, /* ENET1_TXD2_SER1_TXD2 */
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{0, 12, 1, 0, 2}, /* ENET1_TXD3_SER1_TXD3 */
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{0, 6, 2, 0, 2}, /* ENET1_RXD0_SER1_RXD0 */
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{0, 10, 2, 0, 2}, /* ENET1_RXD1_SER1_RXD1 */
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{0, 14, 2, 0, 2}, /* ENET1_RXD2_SER1_RXD2 */
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{0, 15, 2, 0, 2}, /* ENET1_RXD3_SER1_RXD3 */
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{0, 5, 1, 0, 2}, /* ENET1_TX_EN_SER1_RTS_B */
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{0, 13, 1, 0, 2}, /* ENET1_TX_ER */
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{0, 4, 2, 0, 2}, /* ENET1_RX_DV_SER1_CTS_B */
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{0, 8, 2, 0, 2}, /* ENET1_RX_ER_SER1_CD_B */
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{0, 17, 2, 0, 2}, /* ENET1_CRS */
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{0, 16, 2, 0, 2}, /* ENET1_COL */
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/* UCC_5_RMII */
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{1, 11, 2, 0, 1}, /* CLK13 */
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{1, 7, 1, 0, 2}, /* ENET5_TXD0_SER5_TXD0 */
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{1, 10, 1, 0, 2}, /* ENET5_TXD1_SER5_TXD1 */
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{1, 6, 2, 0, 2}, /* ENET5_RXD0_SER5_RXD0 */
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{1, 9, 2, 0, 2}, /* ENET5_RXD1_SER5_RXD1 */
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{1, 5, 1, 0, 2}, /* ENET5_TX_EN_SER5_RTS_B */
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{1, 4, 2, 0, 2}, /* ENET5_RX_DV_SER5_CTS_B */
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{1, 8, 2, 0, 2}, /* ENET5_RX_ER_SER5_CD_B */
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/* TDMA - clock option is configured in OS based on board setting */
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{1, 23, 2, 0, 2}, /* TDMA_TXD */
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{1, 25, 2, 0, 2}, /* TDMA_RXD */
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{1, 26, 1, 0, 2}, /* TDMA_SYNC */
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#endif
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{0, 0, 0, 0, QE_IOP_TAB_END} /* END of table */
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};
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#endif
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int board_early_init_f(void)
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{
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ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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setbits_be32(&gur->pmuxcr,
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(MPC85xx_PMUXCR_SDHC_CD | MPC85xx_PMUXCR_SDHC_WP));
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/* SDHC_DAT[4:7] not exposed to pins (use as SPI) */
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clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA);
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return 0;
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}
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int checkboard(void)
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{
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ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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u8 boot_status;
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printf("Board: %s\n", CONFIG_BOARDNAME);
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boot_status = ((gur->porbmsr) >> MPC85xx_PORBMSR_ROMLOC_SHIFT) & 0xf;
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puts("rom_loc: ");
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if (boot_status == PORBMSR_ROMLOC_NOR)
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puts("nor flash");
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else if (boot_status == PORBMSR_ROMLOC_SDHC)
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puts("sd");
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else
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puts("unknown");
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puts("\n");
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return 0;
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}
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#ifdef CONFIG_PCI
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void pci_init_board(void)
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{
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fsl_pcie_init_board(0);
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}
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#endif
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int board_early_init_r(void)
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{
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const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
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const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
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/*
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* Remap Boot flash region to caching-inhibited
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* so that flash can be erased properly.
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*/
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/* Flush d-cache and invalidate i-cache of any FLASH data */
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flush_dcache();
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invalidate_icache();
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/* invalidate existing TLB entry for flash */
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disable_tlb(flash_esel);
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set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */
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MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */
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0, flash_esel, BOOKE_PAGESZ_64M, 1);/* ts, esel, tsize, iprot */
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return 0;
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}
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int board_eth_init(bd_t *bis)
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{
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struct fsl_pq_mdio_info mdio_info;
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struct tsec_info_struct tsec_info[4];
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ccsr_gur_t *gur __attribute__((unused)) =
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(void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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int num = 0;
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#ifdef CONFIG_TSEC1
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SET_STD_TSEC_INFO(tsec_info[num], 1);
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num++;
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#endif
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#ifdef CONFIG_TSEC2
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SET_STD_TSEC_INFO(tsec_info[num], 2);
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if (is_serdes_configured(SGMII_TSEC2)) {
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printf("eTSEC2 is in sgmii mode.\n");
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tsec_info[num].flags |= TSEC_SGMII;
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}
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num++;
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#endif
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#ifdef CONFIG_TSEC3
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SET_STD_TSEC_INFO(tsec_info[num], 3);
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num++;
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#endif
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if (!num) {
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printf("No TSECs initialized\n");
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return 0;
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}
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mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
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mdio_info.name = DEFAULT_MII_NAME;
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fsl_pq_mdio_init(bis, &mdio_info);
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tsec_eth_init(bis, tsec_info, num);
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#if defined(CONFIG_UEC_ETH)
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/* QE0 and QE3 need to be exposed for UCC1
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* and UCC5 Eth mode (in PMUXCR register).
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* Currently QE/LBC muxed pins assumed to be
|
||||
* LBC for U-Boot and PMUXCR updated by OS if required */
|
||||
|
||||
uec_standard_init(bis);
|
||||
#endif
|
||||
|
||||
return pci_eth_init(bis);
|
||||
}
|
||||
|
||||
#if defined(CONFIG_QE)
|
||||
static void fdt_board_fixup_qe_pins(void *blob)
|
||||
{
|
||||
int node;
|
||||
|
||||
if (!hwconfig("qe")) {
|
||||
/* For QE and eLBC pins multiplexing,
|
||||
* When don't use QE function, remove
|
||||
* qe node from dt blob.
|
||||
*/
|
||||
node = fdt_path_offset(blob, "/qe");
|
||||
if (node >= 0)
|
||||
fdt_del_node(blob, node);
|
||||
} else {
|
||||
/* For TWR Peripheral Modules - TWR-SER2
|
||||
* board only can support Signal Port MII,
|
||||
* so delete one UEC node when use MII port.
|
||||
*/
|
||||
if (hwconfig("mii"))
|
||||
node = fdt_path_offset(blob, "/qe/ucc@2400");
|
||||
else
|
||||
node = fdt_path_offset(blob, "/qe/ucc@2000");
|
||||
if (node >= 0)
|
||||
fdt_del_node(blob, node);
|
||||
}
|
||||
|
||||
return;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_OF_BOARD_SETUP
|
||||
void ft_board_setup(void *blob, bd_t *bd)
|
||||
{
|
||||
phys_addr_t base;
|
||||
phys_size_t size;
|
||||
|
||||
ft_cpu_setup(blob, bd);
|
||||
|
||||
base = getenv_bootm_low();
|
||||
size = getenv_bootm_size();
|
||||
|
||||
fdt_fixup_memory(blob, (u64)base, (u64)size);
|
||||
|
||||
FT_FSL_PCI_SETUP;
|
||||
|
||||
#ifdef CONFIG_QE
|
||||
do_fixup_by_compat(blob, "fsl,qe", "status", "okay",
|
||||
sizeof("okay"), 0);
|
||||
#endif
|
||||
#if defined(CONFIG_TWR_P1025)
|
||||
fdt_board_fixup_qe_pins(blob);
|
||||
#endif
|
||||
fdt_fixup_dr_usb(blob, bd);
|
||||
}
|
||||
#endif
|
||||
92
board/freescale/p1_twr/tlb.c
Normal file
92
board/freescale/p1_twr/tlb.c
Normal file
|
|
@ -0,0 +1,92 @@
|
|||
/*
|
||||
* Copyright 2013 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/mmu.h>
|
||||
|
||||
struct fsl_e_tlb_entry tlb_table[] = {
|
||||
/* TLB 0 - for temp stack in cache */
|
||||
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
|
||||
CONFIG_SYS_INIT_RAM_ADDR_PHYS,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0,
|
||||
0, 0, BOOKE_PAGESZ_4K, 0),
|
||||
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 ,
|
||||
CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0,
|
||||
0, 0, BOOKE_PAGESZ_4K, 0),
|
||||
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 ,
|
||||
CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0,
|
||||
0, 0, BOOKE_PAGESZ_4K, 0),
|
||||
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 ,
|
||||
CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0,
|
||||
0, 0, BOOKE_PAGESZ_4K, 0),
|
||||
|
||||
/* TLB 1 */
|
||||
/* *I*** - Covers boot page */
|
||||
SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I,
|
||||
0, 0, BOOKE_PAGESZ_4K, 1),
|
||||
|
||||
/* *I*G* - CCSRBAR */
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
|
||||
MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 1, BOOKE_PAGESZ_1M, 1),
|
||||
|
||||
#ifndef CONFIG_SPL_BUILD
|
||||
/* W**G* - Flash, localbus */
|
||||
/* This will be changed to *I*G* after relocation to RAM. */
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
|
||||
MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
|
||||
0, 2, BOOKE_PAGESZ_64M, 1),
|
||||
|
||||
/* W**G* - Flash, localbus */
|
||||
/* This will be changed to *I*G* after relocation to RAM. */
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_SSD_BASE, CONFIG_SYS_SSD_BASE_PHYS,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 5, BOOKE_PAGESZ_1M, 1),
|
||||
|
||||
#ifdef CONFIG_PCI
|
||||
/* *I*G* - PCI memory 1.5G */
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
|
||||
MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 3, BOOKE_PAGESZ_1G, 1),
|
||||
|
||||
/* *I*G* - PCI I/O effective: 192K */
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
|
||||
MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 4, BOOKE_PAGESZ_256K, 1),
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SYS_RAMBOOT
|
||||
/* *I*G - eSDHC boot */
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0,
|
||||
0, 8, BOOKE_PAGESZ_1G, 1),
|
||||
#endif
|
||||
|
||||
};
|
||||
|
||||
int num_tlb_entries = ARRAY_SIZE(tlb_table);
|
||||
|
|
@ -848,6 +848,7 @@ P1025RDB_36BIT powerpc mpc85xx p1_p2_rdb_pc freesca
|
|||
P1025RDB_NAND powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1025RDB,NAND
|
||||
P1025RDB_SDCARD powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1025RDB,SDCARD
|
||||
P1025RDB_SPIFLASH powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1025RDB,SPIFLASH
|
||||
TWR-P1025 powerpc mpc85xx p1_twr freescale - p1_twr:TWR_P1025
|
||||
P2010RDB powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2010RDB
|
||||
P2010RDB_36BIT powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2010RDB,36BIT
|
||||
P2010RDB_36BIT_SDCARD powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2010RDB,36BIT,SDCARD
|
||||
|
|
|
|||
635
include/configs/p1_twr.h
Normal file
635
include/configs/p1_twr.h
Normal file
|
|
@ -0,0 +1,635 @@
|
|||
/*
|
||||
* Copyright 2013 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/*
|
||||
* QorIQ P1 Tower boards configuration file
|
||||
*/
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
#if defined(CONFIG_TWR_P1025)
|
||||
#define CONFIG_BOARDNAME "TWR-P1025"
|
||||
#define CONFIG_P1025
|
||||
#define CONFIG_PHY_ATHEROS
|
||||
#define CONFIG_QE
|
||||
#define CONFIG_SYS_LBC_LBCR 0x00080000 /* Conversion of LBC addr */
|
||||
#define CONFIG_SYS_LBC_LCRR 0x80000002 /* LB clock ratio reg */
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SDCARD
|
||||
#define CONFIG_RAMBOOT_SDCARD
|
||||
#define CONFIG_SYS_RAMBOOT
|
||||
#define CONFIG_SYS_EXTRA_ENV_RELOC
|
||||
#define CONFIG_SYS_TEXT_BASE 0x11000000
|
||||
#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_SYS_TEXT_BASE
|
||||
#define CONFIG_SYS_TEXT_BASE 0xeff80000
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_RESET_VECTOR_ADDRESS
|
||||
#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_SYS_MONITOR_BASE
|
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
|
||||
#endif
|
||||
|
||||
/* High Level Configuration Options */
|
||||
#define CONFIG_BOOKE
|
||||
#define CONFIG_E500
|
||||
#define CONFIG_MPC85xx
|
||||
|
||||
#define CONFIG_MP
|
||||
|
||||
#define CONFIG_FSL_ELBC
|
||||
#define CONFIG_PCI
|
||||
#define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */
|
||||
#define CONFIG_PCIE2 /* PCIE controler 2 (slot 2) */
|
||||
#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
|
||||
#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
|
||||
#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
|
||||
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
|
||||
|
||||
#define CONFIG_FSL_LAW
|
||||
#define CONFIG_TSEC_ENET /* tsec ethernet support */
|
||||
#define CONFIG_ENV_OVERWRITE
|
||||
|
||||
#define CONFIG_CMD_SATA
|
||||
#define CONFIG_SATA_SIL3114
|
||||
#define CONFIG_SYS_SATA_MAX_DEVICE 2
|
||||
#define CONFIG_LIBATA
|
||||
#define CONFIG_LBA48
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
extern unsigned long get_board_sys_clk(unsigned long dummy);
|
||||
#endif
|
||||
#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /*sysclk for TWR-P1025 */
|
||||
|
||||
#define CONFIG_DDR_CLK_FREQ 66666666
|
||||
|
||||
#define CONFIG_HWCONFIG
|
||||
/*
|
||||
* These can be toggled for performance analysis, otherwise use default.
|
||||
*/
|
||||
#define CONFIG_L2_CACHE
|
||||
#define CONFIG_BTB
|
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */
|
||||
|
||||
#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
|
||||
#define CONFIG_SYS_MEMTEST_END 0x1fffffff
|
||||
#define CONFIG_PANIC_HANG /* do not reset board on panic */
|
||||
|
||||
#define CONFIG_SYS_CCSRBAR 0xffe00000
|
||||
#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
|
||||
|
||||
/* DDR Setup */
|
||||
#define CONFIG_FSL_DDR3
|
||||
|
||||
#define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_512M
|
||||
#define CONFIG_CHIP_SELECTS_PER_CTRL 1
|
||||
|
||||
#define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19))
|
||||
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
|
||||
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
|
||||
|
||||
#define CONFIG_NUM_DDR_CONTROLLERS 1
|
||||
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
|
||||
|
||||
/* Default settings for DDR3 */
|
||||
#define CONFIG_SYS_DDR_CS0_BNDS 0x0000001f
|
||||
#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202
|
||||
#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
|
||||
#define CONFIG_SYS_DDR_CS1_BNDS 0x00000000
|
||||
#define CONFIG_SYS_DDR_CS1_CONFIG 0x00000000
|
||||
#define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000
|
||||
|
||||
#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
|
||||
#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
|
||||
#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
|
||||
#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
|
||||
|
||||
#define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
|
||||
#define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655a608
|
||||
#define CONFIG_SYS_DDR_SR_CNTR 0x00000000
|
||||
#define CONFIG_SYS_DDR_RCW_1 0x00000000
|
||||
#define CONFIG_SYS_DDR_RCW_2 0x00000000
|
||||
#define CONFIG_SYS_DDR_CONTROL 0xc70c0000 /* Type = DDR3 */
|
||||
#define CONFIG_SYS_DDR_CONTROL_2 0x04401050
|
||||
#define CONFIG_SYS_DDR_TIMING_4 0x00220001
|
||||
#define CONFIG_SYS_DDR_TIMING_5 0x03402400
|
||||
|
||||
#define CONFIG_SYS_DDR_TIMING_3 0x00020000
|
||||
#define CONFIG_SYS_DDR_TIMING_0 0x00220004
|
||||
#define CONFIG_SYS_DDR_TIMING_1 0x5c5b6544
|
||||
#define CONFIG_SYS_DDR_TIMING_2 0x0fa880de
|
||||
#define CONFIG_SYS_DDR_CLK_CTRL 0x03000000
|
||||
#define CONFIG_SYS_DDR_MODE_1 0x80461320
|
||||
#define CONFIG_SYS_DDR_MODE_2 0x00008000
|
||||
#define CONFIG_SYS_DDR_INTERVAL 0x09480000
|
||||
|
||||
/*
|
||||
* Memory map
|
||||
*
|
||||
* 0x0000_0000 0x1fff_ffff DDR Up to 512MB cacheable
|
||||
* 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable(PCIe * 3)
|
||||
* 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable
|
||||
*
|
||||
* Localbus
|
||||
* 0xe000_0000 0xe002_0000 SSD1289 128K non-cacheable
|
||||
* 0xec00_0000 0xefff_ffff FLASH Up to 64M non-cacheable
|
||||
*
|
||||
* 0xff90_0000 0xff97_ffff L2 SRAM Up to 512K cacheable
|
||||
* 0xffd0_0000 0xffd0_3fff init ram 16K Cacheable
|
||||
* 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
|
||||
*/
|
||||
|
||||
/*
|
||||
* Local Bus Definitions
|
||||
*/
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */
|
||||
#define CONFIG_SYS_FLASH_BASE 0xec000000
|
||||
|
||||
#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
|
||||
|
||||
#define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS)) \
|
||||
| BR_PS_16 | BR_V)
|
||||
|
||||
#define CONFIG_FLASH_OR_PRELIM 0xfc0000b1
|
||||
|
||||
#define CONFIG_SYS_SSD_BASE 0xe0000000
|
||||
#define CONFIG_SYS_SSD_BASE_PHYS CONFIG_SYS_SSD_BASE
|
||||
#define CONFIG_SSD_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_SSD_BASE_PHYS) | \
|
||||
BR_PS_16 | BR_V)
|
||||
#define CONFIG_SSD_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
|
||||
OR_GPCM_ACS_DIV2 | OR_GPCM_SCY | \
|
||||
OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
|
||||
|
||||
#define CONFIG_SYS_BR2_PRELIM CONFIG_SSD_BR_PRELIM
|
||||
#define CONFIG_SYS_OR2_PRELIM CONFIG_SSD_OR_PRELIM
|
||||
|
||||
#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
|
||||
#define CONFIG_SYS_FLASH_QUIET_TEST
|
||||
#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
|
||||
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
|
||||
|
||||
#undef CONFIG_SYS_FLASH_CHECKSUM
|
||||
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
|
||||
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
|
||||
|
||||
#define CONFIG_FLASH_CFI_DRIVER
|
||||
#define CONFIG_SYS_FLASH_CFI
|
||||
#define CONFIG_SYS_FLASH_EMPTY_INFO
|
||||
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
|
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
|
||||
|
||||
#define CONFIG_SYS_INIT_RAM_LOCK
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000
|
||||
/* Initial L1 address */
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
|
||||
/* Size of used area in RAM */
|
||||
#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
|
||||
|
||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
|
||||
GENERATED_GBL_DATA_SIZE)
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
|
||||
|
||||
#define CONFIG_SYS_MONITOR_LEN (512 * 1024)/* Reserve 512 kB for Mon */
|
||||
#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */
|
||||
|
||||
#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
|
||||
#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
|
||||
|
||||
/* Serial Port
|
||||
* open - index 2
|
||||
* shorted - index 1
|
||||
*/
|
||||
#define CONFIG_CONS_INDEX 1
|
||||
#undef CONFIG_SERIAL_SOFTWARE_FIFO
|
||||
#define CONFIG_SYS_NS16550
|
||||
#define CONFIG_SYS_NS16550_SERIAL
|
||||
#define CONFIG_SYS_NS16550_REG_SIZE 1
|
||||
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
|
||||
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE \
|
||||
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
|
||||
|
||||
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
|
||||
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
|
||||
|
||||
/* Use the HUSH parser */
|
||||
#define CONFIG_SYS_HUSH_PARSER
|
||||
#ifdef CONFIG_SYS_HUSH_PARSER
|
||||
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Pass open firmware flat tree
|
||||
*/
|
||||
#define CONFIG_OF_LIBFDT
|
||||
#define CONFIG_OF_BOARD_SETUP
|
||||
#define CONFIG_OF_STDOUT_VIA_ALIAS
|
||||
|
||||
#define CONFIG_SYS_64BIT_VSPRINTF
|
||||
#define CONFIG_SYS_64BIT_STRTOUL
|
||||
|
||||
/* new uImage format support */
|
||||
#define CONFIG_FIT
|
||||
#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
|
||||
|
||||
/* I2C */
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */
|
||||
#define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C spd and slave address */
|
||||
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
|
||||
|
||||
/*
|
||||
* I2C2 EEPROM
|
||||
*/
|
||||
#define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C spd and slave address */
|
||||
#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
|
||||
#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
|
||||
|
||||
#define CONFIG_SYS_I2C_PCA9555_ADDR 0x23
|
||||
|
||||
/* enable read and write access to EEPROM */
|
||||
#define CONFIG_CMD_EEPROM
|
||||
#define CONFIG_SYS_I2C_MULTI_EEPROMS
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
|
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
|
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
|
||||
|
||||
/*
|
||||
* eSPI - Enhanced SPI
|
||||
*/
|
||||
#define CONFIG_HARD_SPI
|
||||
#define CONFIG_FSL_ESPI
|
||||
|
||||
#if defined(CONFIG_PCI)
|
||||
/*
|
||||
* General PCI
|
||||
* Memory space is mapped 1-1, but I/O space must start from 0.
|
||||
*/
|
||||
|
||||
/* controller 2, direct to uli, tgtid 2, Base address 9000 */
|
||||
#define CONFIG_SYS_PCIE2_NAME "TWR-ELEV PCIe SLOT"
|
||||
#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
|
||||
#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
|
||||
#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
|
||||
#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
|
||||
#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
|
||||
#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
|
||||
#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
|
||||
#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
|
||||
|
||||
/* controller 1, tgtid 1, Base address a000 */
|
||||
#define CONFIG_SYS_PCIE1_NAME "mini PCIe SLOT"
|
||||
#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
|
||||
#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
|
||||
#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
|
||||
#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
|
||||
#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
|
||||
#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
|
||||
#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000
|
||||
#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
|
||||
|
||||
#define CONFIG_NET_MULTI
|
||||
#define CONFIG_PCI_PNP /* do pci plug-and-play */
|
||||
#define CONFIG_E1000 /* Defind e1000 pci Ethernet card*/
|
||||
#define CONFIG_CMD_PCI
|
||||
#define CONFIG_CMD_NET
|
||||
|
||||
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
|
||||
#define CONFIG_DOS_PARTITION
|
||||
#endif /* CONFIG_PCI */
|
||||
|
||||
#if defined(CONFIG_TSEC_ENET)
|
||||
|
||||
#ifndef CONFIG_NET_MULTI
|
||||
#define CONFIG_NET_MULTI
|
||||
#endif
|
||||
|
||||
#define CONFIG_MII /* MII PHY management */
|
||||
#define CONFIG_TSEC1
|
||||
#define CONFIG_TSEC1_NAME "eTSEC1"
|
||||
#undef CONFIG_TSEC2
|
||||
#undef CONFIG_TSEC2_NAME
|
||||
#define CONFIG_TSEC3
|
||||
#define CONFIG_TSEC3_NAME "eTSEC3"
|
||||
|
||||
#define TSEC1_PHY_ADDR 2
|
||||
#define TSEC2_PHY_ADDR 0
|
||||
#define TSEC3_PHY_ADDR 1
|
||||
|
||||
#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
|
||||
#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
|
||||
#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
|
||||
|
||||
#define TSEC1_PHYIDX 0
|
||||
#define TSEC2_PHYIDX 0
|
||||
#define TSEC3_PHYIDX 0
|
||||
|
||||
#define CONFIG_ETHPRIME "eTSEC1"
|
||||
|
||||
#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
|
||||
|
||||
#define CONFIG_HAS_ETH0
|
||||
#define CONFIG_HAS_ETH1
|
||||
#undef CONFIG_HAS_ETH2
|
||||
#endif /* CONFIG_TSEC_ENET */
|
||||
|
||||
#ifdef CONFIG_QE
|
||||
/* QE microcode/firmware address */
|
||||
#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
|
||||
#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xefec0000
|
||||
#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
|
||||
#endif /* CONFIG_QE */
|
||||
|
||||
#ifdef CONFIG_TWR_P1025
|
||||
/*
|
||||
* QE UEC ethernet configuration
|
||||
*/
|
||||
#define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120)
|
||||
|
||||
#undef CONFIG_UEC_ETH
|
||||
#define CONFIG_PHY_MODE_NEED_CHANGE
|
||||
|
||||
#define CONFIG_UEC_ETH1 /* ETH1 */
|
||||
#define CONFIG_HAS_ETH0
|
||||
|
||||
#ifdef CONFIG_UEC_ETH1
|
||||
#define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */
|
||||
#define CONFIG_SYS_UEC1_RX_CLK QE_CLK12 /* CLK12 for MII */
|
||||
#define CONFIG_SYS_UEC1_TX_CLK QE_CLK9 /* CLK9 for MII */
|
||||
#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
|
||||
#define CONFIG_SYS_UEC1_PHY_ADDR 0x18 /* 0x18 for MII */
|
||||
#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_MII
|
||||
#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
|
||||
#endif /* CONFIG_UEC_ETH1 */
|
||||
|
||||
#define CONFIG_UEC_ETH5 /* ETH5 */
|
||||
#define CONFIG_HAS_ETH1
|
||||
|
||||
#ifdef CONFIG_UEC_ETH5
|
||||
#define CONFIG_SYS_UEC5_UCC_NUM 4 /* UCC5 */
|
||||
#define CONFIG_SYS_UEC5_RX_CLK QE_CLK_NONE
|
||||
#define CONFIG_SYS_UEC5_TX_CLK QE_CLK13 /* CLK 13 for RMII */
|
||||
#define CONFIG_SYS_UEC5_ETH_TYPE FAST_ETH
|
||||
#define CONFIG_SYS_UEC5_PHY_ADDR 0x19 /* 0x19 for RMII */
|
||||
#define CONFIG_SYS_UEC5_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
|
||||
#define CONFIG_SYS_UEC5_INTERFACE_SPEED 100
|
||||
#endif /* CONFIG_UEC_ETH5 */
|
||||
#endif /* CONFIG_TWR-P1025 */
|
||||
|
||||
/*
|
||||
* Environment
|
||||
*/
|
||||
#ifdef CONFIG_SYS_RAMBOOT
|
||||
#ifdef CONFIG_RAMBOOT_SDCARD
|
||||
#define CONFIG_ENV_IS_IN_MMC
|
||||
#define CONFIG_ENV_SIZE 0x2000
|
||||
#define CONFIG_SYS_MMC_ENV_DEV 0
|
||||
#else
|
||||
#define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
|
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
|
||||
#define CONFIG_ENV_SIZE 0x2000
|
||||
#endif
|
||||
#else
|
||||
#define CONFIG_ENV_IS_IN_FLASH
|
||||
#if CONFIG_SYS_MONITOR_BASE > 0xfff80000
|
||||
#define CONFIG_ENV_ADDR 0xfff80000
|
||||
#else
|
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
|
||||
#endif
|
||||
#define CONFIG_ENV_SIZE 0x2000
|
||||
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
|
||||
#endif
|
||||
|
||||
#define CONFIG_LOADS_ECHO /* echo on for serial download */
|
||||
#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
|
||||
|
||||
/*
|
||||
* Command line configuration.
|
||||
*/
|
||||
#include <config_cmd_default.h>
|
||||
|
||||
#define CONFIG_CMD_IRQ
|
||||
#define CONFIG_CMD_PING
|
||||
#define CONFIG_CMD_I2C
|
||||
#define CONFIG_CMD_MII
|
||||
#define CONFIG_CMD_ELF
|
||||
#define CONFIG_CMD_SETEXPR
|
||||
#define CONFIG_CMD_REGINFO
|
||||
|
||||
/*
|
||||
* USB
|
||||
*/
|
||||
#define CONFIG_HAS_FSL_DR_USB
|
||||
|
||||
#if defined(CONFIG_HAS_FSL_DR_USB)
|
||||
#define CONFIG_USB_EHCI
|
||||
|
||||
#ifdef CONFIG_USB_EHCI
|
||||
#define CONFIG_CMD_USB
|
||||
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
|
||||
#define CONFIG_USB_EHCI_FSL
|
||||
#define CONFIG_USB_STORAGE
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#define CONFIG_MMC
|
||||
|
||||
#ifdef CONFIG_MMC
|
||||
#define CONFIG_FSL_ESDHC
|
||||
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
|
||||
#define CONFIG_CMD_MMC
|
||||
#define CONFIG_GENERIC_MMC
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) \
|
||||
|| defined(CONFIG_FSL_SATA)
|
||||
#define CONFIG_CMD_EXT2
|
||||
#define CONFIG_CMD_FAT
|
||||
#define CONFIG_DOS_PARTITION
|
||||
#endif
|
||||
|
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */
|
||||
#define CONFIG_CMDLINE_EDITING /* Command-line editing */
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
|
||||
#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
|
||||
#if defined(CONFIG_CMD_KGDB)
|
||||
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
|
||||
#else
|
||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
#endif
|
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
|
||||
/* Print Buffer Size */
|
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
|
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
|
||||
#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms tick */
|
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data
|
||||
* have to be in the first 64 MB of memory, since this is
|
||||
* the maximum mapped by the Linux kernel during initialization.
|
||||
*/
|
||||
#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/
|
||||
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
|
||||
|
||||
/*
|
||||
* Environment Configuration
|
||||
*/
|
||||
#define CONFIG_HOSTNAME unknown
|
||||
#define CONFIG_ROOTPATH "/opt/nfsroot"
|
||||
#define CONFIG_BOOTFILE "uImage"
|
||||
#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
|
||||
|
||||
/* default location for tftp and bootm */
|
||||
#define CONFIG_LOADADDR 1000000
|
||||
|
||||
#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
|
||||
#define CONFIG_BOOTARGS /* the boot command will set bootargs */
|
||||
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"netdev=eth0\0" \
|
||||
"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
|
||||
"loadaddr=1000000\0" \
|
||||
"bootfile=uImage\0" \
|
||||
"dtbfile=twr-p1025twr.dtb\0" \
|
||||
"ramdiskfile=rootfs.ext2.gz.uboot\0" \
|
||||
"qefirmwarefile=fsl_qe_ucode_1021_10_A.bin\0" \
|
||||
"tftpflash=tftpboot $loadaddr $uboot; " \
|
||||
"protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
|
||||
"erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
|
||||
"cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \
|
||||
"protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
|
||||
"cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
|
||||
"kernelflash=tftpboot $loadaddr $bootfile; " \
|
||||
"protect off 0xefa80000 +$filesize; " \
|
||||
"erase 0xefa80000 +$filesize; " \
|
||||
"cp.b $loadaddr 0xefa80000 $filesize; " \
|
||||
"protect on 0xefa80000 +$filesize; " \
|
||||
"cmp.b $loadaddr 0xefa80000 $filesize\0" \
|
||||
"dtbflash=tftpboot $loadaddr $dtbfile; " \
|
||||
"protect off 0xefe80000 +$filesize; " \
|
||||
"erase 0xefe80000 +$filesize; " \
|
||||
"cp.b $loadaddr 0xefe80000 $filesize; " \
|
||||
"protect on 0xefe80000 +$filesize; " \
|
||||
"cmp.b $loadaddr 0xefe80000 $filesize\0" \
|
||||
"ramdiskflash=tftpboot $loadaddr $ramdiskfile; " \
|
||||
"protect off 0xeeb80000 +$filesize; " \
|
||||
"erase 0xeeb80000 +$filesize; " \
|
||||
"cp.b $loadaddr 0xeeb80000 $filesize; " \
|
||||
"protect on 0xeeb80000 +$filesize; " \
|
||||
"cmp.b $loadaddr 0xeeb80000 $filesize\0" \
|
||||
"qefirmwareflash=tftpboot $loadaddr $qefirmwarefile; " \
|
||||
"protect off 0xefec0000 +$filesize; " \
|
||||
"erase 0xefec0000 +$filesize; " \
|
||||
"cp.b $loadaddr 0xefec0000 $filesize; " \
|
||||
"protect on 0xefec0000 +$filesize; " \
|
||||
"cmp.b $loadaddr 0xefec0000 $filesize\0" \
|
||||
"consoledev=ttyS0\0" \
|
||||
"ramdiskaddr=2000000\0" \
|
||||
"ramdiskfile=rootfs.ext2.gz.uboot\0" \
|
||||
"fdtaddr=c00000\0" \
|
||||
"bdev=sda1\0" \
|
||||
"norbootaddr=ef080000\0" \
|
||||
"norfdtaddr=ef040000\0" \
|
||||
"ramdisk_size=120000\0" \
|
||||
"usbboot=setenv bootargs root=/dev/sda1 rw rootdelay=5 " \
|
||||
"console=$consoledev,$baudrate $othbootargs ; bootm 0xefa80000 - 0xefe80000"
|
||||
|
||||
#define CONFIG_NFSBOOTCOMMAND \
|
||||
"setenv bootargs root=/dev/nfs rw " \
|
||||
"nfsroot=$serverip:$rootpath " \
|
||||
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
|
||||
"console=$consoledev,$baudrate $othbootargs;" \
|
||||
"tftp $loadaddr $bootfile&&" \
|
||||
"tftp $fdtaddr $fdtfile&&" \
|
||||
"bootm $loadaddr - $fdtaddr"
|
||||
|
||||
#define CONFIG_HDBOOT \
|
||||
"setenv bootargs root=/dev/$bdev rw rootdelay=30 " \
|
||||
"console=$consoledev,$baudrate $othbootargs;" \
|
||||
"usb start;" \
|
||||
"ext2load usb 0:1 $loadaddr /boot/$bootfile;" \
|
||||
"ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \
|
||||
"bootm $loadaddr - $fdtaddr"
|
||||
|
||||
#define CONFIG_USB_FAT_BOOT \
|
||||
"setenv bootargs root=/dev/ram rw " \
|
||||
"console=$consoledev,$baudrate $othbootargs " \
|
||||
"ramdisk_size=$ramdisk_size;" \
|
||||
"usb start;" \
|
||||
"fatload usb 0:2 $loadaddr $bootfile;" \
|
||||
"fatload usb 0:2 $fdtaddr $fdtfile;" \
|
||||
"fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \
|
||||
"bootm $loadaddr $ramdiskaddr $fdtaddr"
|
||||
|
||||
#define CONFIG_USB_EXT2_BOOT \
|
||||
"setenv bootargs root=/dev/ram rw " \
|
||||
"console=$consoledev,$baudrate $othbootargs " \
|
||||
"ramdisk_size=$ramdisk_size;" \
|
||||
"usb start;" \
|
||||
"ext2load usb 0:4 $loadaddr $bootfile;" \
|
||||
"ext2load usb 0:4 $fdtaddr $fdtfile;" \
|
||||
"ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
|
||||
"bootm $loadaddr $ramdiskaddr $fdtaddr"
|
||||
|
||||
#define CONFIG_NORBOOT \
|
||||
"setenv bootargs root=/dev/mtdblock3 rw " \
|
||||
"console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \
|
||||
"bootm $norbootaddr - $norfdtaddr"
|
||||
|
||||
#define CONFIG_RAMBOOTCOMMAND_TFTP \
|
||||
"setenv bootargs root=/dev/ram rw " \
|
||||
"console=$consoledev,$baudrate $othbootargs " \
|
||||
"ramdisk_size=$ramdisk_size;" \
|
||||
"tftp $ramdiskaddr $ramdiskfile;" \
|
||||
"tftp $loadaddr $bootfile;" \
|
||||
"tftp $fdtaddr $fdtfile;" \
|
||||
"bootm $loadaddr $ramdiskaddr $fdtaddr"
|
||||
|
||||
#define CONFIG_RAMBOOTCOMMAND \
|
||||
"setenv bootargs root=/dev/ram rw " \
|
||||
"console=$consoledev,$baudrate $othbootargs " \
|
||||
"ramdisk_size=$ramdisk_size;" \
|
||||
"bootm 0xefa80000 0xeeb80000 0xefe80000"
|
||||
|
||||
#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
Loading…
Add table
Reference in a new issue