mirror of
https://github.com/Fishwaldo/u-boot.git
synced 2025-03-21 14:41:31 +00:00
Merge with /home/wd/git/u-boot/custodian/u-boot-nand-flash
This commit is contained in:
Wolfgang Denk
commit
4a3c7eb917
31 changed files with 240 additions and 468 deletions
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@ -28,7 +28,9 @@ endif
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|||
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LIB = $(obj)lib$(BOARD).a
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COBJS = $(BOARD).o flash.o ../common/misc.o
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COBJS = $(BOARD).o flash.o \
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../common/misc.o \
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../common/esd405ep_nand.o \
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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@ -23,6 +23,7 @@
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#include <common.h>
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#include <asm/processor.h>
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#include <asm/io.h>
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#include <command.h>
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#include <malloc.h>
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@ -33,6 +34,7 @@
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#endif
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extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
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extern void lxt971_no_sleep(void);
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/* fpga configuration data - gzip compressed and generated by bin2c */
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const unsigned char fpgadata[] =
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@ -164,17 +166,11 @@ int misc_init_r (void)
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/*
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* Reset external DUARTs
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*/
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out32(GPIO0_OR, in32(GPIO0_OR) | CFG_DUART_RST); /* set reset to high */
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out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_DUART_RST);
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udelay(10); /* wait 10us */
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out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_DUART_RST); /* set reset to low */
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out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_DUART_RST);
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udelay(1000); /* wait 1ms */
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/*
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* Set NAND-FLASH GPIO signals to default
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*/
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out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE));
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out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);
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/*
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* Enable interrupts in exar duart mcr[3]
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*/
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@ -218,35 +214,17 @@ long int initdram (int board_type)
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mtdcr(memcfga, mem_mb0cf);
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val = mfdcr(memcfgd);
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#if 0
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printf("\nmb0cf=%x\n", val); /* test-only */
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printf("strap=%x\n", mfdcr(strap)); /* test-only */
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#endif
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return (4*1024*1024 << ((val & 0x000e0000) >> 17));
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}
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/* ------------------------------------------------------------------------- */
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int testdram (void)
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void reset_phy(void)
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{
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/* TODO: XXX XXX XXX */
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printf ("test: 16 MB - ok\n");
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return (0);
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}
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/* ------------------------------------------------------------------------- */
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#if defined(CONFIG_CMD_NAND)
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#include <linux/mtd/nand_legacy.h>
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extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
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void nand_init(void)
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{
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nand_probe(CFG_NAND_BASE);
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if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
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print_size(nand_dev_desc[0].totlen, "\n");
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}
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}
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#ifdef CONFIG_LXT971_NO_SLEEP
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/*
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* Disable sleep mode in LXT971
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*/
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lxt971_no_sleep();
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#endif
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}
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@ -33,7 +33,10 @@ CPLD = ../common/xilinx_jtag/lenval.o \
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../common/xilinx_jtag/micro.o \
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../common/xilinx_jtag/ports.o
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COBJS = $(BOARD).o flash.o ../common/misc.o $(CPLD)
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COBJS = $(BOARD).o flash.o \
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../common/misc.o \
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$(CPLD) \
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../common/esd405ep_nand.o \
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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@ -1,5 +1,5 @@
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/*
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* (C) Copyright 2005
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* (C) Copyright 2005-2007
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* Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
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*
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* See file CREDITS for list of people who contributed to this
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@ -23,6 +23,7 @@
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#include <common.h>
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#include <asm/processor.h>
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#include <asm/io.h>
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#include <command.h>
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#include <malloc.h>
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@ -68,9 +69,9 @@ int board_early_init_f (void)
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/*
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* Reset CPLD via GPIO12 (CS3) pin
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*/
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out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_PLD_RESET);
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out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_PLD_RESET);
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udelay(1000); /* wait 1ms */
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out32(GPIO0_OR, in32(GPIO0_OR) | CFG_PLD_RESET);
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out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_PLD_RESET);
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udelay(1000); /* wait 1ms */
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return 0;
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@ -94,13 +95,7 @@ int misc_init_r (void)
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/*
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* Setup and enable EEPROM write protection
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*/
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out32(GPIO0_OR, in32(GPIO0_OR) | CFG_EEPROM_WP);
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/*
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* Set NAND-FLASH GPIO signals to default
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*/
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out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE));
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out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);
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out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_EEPROM_WP);
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return (0);
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}
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@ -153,11 +148,6 @@ long int initdram (int board_type)
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mtdcr(memcfga, mem_mb0cf);
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val = mfdcr(memcfgd);
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#if 0
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printf("\nmb0cf=%x\n", val); /* test-only */
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printf("strap=%x\n", mfdcr(strap)); /* test-only */
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#endif
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return (4*1024*1024 << ((val & 0x000e0000) >> 17));
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}
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@ -180,17 +170,17 @@ int eeprom_write_enable (unsigned dev_addr, int state)
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switch (state) {
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case 1:
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/* Enable write access, clear bit GPIO_SINT2. */
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out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_EEPROM_WP);
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out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_EEPROM_WP);
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state = 0;
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break;
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case 0:
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/* Disable write access, set bit GPIO_SINT2. */
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out32(GPIO0_OR, in32(GPIO0_OR) | CFG_EEPROM_WP);
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out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_EEPROM_WP);
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state = 0;
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break;
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default:
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/* Read current status back. */
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state = (0 == (in32(GPIO0_OR) & CFG_EEPROM_WP));
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state = (0 == (in_be32((void *)GPIO0_OR) & CFG_EEPROM_WP));
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break;
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}
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}
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@ -235,19 +225,6 @@ U_BOOT_CMD(eepwren, 2, 0, do_eep_wren,
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/* ------------------------------------------------------------------------- */
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#if defined(CONFIG_CMD_NAND)
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#include <linux/mtd/nand_legacy.h>
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extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
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void nand_init(void)
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{
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nand_probe(CFG_NAND_BASE);
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if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
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print_size(nand_dev_desc[0].totlen, "\n");
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}
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}
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#endif
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void reset_phy(void)
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{
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#ifdef CONFIG_LXT971_NO_SLEEP
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@ -31,7 +31,9 @@
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#include <command.h>
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#include <image.h>
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#include <asm/byteorder.h>
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#if defined(CFG_NAND_LEGACY)
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#include <linux/mtd/nand_legacy.h>
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#endif
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#include <fat.h>
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#include <part.h>
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@ -294,6 +296,8 @@ int au_do_update(int i, long sz)
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rc = nand_legacy_rw(nand_dev_desc, NANDRW_WRITE | NANDRW_JFFS2,
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start, nbytes, (size_t *)&total, (uchar *)addr);
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debug ("nand_legacy_rw: ret=%x total=%d nbytes=%d\n", rc, total, nbytes);
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#else
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rc = -1;
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#endif
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}
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if (rc != 0) {
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87
board/esd/common/esd405ep_nand.c
Normal file
87
board/esd/common/esd405ep_nand.c
Normal file
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@ -0,0 +1,87 @@
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/*
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* (C) Copyright 2007
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* Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
|
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#if defined(CONFIG_CMD_NAND)
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#include <asm/io.h>
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#include <nand.h>
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/*
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* hardware specific access to control-lines
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*/
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static void esd405ep_nand_hwcontrol(struct mtd_info *mtdinfo, int cmd)
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{
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switch(cmd) {
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case NAND_CTL_SETCLE:
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out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_NAND_CLE);
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break;
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case NAND_CTL_CLRCLE:
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out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_NAND_CLE);
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break;
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case NAND_CTL_SETALE:
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out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_NAND_ALE);
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break;
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case NAND_CTL_CLRALE:
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out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_NAND_ALE);
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break;
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case NAND_CTL_SETNCE:
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out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_NAND_CE);
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break;
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case NAND_CTL_CLRNCE:
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out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_NAND_CE);
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break;
|
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}
|
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}
|
||||
|
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|
||||
/*
|
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* read device ready pin
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*/
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static int esd405ep_nand_device_ready(struct mtd_info *mtdinfo)
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{
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if (in_be32((void *)GPIO0_IR) & CFG_NAND_RDY)
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return 1;
|
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return 0;
|
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}
|
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|
||||
|
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int board_nand_init(struct nand_chip *nand)
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{
|
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/*
|
||||
* Set NAND-FLASH GPIO signals to defaults
|
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*/
|
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out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE));
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out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_NAND_CE);
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|
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/*
|
||||
* Initialize nand_chip structure
|
||||
*/
|
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nand->hwcontrol = esd405ep_nand_hwcontrol;
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nand->dev_ready = esd405ep_nand_device_ready;
|
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nand->eccmode = NAND_ECC_SOFT;
|
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nand->chip_delay = NAND_BIG_DELAY_US;
|
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nand->options = NAND_SAMSUNG_LP_OPTIONS;
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
|
@ -28,7 +28,10 @@ endif
|
|||
|
||||
LIB = $(obj)lib$(BOARD).a
|
||||
|
||||
COBJS = $(BOARD).o flash.o ../common/misc.o ../common/auto_update.o
|
||||
COBJS = $(BOARD).o flash.o \
|
||||
../common/misc.o \
|
||||
../common/esd405ep_nand.o \
|
||||
../common/auto_update.o
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
|
|
|
|||
|
|
@ -5,7 +5,7 @@
|
|||
* (C) Copyright 2005
|
||||
* Stefan Roese, DENX Software Engineering, sr@denx.de.
|
||||
*
|
||||
* (C) Copyright 2006
|
||||
* (C) Copyright 2006-2007
|
||||
* Matthias Fuchs, esd GmbH, matthias.fuchs@esd-electronics.com
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
|
|
@ -476,12 +476,6 @@ int misc_init_r (void)
|
|||
*/
|
||||
out32(GPIO0_OR, in32(GPIO0_OR) | CFG_EEPROM_WP);
|
||||
|
||||
/*
|
||||
* Set NAND-FLASH GPIO signals to default
|
||||
*/
|
||||
out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE));
|
||||
out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);
|
||||
|
||||
/*
|
||||
* Reset touch-screen controller
|
||||
*/
|
||||
|
|
@ -690,20 +684,6 @@ void ide_set_reset(int on)
|
|||
#endif /* CONFIG_IDE_RESET */
|
||||
|
||||
|
||||
#if defined(CONFIG_CMD_NAND)
|
||||
#include <linux/mtd/nand_legacy.h>
|
||||
extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
|
||||
|
||||
void nand_init(void)
|
||||
{
|
||||
nand_probe(CFG_NAND_BASE);
|
||||
if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
|
||||
print_size(nand_dev_desc[0].totlen, "\n");
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(CFG_EEPROM_WREN)
|
||||
/* Input: <dev_addr> I2C address of EEPROM device to enable.
|
||||
* <state> -1: deliver current state
|
||||
|
|
|
|||
|
|
@ -28,7 +28,9 @@ endif
|
|||
|
||||
LIB = $(obj)lib$(BOARD).a
|
||||
|
||||
COBJS = $(BOARD).o flash.o ../common/misc.o
|
||||
COBJS = $(BOARD).o flash.o \
|
||||
../common/misc.o \
|
||||
../common/esd405ep_nand.o \
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
|
|
|
|||
|
|
@ -152,12 +152,6 @@ int misc_init_r (void)
|
|||
|
||||
out32(GPIO0_OR, val);
|
||||
|
||||
/*
|
||||
* Set NAND-FLASH GPIO signals to default
|
||||
*/
|
||||
out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE));
|
||||
out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);
|
||||
|
||||
/*
|
||||
* check board type and setup AP power
|
||||
*/
|
||||
|
|
@ -242,33 +236,5 @@ long int initdram (int board_type)
|
|||
mtdcr(memcfga, mem_mb0cf);
|
||||
val = mfdcr(memcfgd);
|
||||
|
||||
#if 0
|
||||
printf("\nmb0cf=%x\n", val); /* test-only */
|
||||
printf("strap=%x\n", mfdcr(strap)); /* test-only */
|
||||
#endif
|
||||
|
||||
return (4*1024*1024 << ((val & 0x000e0000) >> 17));
|
||||
}
|
||||
|
||||
|
||||
int testdram (void)
|
||||
{
|
||||
/* TODO: XXX XXX XXX */
|
||||
printf ("test: 16 MB - ok\n");
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
|
||||
#if defined(CONFIG_CMD_NAND)
|
||||
#include <linux/mtd/nand_legacy.h>
|
||||
extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
|
||||
|
||||
void nand_init(void)
|
||||
{
|
||||
nand_probe(CFG_NAND_BASE);
|
||||
if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
|
||||
print_size(nand_dev_desc[0].totlen, "\n");
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -28,7 +28,10 @@ endif
|
|||
|
||||
LIB = $(obj)lib$(BOARD).a
|
||||
|
||||
COBJS = $(BOARD).o flash.o ../common/misc.o ../common/auto_update.o
|
||||
COBJS = $(BOARD).o flash.o \
|
||||
../common/misc.o \
|
||||
../common/esd405ep_nand.o \
|
||||
../common/auto_update.o
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
|
|
|
|||
|
|
@ -23,6 +23,7 @@
|
|||
|
||||
#include <common.h>
|
||||
#include <asm/processor.h>
|
||||
#include <asm/io.h>
|
||||
#include <command.h>
|
||||
#include <malloc.h>
|
||||
|
||||
|
|
@ -31,6 +32,8 @@
|
|||
#define FPGA_DEBUG
|
||||
#endif
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
|
||||
extern void lxt971_no_sleep(void);
|
||||
|
||||
|
|
@ -114,6 +117,10 @@ int misc_init_r (void)
|
|||
int index;
|
||||
int i;
|
||||
|
||||
/* adjust flash start and offset */
|
||||
gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
|
||||
gd->bd->bi_flashoffset = 0;
|
||||
|
||||
dst = malloc(CFG_FPGA_MAX_SIZE);
|
||||
if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
|
||||
printf ("GUNZIP ERROR - must RESET board to recover\n");
|
||||
|
|
@ -177,17 +184,11 @@ int misc_init_r (void)
|
|||
/*
|
||||
* Reset external DUARTs
|
||||
*/
|
||||
out32(GPIO0_OR, in32(GPIO0_OR) | CFG_DUART_RST); /* set reset to high */
|
||||
out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_DUART_RST);
|
||||
udelay(10); /* wait 10us */
|
||||
out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_DUART_RST); /* set reset to low */
|
||||
out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_DUART_RST);
|
||||
udelay(1000); /* wait 1ms */
|
||||
|
||||
/*
|
||||
* Set NAND-FLASH GPIO signals to default
|
||||
*/
|
||||
out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE));
|
||||
out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);
|
||||
|
||||
/*
|
||||
* Enable interrupts in exar duart mcr[3]
|
||||
*/
|
||||
|
|
@ -226,24 +227,10 @@ long int initdram (int board_type)
|
|||
mtdcr(memcfga, mem_mb0cf);
|
||||
val = mfdcr(memcfgd);
|
||||
|
||||
#if 0
|
||||
printf("\nmb0cf=%x\n", val); /* test-only */
|
||||
printf("strap=%x\n", mfdcr(strap)); /* test-only */
|
||||
#endif
|
||||
|
||||
return (4*1024*1024 << ((val & 0x000e0000) >> 17));
|
||||
}
|
||||
|
||||
|
||||
int testdram (void)
|
||||
{
|
||||
/* TODO: XXX XXX XXX */
|
||||
printf ("test: 16 MB - ok\n");
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
|
||||
#ifdef CONFIG_IDE_RESET
|
||||
void ide_set_reset(int on)
|
||||
{
|
||||
|
|
@ -262,31 +249,6 @@ void ide_set_reset(int on)
|
|||
#endif /* CONFIG_IDE_RESET */
|
||||
|
||||
|
||||
#if defined(CONFIG_CMD_NAND)
|
||||
#include <linux/mtd/nand_legacy.h>
|
||||
extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
|
||||
|
||||
void nand_init(void)
|
||||
{
|
||||
nand_probe(CFG_NAND_BASE);
|
||||
if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
|
||||
print_size(nand_dev_desc[0].totlen, "\n");
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#ifdef CONFIG_AUTO_UPDATE_SHOW
|
||||
void board_auto_update_show(int au_active)
|
||||
{
|
||||
if (au_active) {
|
||||
printf("\n Dies ist die board-funktion: Updating!!!\n");
|
||||
} else {
|
||||
printf("\n Dies ist die board-funktion: Updating done!!!\n");
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
void reset_phy(void)
|
||||
{
|
||||
#ifdef CONFIG_LXT971_NO_SLEEP
|
||||
|
|
|
|||
|
|
@ -28,7 +28,9 @@ endif
|
|||
|
||||
LIB = $(obj)lib$(BOARD).a
|
||||
|
||||
COBJS = $(BOARD).o flash.o ../common/misc.o
|
||||
COBJS = $(BOARD).o flash.o \
|
||||
../common/misc.o \
|
||||
../common/esd405ep_nand.o \
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
|
|
|
|||
|
|
@ -194,12 +194,6 @@ int misc_init_r (void)
|
|||
out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_DUART_RST); /* set reset to low */
|
||||
udelay(1000); /* wait 1ms */
|
||||
|
||||
/*
|
||||
* Set NAND-FLASH GPIO signals to default
|
||||
*/
|
||||
out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE));
|
||||
out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);
|
||||
|
||||
/*
|
||||
* Enable interrupts in exar duart mcr[3]
|
||||
*/
|
||||
|
|
@ -340,17 +334,3 @@ void ide_set_reset(int on)
|
|||
}
|
||||
}
|
||||
#endif /* CONFIG_IDE_RESET */
|
||||
|
||||
|
||||
#if defined(CONFIG_CMD_NAND)
|
||||
#include <linux/mtd/nand_legacy.h>
|
||||
extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
|
||||
|
||||
void nand_init(void)
|
||||
{
|
||||
nand_probe(CFG_NAND_BASE);
|
||||
if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
|
||||
print_size(nand_dev_desc[0].totlen, "\n");
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -28,7 +28,9 @@ endif
|
|||
|
||||
LIB = $(obj)lib$(BOARD).a
|
||||
|
||||
COBJS = $(BOARD).o flash.o ../common/misc.o
|
||||
COBJS = $(BOARD).o flash.o \
|
||||
../common/misc.o \
|
||||
../common/esd405ep_nand.o \
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
|
|
|
|||
|
|
@ -169,12 +169,6 @@ int misc_init_r (void)
|
|||
out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_DUART_RST); /* set reset to low */
|
||||
udelay(1000); /* wait 1ms */
|
||||
|
||||
/*
|
||||
* Set NAND-FLASH GPIO signals to default
|
||||
*/
|
||||
out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE));
|
||||
out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);
|
||||
|
||||
/*
|
||||
* Enable interrupts in exar duart mcr[3]
|
||||
*/
|
||||
|
|
@ -218,35 +212,5 @@ long int initdram (int board_type)
|
|||
mtdcr(memcfga, mem_mb0cf);
|
||||
val = mfdcr(memcfgd);
|
||||
|
||||
#if 0
|
||||
printf("\nmb0cf=%x\n", val); /* test-only */
|
||||
printf("strap=%x\n", mfdcr(strap)); /* test-only */
|
||||
#endif
|
||||
|
||||
return (4*1024*1024 << ((val & 0x000e0000) >> 17));
|
||||
}
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
|
||||
int testdram (void)
|
||||
{
|
||||
/* TODO: XXX XXX XXX */
|
||||
printf ("test: 16 MB - ok\n");
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
|
||||
#if defined(CONFIG_CMD_NAND)
|
||||
#include <linux/mtd/nand_legacy.h>
|
||||
extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
|
||||
|
||||
void nand_init(void)
|
||||
{
|
||||
nand_probe(CFG_NAND_BASE);
|
||||
if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
|
||||
print_size(nand_dev_desc[0].totlen, "\n");
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -468,14 +468,31 @@ static int nand_load_image(cmd_tbl_t *cmdtp, nand_info_t *nand,
|
|||
ulong offset, ulong addr, char *cmd)
|
||||
{
|
||||
int r;
|
||||
char *ep;
|
||||
char *ep, *s;
|
||||
ulong cnt;
|
||||
image_header_t *hdr;
|
||||
int jffs2 = 0;
|
||||
|
||||
s = strchr(cmd, '.');
|
||||
if (s != NULL &&
|
||||
(!strcmp(s, ".jffs2") || !strcmp(s, ".e") || !strcmp(s, ".i")))
|
||||
jffs2 = 1;
|
||||
|
||||
printf("\nLoading from %s, offset 0x%lx\n", nand->name, offset);
|
||||
|
||||
cnt = nand->oobblock;
|
||||
r = nand_read(nand, offset, &cnt, (u_char *) addr);
|
||||
if (jffs2) {
|
||||
nand_read_options_t opts;
|
||||
memset(&opts, 0, sizeof(opts));
|
||||
opts.buffer = (u_char*) addr;
|
||||
opts.length = cnt;
|
||||
opts.offset = offset;
|
||||
opts.quiet = 1;
|
||||
r = nand_read_opts(nand, &opts);
|
||||
} else {
|
||||
r = nand_read(nand, offset, &cnt, (u_char *) addr);
|
||||
}
|
||||
|
||||
if (r) {
|
||||
puts("** Read error\n");
|
||||
show_boot_progress (-56);
|
||||
|
|
@ -495,8 +512,18 @@ static int nand_load_image(cmd_tbl_t *cmdtp, nand_info_t *nand,
|
|||
print_image_hdr(hdr);
|
||||
|
||||
cnt = (ntohl(hdr->ih_size) + sizeof (image_header_t));
|
||||
if (jffs2) {
|
||||
nand_read_options_t opts;
|
||||
memset(&opts, 0, sizeof(opts));
|
||||
opts.buffer = (u_char*) addr;
|
||||
opts.length = cnt;
|
||||
opts.offset = offset;
|
||||
opts.quiet = 1;
|
||||
r = nand_read_opts(nand, &opts);
|
||||
} else {
|
||||
r = nand_read(nand, offset, &cnt, (u_char *) addr);
|
||||
}
|
||||
|
||||
r = nand_read(nand, offset, &cnt, (u_char *) addr);
|
||||
if (r) {
|
||||
puts("** Read error\n");
|
||||
show_boot_progress (-58);
|
||||
|
|
@ -545,7 +572,7 @@ int do_nandboot(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
|
|||
if (argc > 3)
|
||||
goto usage;
|
||||
if (argc == 3)
|
||||
addr = simple_strtoul(argv[2], NULL, 16);
|
||||
addr = simple_strtoul(argv[1], NULL, 16);
|
||||
else
|
||||
addr = CFG_LOAD_ADDR;
|
||||
return nand_load_image(cmdtp, &nand_info[dev->id->num],
|
||||
|
|
@ -604,7 +631,7 @@ usage:
|
|||
|
||||
U_BOOT_CMD(nboot, 4, 1, do_nandboot,
|
||||
"nboot - boot from NAND device\n",
|
||||
"[partition] | [[[loadAddr] dev] offset]\n");
|
||||
"[.jffs2] [partition] | [[[loadAddr] dev] offset]\n");
|
||||
|
||||
#endif
|
||||
|
||||
|
|
|
|||
|
|
@ -123,6 +123,7 @@ struct nand_manufacturers nand_manuf_ids[] = {
|
|||
{NAND_MFR_NATIONAL, "National"},
|
||||
{NAND_MFR_RENESAS, "Renesas"},
|
||||
{NAND_MFR_STMICRO, "ST Micro"},
|
||||
{NAND_MFR_MICRON, "Micron"},
|
||||
{0x0, "Unknown"}
|
||||
};
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -53,9 +53,13 @@
|
|||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
|
||||
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
|
||||
|
||||
#define CONFIG_NET_MULTI 1
|
||||
#undef CONFIG_HAS_ETH1
|
||||
|
||||
#define CONFIG_MII 1 /* MII PHY management */
|
||||
#define CONFIG_PHY_ADDR 0 /* PHY address */
|
||||
#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
|
||||
#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */
|
||||
|
||||
#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/
|
||||
|
||||
|
|
@ -144,39 +148,16 @@
|
|||
* NAND-FLASH stuff
|
||||
*-----------------------------------------------------------------------
|
||||
*/
|
||||
#define CFG_NAND_BASE_LIST { CFG_NAND_BASE }
|
||||
#define NAND_MAX_CHIPS 1
|
||||
#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
|
||||
#define NAND_BIG_DELAY_US 25
|
||||
|
||||
#define CFG_NAND_LEGACY
|
||||
#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
|
||||
#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
|
||||
#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
|
||||
#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
|
||||
|
||||
#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
|
||||
#define SECTORSIZE 512
|
||||
|
||||
#define ADDR_COLUMN 1
|
||||
#define ADDR_PAGE 2
|
||||
#define ADDR_COLUMN_PAGE 3
|
||||
|
||||
#define NAND_ChipID_UNKNOWN 0x00
|
||||
#define NAND_MAX_FLOORS 1
|
||||
#define NAND_MAX_CHIPS 1
|
||||
|
||||
#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
|
||||
#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
|
||||
#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
|
||||
#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
|
||||
|
||||
#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0)
|
||||
#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0)
|
||||
#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0)
|
||||
#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0)
|
||||
#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0)
|
||||
#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0)
|
||||
#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY))
|
||||
|
||||
#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
|
||||
#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
|
||||
#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
|
||||
#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
|
||||
|
||||
#define CONFIG_MTD_NAND_VERIFY_WRITE 1 /* verify all writes!!! */
|
||||
#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
|
|
|
|||
|
|
@ -90,8 +90,6 @@
|
|||
#define CONFIG_CMD_EEPROM
|
||||
|
||||
|
||||
#define CFG_NAND_LEGACY
|
||||
|
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */
|
||||
|
||||
#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
|
||||
|
|
@ -157,34 +155,15 @@
|
|||
* NAND-FLASH stuff
|
||||
*-----------------------------------------------------------------------
|
||||
*/
|
||||
#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
|
||||
#define SECTORSIZE 512
|
||||
#define CFG_NAND_BASE_LIST { CFG_NAND_BASE }
|
||||
#define NAND_MAX_CHIPS 1
|
||||
#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
|
||||
#define NAND_BIG_DELAY_US 25
|
||||
|
||||
#define ADDR_COLUMN 1
|
||||
#define ADDR_PAGE 2
|
||||
#define ADDR_COLUMN_PAGE 3
|
||||
|
||||
#define NAND_ChipID_UNKNOWN 0x00
|
||||
#define NAND_MAX_FLOORS 1
|
||||
#define NAND_MAX_CHIPS 1
|
||||
|
||||
#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
|
||||
#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
|
||||
#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
|
||||
#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
|
||||
|
||||
#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0)
|
||||
#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0)
|
||||
#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0)
|
||||
#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0)
|
||||
#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0)
|
||||
#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0)
|
||||
#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY))
|
||||
|
||||
#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
|
||||
#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
|
||||
#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
|
||||
#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
|
||||
#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
|
||||
#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
|
||||
#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
|
||||
#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
|
||||
|
||||
#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
|
||||
|
||||
|
|
|
|||
|
|
@ -92,8 +92,6 @@
|
|||
|
||||
#define CONFIG_SUPPORT_VFAT
|
||||
|
||||
#define CFG_NAND_LEGACY
|
||||
|
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */
|
||||
|
||||
#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
|
||||
|
|
|
|||
|
|
@ -114,8 +114,6 @@
|
|||
#define CONFIG_AUTO_UPDATE 1 /* autoupdate via compactflash */
|
||||
#endif
|
||||
|
||||
#define CFG_NAND_LEGACY
|
||||
|
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */
|
||||
|
||||
#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
|
||||
|
|
|
|||
|
|
@ -100,9 +100,6 @@
|
|||
|
||||
#define CONFIG_SUPPORT_VFAT
|
||||
|
||||
#define CFG_NAND_LEGACY
|
||||
|
||||
|
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */
|
||||
|
||||
#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
|
||||
|
|
|
|||
|
|
@ -111,8 +111,6 @@
|
|||
|
||||
#undef CONFIG_AUTO_UPDATE /* autoupdate via compactflash */
|
||||
|
||||
#define CFG_NAND_LEGACY
|
||||
|
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */
|
||||
|
||||
#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
|
||||
|
|
|
|||
|
|
@ -141,8 +141,6 @@
|
|||
#define CONFIG_AUTO_UPDATE 1 /* autoupdate via compactflash */
|
||||
#undef CONFIG_AUTO_UPDATE_SHOW /* use board show routine */
|
||||
|
||||
#define CFG_NAND_LEGACY
|
||||
|
||||
#undef CONFIG_BZIP2 /* include support for bzip2 compressed images */
|
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */
|
||||
|
||||
|
|
@ -209,34 +207,15 @@
|
|||
* NAND-FLASH stuff
|
||||
*-----------------------------------------------------------------------
|
||||
*/
|
||||
#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
|
||||
#define SECTORSIZE 512
|
||||
#define CFG_NAND_BASE_LIST { CFG_NAND_BASE }
|
||||
#define NAND_MAX_CHIPS 1
|
||||
#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
|
||||
#define NAND_BIG_DELAY_US 25
|
||||
|
||||
#define ADDR_COLUMN 1
|
||||
#define ADDR_PAGE 2
|
||||
#define ADDR_COLUMN_PAGE 3
|
||||
|
||||
#define NAND_ChipID_UNKNOWN 0x00
|
||||
#define NAND_MAX_FLOORS 1
|
||||
#define NAND_MAX_CHIPS 1
|
||||
|
||||
#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
|
||||
#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
|
||||
#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
|
||||
#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
|
||||
|
||||
#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0)
|
||||
#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0)
|
||||
#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0)
|
||||
#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0)
|
||||
#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0)
|
||||
#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0)
|
||||
#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY))
|
||||
|
||||
#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
|
||||
#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
|
||||
#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
|
||||
#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
|
||||
#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
|
||||
#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
|
||||
#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
|
||||
#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
|
||||
|
||||
#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
|
||||
|
||||
|
|
|
|||
|
|
@ -147,36 +147,15 @@
|
|||
* NAND-FLASH stuff
|
||||
*-----------------------------------------------------------------------
|
||||
*/
|
||||
#define CFG_NAND_LEGACY
|
||||
#define CFG_NAND_BASE_LIST { CFG_NAND_BASE }
|
||||
#define NAND_MAX_CHIPS 1
|
||||
#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
|
||||
#define NAND_BIG_DELAY_US 25
|
||||
|
||||
#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
|
||||
#define SECTORSIZE 512
|
||||
|
||||
#define ADDR_COLUMN 1
|
||||
#define ADDR_PAGE 2
|
||||
#define ADDR_COLUMN_PAGE 3
|
||||
|
||||
#define NAND_ChipID_UNKNOWN 0x00
|
||||
#define NAND_MAX_FLOORS 1
|
||||
#define NAND_MAX_CHIPS 1
|
||||
|
||||
#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
|
||||
#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
|
||||
#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
|
||||
#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
|
||||
|
||||
#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0)
|
||||
#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0)
|
||||
#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0)
|
||||
#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0)
|
||||
#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0)
|
||||
#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0)
|
||||
#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY))
|
||||
|
||||
#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
|
||||
#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
|
||||
#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
|
||||
#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
|
||||
#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
|
||||
#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
|
||||
#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
|
||||
#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
|
||||
|
||||
#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
|
||||
|
||||
|
|
|
|||
|
|
@ -96,7 +96,6 @@
|
|||
#define CONFIG_SUPPORT_VFAT
|
||||
|
||||
#define CONFIG_AUTO_UPDATE 1 /* autoupdate via compactflash */
|
||||
#define CONFIG_AUTO_UPDATE_SHOW 1 /* use board show routine */
|
||||
|
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */
|
||||
|
||||
|
|
@ -168,36 +167,15 @@
|
|||
* NAND-FLASH stuff
|
||||
*-----------------------------------------------------------------------
|
||||
*/
|
||||
#define CFG_NAND_LEGACY
|
||||
#define CFG_NAND_BASE_LIST { CFG_NAND_BASE }
|
||||
#define NAND_MAX_CHIPS 1
|
||||
#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
|
||||
#define NAND_BIG_DELAY_US 25
|
||||
|
||||
#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
|
||||
#define SECTORSIZE 512
|
||||
|
||||
#define ADDR_COLUMN 1
|
||||
#define ADDR_PAGE 2
|
||||
#define ADDR_COLUMN_PAGE 3
|
||||
|
||||
#define NAND_ChipID_UNKNOWN 0x00
|
||||
#define NAND_MAX_FLOORS 1
|
||||
#define NAND_MAX_CHIPS 1
|
||||
|
||||
#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
|
||||
#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
|
||||
#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
|
||||
#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
|
||||
|
||||
#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0)
|
||||
#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0)
|
||||
#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0)
|
||||
#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0)
|
||||
#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0)
|
||||
#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0)
|
||||
#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY))
|
||||
|
||||
#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
|
||||
#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
|
||||
#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
|
||||
#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
|
||||
#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
|
||||
#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
|
||||
#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
|
||||
#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
|
||||
|
||||
#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
|
||||
|
||||
|
|
@ -276,11 +254,6 @@
|
|||
|
||||
#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
|
||||
|
||||
#if 0 /* test-only */
|
||||
#define CFG_JFFS2_FIRST_BANK 0 /* use for JFFS2 */
|
||||
#define CFG_JFFS2_NUM_BANKS 1 /* ! second bank contains U-Boot */
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Start addresses for the final memory configuration
|
||||
* (Set up by the startup code)
|
||||
|
|
@ -306,9 +279,6 @@
|
|||
#define CFG_ENV_SIZE 0x700 /* 2048 bytes may be used for env vars*/
|
||||
/* total size of a CAT24WC16 is 2048 bytes */
|
||||
|
||||
#define CFG_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */
|
||||
#define CFG_NVRAM_SIZE 242 /* NVRAM size */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* I2C EEPROM (CAT24WC16) for environment
|
||||
*/
|
||||
|
|
@ -317,7 +287,7 @@
|
|||
#define CFG_I2C_SLAVE 0x7F
|
||||
|
||||
#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT24WC08 */
|
||||
#if 1 /* test-only */
|
||||
|
||||
/* CAT24WC08/16... */
|
||||
#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
|
||||
/* mask of address bits that overflow into the "EEPROM chip address" */
|
||||
|
|
@ -325,15 +295,6 @@
|
|||
#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
|
||||
/* 16 byte page write mode using*/
|
||||
/* last 4 bits of the address */
|
||||
#else
|
||||
/* CAT24WC32/64... */
|
||||
#define CFG_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */
|
||||
/* mask of address bits that overflow into the "EEPROM chip address" */
|
||||
#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x01
|
||||
#define CFG_EEPROM_PAGE_WRITE_BITS 5 /* The Catalyst CAT24WC32 has */
|
||||
/* 32 byte page write mode using*/
|
||||
/* last 5 bits of the address */
|
||||
#endif
|
||||
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
|
||||
#define CFG_EEPROM_PAGE_WRITE_ENABLE
|
||||
|
||||
|
|
|
|||
|
|
@ -153,36 +153,15 @@
|
|||
* NAND-FLASH stuff
|
||||
*-----------------------------------------------------------------------
|
||||
*/
|
||||
#define CFG_NAND_LEGACY
|
||||
#define CFG_NAND_BASE_LIST { CFG_NAND_BASE }
|
||||
#define NAND_MAX_CHIPS 1
|
||||
#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
|
||||
#define NAND_BIG_DELAY_US 25
|
||||
|
||||
#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
|
||||
#define SECTORSIZE 512
|
||||
|
||||
#define ADDR_COLUMN 1
|
||||
#define ADDR_PAGE 2
|
||||
#define ADDR_COLUMN_PAGE 3
|
||||
|
||||
#define NAND_ChipID_UNKNOWN 0x00
|
||||
#define NAND_MAX_FLOORS 1
|
||||
#define NAND_MAX_CHIPS 1
|
||||
|
||||
#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
|
||||
#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
|
||||
#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
|
||||
#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
|
||||
|
||||
#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0)
|
||||
#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0)
|
||||
#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0)
|
||||
#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0)
|
||||
#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0)
|
||||
#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0)
|
||||
#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY))
|
||||
|
||||
#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
|
||||
#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
|
||||
#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
|
||||
#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
|
||||
#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
|
||||
#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
|
||||
#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
|
||||
#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
|
||||
|
||||
#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
|
||||
|
||||
|
|
|
|||
|
|
@ -145,38 +145,16 @@
|
|||
* NAND-FLASH stuff
|
||||
*-----------------------------------------------------------------------
|
||||
*/
|
||||
#define CFG_NAND_LEGACY
|
||||
#define CFG_NAND_BASE_LIST { CFG_NAND_BASE }
|
||||
#define NAND_MAX_CHIPS 1
|
||||
#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
|
||||
#define NAND_BIG_DELAY_US 25
|
||||
|
||||
#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
|
||||
#define SECTORSIZE 512
|
||||
#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
|
||||
#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
|
||||
#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
|
||||
#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
|
||||
|
||||
#define ADDR_COLUMN 1
|
||||
#define ADDR_PAGE 2
|
||||
#define ADDR_COLUMN_PAGE 3
|
||||
|
||||
#define NAND_ChipID_UNKNOWN 0x00
|
||||
#define NAND_MAX_FLOORS 1
|
||||
#define NAND_MAX_CHIPS 1
|
||||
|
||||
#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
|
||||
#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
|
||||
#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
|
||||
#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
|
||||
|
||||
#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0)
|
||||
#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0)
|
||||
#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0)
|
||||
#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0)
|
||||
#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0)
|
||||
#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0)
|
||||
#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY))
|
||||
|
||||
#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
|
||||
#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
|
||||
#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
|
||||
#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
|
||||
|
||||
#define CONFIG_MTD_NAND_VERIFY_WRITE 1 /* verify all writes!!! */
|
||||
#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
|
|
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|||
|
|
@ -348,6 +348,7 @@ struct nand_chip {
|
|||
#define NAND_MFR_NATIONAL 0x8f
|
||||
#define NAND_MFR_RENESAS 0x07
|
||||
#define NAND_MFR_STMICRO 0x20
|
||||
#define NAND_MFR_MICRON 0x2c
|
||||
|
||||
/**
|
||||
* struct nand_flash_dev - NAND Flash Device ID Structure
|
||||
|
|
|
|||
|
|
@ -32,6 +32,7 @@ typedef struct mtd_info nand_info_t;
|
|||
|
||||
extern int nand_curr_device;
|
||||
extern nand_info_t nand_info[];
|
||||
extern void nand_init(void);
|
||||
|
||||
static inline int nand_read(nand_info_t *info, ulong ofs, ulong *len, u_char *buf)
|
||||
{
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue