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ARM: dts: stm32mp1: use OPP information for PLL1 settings in SPL

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This patch allows to switch the CPU frequency to 800MHz on the
ST Microelectronics board (DK1/DK2 and EV1) or dh electronics SOM
using the STM32MP15x SOC and when it is supported by the HW
(for STM32MP15xD and STM32MP15xF).

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
This commit is contained in:
Patrick Delaunay 2020-05-25 12:19:48 +02:00
parent 2f238327b7
commit 4a87fea6de
5 changed files with 10 additions and 36 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

10
arch/arm/dts/stm32mp15-u-boot.dtsi
View file

@ -88,6 +88,16 @@
u-boot,dm-pre-reloc; u-boot,dm-pre-reloc;
}; };
&cpu0_opp_table {
u-boot,dm-spl;
opp-650000000 {
u-boot,dm-spl;
};
opp-800000000 {
u-boot,dm-spl;
};
};
&gpioa { &gpioa {
u-boot,dm-pre-reloc; u-boot,dm-pre-reloc;
}; };

9
arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi
View file

@ -133,15 +133,6 @@
CLK_LPTIM45_LSE CLK_LPTIM45_LSE
>; >;
/* VCO = 1300.0 MHz => P = 650 (CPU) */
pll1: st,pll@0 {
compatible = "st,stm32mp1-pll";
reg = <0>;
cfg = < 2 80 0 0 0 PQR(1,0,0) >;
frac = < 0x800 >;
u-boot,dm-pre-reloc;
};
/* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */ /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
pll2: st,pll@1 { pll2: st,pll@1 {
compatible = "st,stm32mp1-pll"; compatible = "st,stm32mp1-pll";

9
arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi
View file

@ -129,15 +129,6 @@
CLK_LPTIM45_LSE CLK_LPTIM45_LSE
>; >;
/* VCO = 1300.0 MHz => P = 650 (CPU) */
pll1: st,pll@0 {
compatible = "st,stm32mp1-pll";
reg = <0>;
cfg = < 2 80 0 0 0 PQR(1,0,0) >;
frac = < 0x800 >;
u-boot,dm-pre-reloc;
};
/* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */ /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
pll2: st,pll@1 { pll2: st,pll@1 {
compatible = "st,stm32mp1-pll"; compatible = "st,stm32mp1-pll";

9
arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi
View file

@ -235,15 +235,6 @@
CLK_LPTIM45_LSE CLK_LPTIM45_LSE
>; >;
/* VCO = 1300.0 MHz => P = 650 (CPU) */
pll1: st,pll@0 {
compatible = "st,stm32mp1-pll";
reg = <0>;
cfg = < 2 80 0 0 0 PQR(1,0,0) >;
frac = < 0x800 >;
u-boot,dm-pre-reloc;
};
/* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */ /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
pll2: st,pll@1 { pll2: st,pll@1 {
compatible = "st,stm32mp1-pll"; compatible = "st,stm32mp1-pll";

9
arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi
View file

@ -114,15 +114,6 @@
CLK_LPTIM45_LSE CLK_LPTIM45_LSE
>; >;
/* VCO = 1300.0 MHz => P = 650 (CPU) */
pll1: st,pll@0 {
compatible = "st,stm32mp1-pll";
reg = <0>;
cfg = < 2 80 0 0 0 PQR(1,0,0) >;
frac = < 0x800 >;
u-boot,dm-pre-reloc;
};
/* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */ /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
pll2: st,pll@1 { pll2: st,pll@1 {
compatible = "st,stm32mp1-pll"; compatible = "st,stm32mp1-pll";