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phy: marvell: a3700: Set TXDCLK_2X_SEL bit during PCIe initialization

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Marvell Armada 3700 Functional Specifications, section 52.2 PCIe Link
Initialization says that TXDCLK_2X_SEL bit needs to be enabled for PCIe
Root Complex mode.

Same change was included in TF-A project:
https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/9408

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Pali Rohár 2021-09-24 16:11:55 +02:00 • committed by Stefan Roese
parent 646a152247
commit 4adb16b29a
2 changed files with 2 additions and 1 deletions
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2
drivers/phy/marvell/comphy_a3700.c
View file

@ -200,7 +200,7 @@ static int comphy_pcie_power_up(u32 speed, u32 invert)
* 6. Enable the output of 100M/125M/500M clock
*/
reg_set16(phy_addr(PCIE, MISC_REG0),
0xA00D | rb_clk500m_en | rb_clk100m_125m_en, 0xFFFF);
0xA00D | rb_clk500m_en | rb_txdclk_2x_sel | rb_clk100m_125m_en, 0xFFFF);
/*
* 7. Enable TX

1
drivers/phy/marvell/comphy_a3700.h
View file

@ -120,6 +120,7 @@ static inline void __iomem *phy_addr(enum phy_unit unit, u32 addr)
#define MISC_REG0 0x4f
#define rb_clk100m_125m_en BIT(4)
#define rb_txdclk_2x_sel BIT(6)
#define rb_clk500m_en BIT(7)
#define rb_ref_clk_sel BIT(10)