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riscv: dts: jh7110: Add a new clock input to gmac

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To be compatible with the VisionFive 2 board.
The code is ported from tag JH7110_VF2_515_v3.9.3 of VF2 repo.

Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
This commit is contained in:
Hal Feng 2023-08-09 16:02:50 +08:00
parent 4f914dd6f7
commit 4b07186e8e
1 changed files with 8 additions and 4 deletions
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12
arch/riscv/dts/jh7110.dtsi
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@ -856,13 +856,15 @@
"ptp_ref", "ptp_ref",
"stmmaceth", "stmmaceth",
"pclk", "pclk",
"gtxc"; "gtxc",
"rmii_rtx";
clocks = <&clkgen JH7110_GMAC0_GTXCLK>, clocks = <&clkgen JH7110_GMAC0_GTXCLK>,
<&clkgen JH7110_U0_GMAC5_CLK_TX>, <&clkgen JH7110_U0_GMAC5_CLK_TX>,
<&clkgen JH7110_GMAC0_PTP>, <&clkgen JH7110_GMAC0_PTP>,
<&clkgen JH7110_U0_GMAC5_CLK_AHB>, <&clkgen JH7110_U0_GMAC5_CLK_AHB>,
<&clkgen JH7110_U0_GMAC5_CLK_AXI>, <&clkgen JH7110_U0_GMAC5_CLK_AXI>,
<&clkgen JH7110_GMAC0_GTXC>; <&clkgen JH7110_GMAC0_GTXC>,
<&clkgen JH7110_GMAC0_RMII_RTX>;
resets = <&rstgen RSTN_U0_DW_GMAC5_AXI64_AHB>, resets = <&rstgen RSTN_U0_DW_GMAC5_AXI64_AHB>,
<&rstgen RSTN_U0_DW_GMAC5_AXI64_AXI>; <&rstgen RSTN_U0_DW_GMAC5_AXI64_AXI>;
reset-names = "ahb", "stmmaceth"; reset-names = "ahb", "stmmaceth";
@ -897,13 +899,15 @@
"ptp_ref", "ptp_ref",
"stmmaceth", "stmmaceth",
"pclk", "pclk",
"gtxc"; "gtxc",
"rmii_rtx";
clocks = <&clkgen JH7110_GMAC1_GTXCLK>, clocks = <&clkgen JH7110_GMAC1_GTXCLK>,
<&clkgen JH7110_GMAC5_CLK_TX>, <&clkgen JH7110_GMAC5_CLK_TX>,
<&clkgen JH7110_GMAC5_CLK_PTP>, <&clkgen JH7110_GMAC5_CLK_PTP>,
<&clkgen JH7110_GMAC5_CLK_AHB>, <&clkgen JH7110_GMAC5_CLK_AHB>,
<&clkgen JH7110_GMAC5_CLK_AXI>, <&clkgen JH7110_GMAC5_CLK_AXI>,
<&clkgen JH7110_GMAC1_GTXC>; <&clkgen JH7110_GMAC1_GTXC>,
<&clkgen JH7110_GMAC1_RMII_RTX>;
resets = <&rstgen RSTN_U1_DW_GMAC5_AXI64_H_N>, resets = <&rstgen RSTN_U1_DW_GMAC5_AXI64_H_N>,
<&rstgen RSTN_U1_DW_GMAC5_AXI64_A_I>; <&rstgen RSTN_U1_DW_GMAC5_AXI64_A_I>;
reset-names = "ahb", "stmmaceth"; reset-names = "ahb", "stmmaceth";