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arm: relocate_code(): Remove useless relocation offset computation

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Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
This commit is contained in:
Benoît Thébaudeau 2013-04-11 09:35:45 +00:00 • committed by Albert ARIBAUD
parent 1dd1276fd8
commit 4b3db1cd31
13 changed files with 39 additions and 66 deletions
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8
arch/arm/cpu/arm1136/start.S
View file

@ -185,16 +185,15 @@ relocate_code:
mov r6, r2 /* save addr of destination */ mov r6, r2 /* save addr of destination */
adr r0, _start adr r0, _start
cmp r0, r6 subs r9, r6, r0 /* r9 <- relocation offset */
moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */
beq relocate_done /* skip relocation */ beq relocate_done /* skip relocation */
mov r1, r6 /* r1 <- scratch for copy_loop */ mov r1, r6 /* r1 <- scratch for copy_loop */
ldr r3, _image_copy_end_ofs ldr r3, _image_copy_end_ofs
add r2, r0, r3 /* r2 <- source end address */ add r2, r0, r3 /* r2 <- source end address */
copy_loop: copy_loop:
ldmia r0!, {r9-r10} /* copy from source address [r0] */ ldmia r0!, {r10-r11} /* copy from source address [r0] */
stmia r1!, {r9-r10} /* copy to target address [r1] */ stmia r1!, {r10-r11} /* copy to target address [r1] */
cmp r0, r2 /* until source end address [r2] */ cmp r0, r2 /* until source end address [r2] */
blo copy_loop blo copy_loop
@ -203,7 +202,6 @@ copy_loop:
* fix .rel.dyn relocations * fix .rel.dyn relocations
*/ */
ldr r0, _TEXT_BASE /* r0 <- Text base */ ldr r0, _TEXT_BASE /* r0 <- Text base */
sub r9, r6, r0 /* r9 <- relocation offset */
ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */ ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
add r10, r10, r0 /* r10 <- sym table in FLASH */ add r10, r10, r0 /* r10 <- sym table in FLASH */
ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */ ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */

8
arch/arm/cpu/arm1176/start.S
View file

@ -248,16 +248,15 @@ relocate_code:
mov r6, r2 /* save addr of destination */ mov r6, r2 /* save addr of destination */
adr r0, _start adr r0, _start
cmp r0, r6 subs r9, r6, r0 /* r9 <- relocation offset */
moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */
beq relocate_done /* skip relocation */ beq relocate_done /* skip relocation */
mov r1, r6 /* r1 <- scratch for copy_loop */ mov r1, r6 /* r1 <- scratch for copy_loop */
ldr r3, _bss_start_ofs ldr r3, _bss_start_ofs
add r2, r0, r3 /* r2 <- source end address */ add r2, r0, r3 /* r2 <- source end address */
copy_loop: copy_loop:
ldmia r0!, {r9-r10} /* copy from source address [r0] */ ldmia r0!, {r10-r11} /* copy from source address [r0] */
stmia r1!, {r9-r10} /* copy to target address [r1] */ stmia r1!, {r10-r11} /* copy to target address [r1] */
cmp r0, r2 /* until source end address [r2] */ cmp r0, r2 /* until source end address [r2] */
blo copy_loop blo copy_loop
@ -266,7 +265,6 @@ copy_loop:
* fix .rel.dyn relocations * fix .rel.dyn relocations
*/ */
ldr r0, _TEXT_BASE /* r0 <- Text base */ ldr r0, _TEXT_BASE /* r0 <- Text base */
sub r9, r6, r0 /* r9 <- relocation offset */
ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */ ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
add r10, r10, r0 /* r10 <- sym table in FLASH */ add r10, r10, r0 /* r10 <- sym table in FLASH */
ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */ ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */

8
arch/arm/cpu/arm720t/start.S
View file

@ -163,16 +163,15 @@ relocate_code:
mov r6, r2 /* save addr of destination */ mov r6, r2 /* save addr of destination */
adr r0, _start adr r0, _start
cmp r0, r6 subs r9, r6, r0 /* r9 <- relocation offset */
moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */
beq relocate_done /* skip relocation */ beq relocate_done /* skip relocation */
mov r1, r6 /* r1 <- scratch for copy_loop */ mov r1, r6 /* r1 <- scratch for copy_loop */
ldr r3, _bss_start_ofs ldr r3, _bss_start_ofs
add r2, r0, r3 /* r2 <- source end address */ add r2, r0, r3 /* r2 <- source end address */
copy_loop: copy_loop:
ldmia r0!, {r9-r10} /* copy from source address [r0] */ ldmia r0!, {r10-r11} /* copy from source address [r0] */
stmia r1!, {r9-r10} /* copy to target address [r1] */ stmia r1!, {r10-r11} /* copy to target address [r1] */
cmp r0, r2 /* until source end address [r2] */ cmp r0, r2 /* until source end address [r2] */
blo copy_loop blo copy_loop
@ -181,7 +180,6 @@ copy_loop:
* fix .rel.dyn relocations * fix .rel.dyn relocations
*/ */
ldr r0, _TEXT_BASE /* r0 <- Text base */ ldr r0, _TEXT_BASE /* r0 <- Text base */
sub r9, r6, r0 /* r9 <- relocation offset */
ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */ ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
add r10, r10, r0 /* r10 <- sym table in FLASH */ add r10, r10, r0 /* r10 <- sym table in FLASH */
ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */ ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */

8
arch/arm/cpu/arm920t/start.S
View file

@ -202,16 +202,15 @@ relocate_code:
mov r6, r2 /* save addr of destination */ mov r6, r2 /* save addr of destination */
adr r0, _start adr r0, _start
cmp r0, r6 subs r9, r6, r0 /* r9 <- relocation offset */
moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */
beq relocate_done /* skip relocation */ beq relocate_done /* skip relocation */
mov r1, r6 /* r1 <- scratch for copy_loop */ mov r1, r6 /* r1 <- scratch for copy_loop */
ldr r3, _bss_start_ofs ldr r3, _bss_start_ofs
add r2, r0, r3 /* r2 <- source end address */ add r2, r0, r3 /* r2 <- source end address */
copy_loop: copy_loop:
ldmia r0!, {r9-r10} /* copy from source address [r0] */ ldmia r0!, {r10-r11} /* copy from source address [r0] */
stmia r1!, {r9-r10} /* copy to target address [r1] */ stmia r1!, {r10-r11} /* copy to target address [r1] */
cmp r0, r2 /* until source end address [r2] */ cmp r0, r2 /* until source end address [r2] */
blo copy_loop blo copy_loop
@ -220,7 +219,6 @@ copy_loop:
* fix .rel.dyn relocations * fix .rel.dyn relocations
*/ */
ldr r0, _TEXT_BASE /* r0 <- Text base */ ldr r0, _TEXT_BASE /* r0 <- Text base */
sub r9, r6, r0 /* r9 <- relocation offset */
ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */ ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
add r10, r10, r0 /* r10 <- sym table in FLASH */ add r10, r10, r0 /* r10 <- sym table in FLASH */
ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */ ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */

8
arch/arm/cpu/arm925t/start.S
View file

@ -192,16 +192,15 @@ relocate_code:
mov r6, r2 /* save addr of destination */ mov r6, r2 /* save addr of destination */
adr r0, _start adr r0, _start
cmp r0, r6 subs r9, r6, r0 /* r9 <- relocation offset */
moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */
beq relocate_done /* skip relocation */ beq relocate_done /* skip relocation */
mov r1, r6 /* r1 <- scratch for copy_loop */ mov r1, r6 /* r1 <- scratch for copy_loop */
ldr r3, _bss_start_ofs ldr r3, _bss_start_ofs
add r2, r0, r3 /* r2 <- source end address */ add r2, r0, r3 /* r2 <- source end address */
copy_loop: copy_loop:
ldmia r0!, {r9-r10} /* copy from source address [r0] */ ldmia r0!, {r10-r11} /* copy from source address [r0] */
stmia r1!, {r9-r10} /* copy to target address [r1] */ stmia r1!, {r10-r11} /* copy to target address [r1] */
cmp r0, r2 /* until source end address [r2] */ cmp r0, r2 /* until source end address [r2] */
blo copy_loop blo copy_loop
@ -210,7 +209,6 @@ copy_loop:
* fix .rel.dyn relocations * fix .rel.dyn relocations
*/ */
ldr r0, _TEXT_BASE /* r0 <- Text base */ ldr r0, _TEXT_BASE /* r0 <- Text base */
sub r9, r6, r0 /* r9 <- relocation offset */
ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */ ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
add r10, r10, r0 /* r10 <- sym table in FLASH */ add r10, r10, r0 /* r10 <- sym table in FLASH */
ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */ ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */

9
arch/arm/cpu/arm926ejs/start.S
View file

@ -209,17 +209,15 @@ relocate_code:
mov r6, r2 /* save addr of destination */ mov r6, r2 /* save addr of destination */
adr r0, _start adr r0, _start
sub r9, r6, r0 /* r9 <- relocation offset */ subs r9, r6, r0 /* r9 <- relocation offset */
cmp r0, r6
moveq r9, #0 /* no relocation. offset(r9) = 0 */
beq relocate_done /* skip relocation */ beq relocate_done /* skip relocation */
mov r1, r6 /* r1 <- scratch for copy loop */ mov r1, r6 /* r1 <- scratch for copy loop */
ldr r3, _bss_start_ofs ldr r3, _bss_start_ofs
add r2, r0, r3 /* r2 <- source end address */ add r2, r0, r3 /* r2 <- source end address */
copy_loop: copy_loop:
ldmia r0!, {r9-r10} /* copy from source address [r0] */ ldmia r0!, {r10-r11} /* copy from source address [r0] */
stmia r1!, {r9-r10} /* copy to target address [r1] */ stmia r1!, {r10-r11} /* copy to target address [r1] */
cmp r0, r2 /* until source end address [r2] */ cmp r0, r2 /* until source end address [r2] */
blo copy_loop blo copy_loop
@ -228,7 +226,6 @@ copy_loop:
* fix .rel.dyn relocations * fix .rel.dyn relocations
*/ */
ldr r0, _TEXT_BASE /* r0 <- Text base */ ldr r0, _TEXT_BASE /* r0 <- Text base */
sub r9, r6, r0 /* r9 <- relocation offset */
ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */ ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
add r10, r10, r0 /* r10 <- sym table in FLASH */ add r10, r10, r0 /* r10 <- sym table in FLASH */
ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */ ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */

8
arch/arm/cpu/arm946es/start.S
View file

@ -167,16 +167,15 @@ relocate_code:
mov r6, r2 /* save addr of destination */ mov r6, r2 /* save addr of destination */
adr r0, _start adr r0, _start
cmp r0, r6 subs r9, r6, r0 /* r9 <- relocation offset */
moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */
beq relocate_done /* skip relocation */ beq relocate_done /* skip relocation */
mov r1, r6 /* r1 <- scratch for copy_loop */ mov r1, r6 /* r1 <- scratch for copy_loop */
ldr r3, _bss_start_ofs ldr r3, _bss_start_ofs
add r2, r0, r3 /* r2 <- source end address */ add r2, r0, r3 /* r2 <- source end address */
copy_loop: copy_loop:
ldmia r0!, {r9-r10} /* copy from source address [r0] */ ldmia r0!, {r10-r11} /* copy from source address [r0] */
stmia r1!, {r9-r10} /* copy to target address [r1] */ stmia r1!, {r10-r11} /* copy to target address [r1] */
cmp r0, r2 /* until source end address [r2] */ cmp r0, r2 /* until source end address [r2] */
blo copy_loop blo copy_loop
@ -185,7 +184,6 @@ copy_loop:
* fix .rel.dyn relocations * fix .rel.dyn relocations
*/ */
ldr r0, _TEXT_BASE /* r0 <- Text base */ ldr r0, _TEXT_BASE /* r0 <- Text base */
sub r9, r6, r0 /* r9 <- relocation offset */
ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */ ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
add r10, r10, r0 /* r10 <- sym table in FLASH */ add r10, r10, r0 /* r10 <- sym table in FLASH */
ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */ ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */

8
arch/arm/cpu/arm_intcm/start.S
View file

@ -163,16 +163,15 @@ relocate_code:
mov r6, r2 /* save addr of destination */ mov r6, r2 /* save addr of destination */
adr r0, _start adr r0, _start
cmp r0, r6 subs r9, r6, r0 /* r9 <- relocation offset */
moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */
beq relocate_done /* skip relocation */ beq relocate_done /* skip relocation */
mov r1, r6 /* r1 <- scratch for copy_loop */ mov r1, r6 /* r1 <- scratch for copy_loop */
ldr r3, _bss_start_ofs ldr r3, _bss_start_ofs
add r2, r0, r3 /* r2 <- source end address */ add r2, r0, r3 /* r2 <- source end address */
copy_loop: copy_loop:
ldmia r0!, {r9-r10} /* copy from source address [r0] */ ldmia r0!, {r10-r11} /* copy from source address [r0] */
stmia r1!, {r9-r10} /* copy to target address [r1] */ stmia r1!, {r10-r11} /* copy to target address [r1] */
cmp r0, r2 /* until source end address [r2] */ cmp r0, r2 /* until source end address [r2] */
blo copy_loop blo copy_loop
@ -181,7 +180,6 @@ copy_loop:
* fix .rel.dyn relocations * fix .rel.dyn relocations
*/ */
ldr r0, _TEXT_BASE /* r0 <- Text base */ ldr r0, _TEXT_BASE /* r0 <- Text base */
sub r9, r6, r0 /* r9 <- relocation offset */
ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */ ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
add r10, r10, r0 /* r10 <- sym table in FLASH */ add r10, r10, r0 /* r10 <- sym table in FLASH */
ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */ ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */

8
arch/arm/cpu/armv7/start.S
View file

@ -175,16 +175,15 @@ ENTRY(relocate_code)
mov r6, r2 /* save addr of destination */ mov r6, r2 /* save addr of destination */
adr r0, _start adr r0, _start
cmp r0, r6 subs r9, r6, r0 /* r9 <- relocation offset */
moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */
beq relocate_done /* skip relocation */ beq relocate_done /* skip relocation */
mov r1, r6 /* r1 <- scratch for copy_loop */ mov r1, r6 /* r1 <- scratch for copy_loop */
ldr r3, _image_copy_end_ofs ldr r3, _image_copy_end_ofs
add r2, r0, r3 /* r2 <- source end address */ add r2, r0, r3 /* r2 <- source end address */
copy_loop: copy_loop:
ldmia r0!, {r9-r10} /* copy from source address [r0] */ ldmia r0!, {r10-r11} /* copy from source address [r0] */
stmia r1!, {r9-r10} /* copy to target address [r1] */ stmia r1!, {r10-r11} /* copy to target address [r1] */
cmp r0, r2 /* until source end address [r2] */ cmp r0, r2 /* until source end address [r2] */
blo copy_loop blo copy_loop
@ -192,7 +191,6 @@ copy_loop:
* fix .rel.dyn relocations * fix .rel.dyn relocations
*/ */
ldr r0, _TEXT_BASE /* r0 <- Text base */ ldr r0, _TEXT_BASE /* r0 <- Text base */
sub r9, r6, r0 /* r9 <- relocation offset */
ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */ ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
add r10, r10, r0 /* r10 <- sym table in FLASH */ add r10, r10, r0 /* r10 <- sym table in FLASH */
ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */ ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */

8
arch/arm/cpu/ixp/start.S
View file

@ -265,16 +265,15 @@ relocate_code:
mov r6, r2 /* save addr of destination */ mov r6, r2 /* save addr of destination */
adr r0, _start adr r0, _start
cmp r0, r6 subs r9, r6, r0 /* r9 <- relocation offset */
moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */
beq relocate_done /* skip relocation */ beq relocate_done /* skip relocation */
mov r1, r6 /* r1 <- scratch for copy_loop */ mov r1, r6 /* r1 <- scratch for copy_loop */
ldr r3, _bss_start_ofs ldr r3, _bss_start_ofs
add r2, r0, r3 /* r2 <- source end address */ add r2, r0, r3 /* r2 <- source end address */
copy_loop: copy_loop:
ldmia r0!, {r9-r10} /* copy from source address [r0] */ ldmia r0!, {r10-r11} /* copy from source address [r0] */
stmia r1!, {r9-r10} /* copy to target address [r1] */ stmia r1!, {r10-r11} /* copy to target address [r1] */
cmp r0, r2 /* until source end address [r2] */ cmp r0, r2 /* until source end address [r2] */
blo copy_loop blo copy_loop
@ -283,7 +282,6 @@ copy_loop:
* fix .rel.dyn relocations * fix .rel.dyn relocations
*/ */
ldr r0, _TEXT_BASE /* r0 <- Text base */ ldr r0, _TEXT_BASE /* r0 <- Text base */
sub r9, r6, r0 /* r9 <- relocation offset */
ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */ ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
add r10, r10, r0 /* r10 <- sym table in FLASH */ add r10, r10, r0 /* r10 <- sym table in FLASH */
ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */ ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */

8
arch/arm/cpu/pxa/start.S
View file

@ -187,16 +187,15 @@ relocate_code:
#endif #endif
adr r0, _start adr r0, _start
cmp r0, r6 subs r9, r6, r0 /* r9 <- relocation offset */
moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */
beq relocate_done /* skip relocation */ beq relocate_done /* skip relocation */
mov r1, r6 /* r1 <- scratch for copy_loop */ mov r1, r6 /* r1 <- scratch for copy_loop */
ldr r3, _bss_start_ofs ldr r3, _bss_start_ofs
add r2, r0, r3 /* r2 <- source end address */ add r2, r0, r3 /* r2 <- source end address */
copy_loop: copy_loop:
ldmia r0!, {r9-r10} /* copy from source address [r0] */ ldmia r0!, {r10-r11} /* copy from source address [r0] */
stmia r1!, {r9-r10} /* copy to target address [r1] */ stmia r1!, {r10-r11} /* copy to target address [r1] */
cmp r0, r2 /* until source end address [r2] */ cmp r0, r2 /* until source end address [r2] */
blo copy_loop blo copy_loop
@ -205,7 +204,6 @@ copy_loop:
* fix .rel.dyn relocations * fix .rel.dyn relocations
*/ */
ldr r0, _TEXT_BASE /* r0 <- Text base */ ldr r0, _TEXT_BASE /* r0 <- Text base */
sub r9, r6, r0 /* r9 <- relocation offset */
ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */ ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
add r10, r10, r0 /* r10 <- sym table in FLASH */ add r10, r10, r0 /* r10 <- sym table in FLASH */
ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */ ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */

8
arch/arm/cpu/s3c44b0/start.S
View file

@ -148,16 +148,15 @@ relocate_code:
mov r6, r2 /* save addr of destination */ mov r6, r2 /* save addr of destination */
adr r0, _start adr r0, _start
cmp r0, r6 subs r9, r6, r0 /* r9 <- relocation offset */
moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */
beq relocate_done /* skip relocation */ beq relocate_done /* skip relocation */
mov r1, r6 /* r1 <- scratch for copy_loop */ mov r1, r6 /* r1 <- scratch for copy_loop */
ldr r3, _bss_start_ofs ldr r3, _bss_start_ofs
add r2, r0, r3 /* r2 <- source end address */ add r2, r0, r3 /* r2 <- source end address */
copy_loop: copy_loop:
ldmia r0!, {r9-r10} /* copy from source address [r0] */ ldmia r0!, {r10-r11} /* copy from source address [r0] */
stmia r1!, {r9-r10} /* copy to target address [r1] */ stmia r1!, {r10-r11} /* copy to target address [r1] */
cmp r0, r2 /* until source end address [r2] */ cmp r0, r2 /* until source end address [r2] */
blo copy_loop blo copy_loop
@ -166,7 +165,6 @@ copy_loop:
* fix .rel.dyn relocations * fix .rel.dyn relocations
*/ */
ldr r0, _TEXT_BASE /* r0 <- Text base */ ldr r0, _TEXT_BASE /* r0 <- Text base */
sub r9, r6, r0 /* r9 <- relocation offset */
ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */ ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
add r10, r10, r0 /* r10 <- sym table in FLASH */ add r10, r10, r0 /* r10 <- sym table in FLASH */
ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */ ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */

8
arch/arm/cpu/sa1100/start.S
View file

@ -152,16 +152,15 @@ relocate_code:
mov r6, r2 /* save addr of destination */ mov r6, r2 /* save addr of destination */
adr r0, _start adr r0, _start
cmp r0, r6 subs r9, r6, r0 /* r9 <- relocation offset */
moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */
beq relocate_done /* skip relocation */ beq relocate_done /* skip relocation */
mov r1, r6 /* r1 <- scratch for copy_loop */ mov r1, r6 /* r1 <- scratch for copy_loop */
ldr r3, _bss_start_ofs ldr r3, _bss_start_ofs
add r2, r0, r3 /* r2 <- source end address */ add r2, r0, r3 /* r2 <- source end address */
copy_loop: copy_loop:
ldmia r0!, {r9-r10} /* copy from source address [r0] */ ldmia r0!, {r10-r11} /* copy from source address [r0] */
stmia r1!, {r9-r10} /* copy to target address [r1] */ stmia r1!, {r10-r11} /* copy to target address [r1] */
cmp r0, r2 /* until source end address [r2] */ cmp r0, r2 /* until source end address [r2] */
blo copy_loop blo copy_loop
@ -170,7 +169,6 @@ copy_loop:
* fix .rel.dyn relocations * fix .rel.dyn relocations
*/ */
ldr r0, _TEXT_BASE /* r0 <- Text base */ ldr r0, _TEXT_BASE /* r0 <- Text base */
sub r9, r6, r0 /* r9 <- relocation offset */
ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */ ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
add r10, r10, r0 /* r10 <- sym table in FLASH */ add r10, r10, r0 /* r10 <- sym table in FLASH */
ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */ ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */