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Merge git://git.denx.de/u-boot-mmc
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commit
4bafceff0e
4 changed files with 35 additions and 27 deletions
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@ -67,7 +67,7 @@ struct hsmmc {
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struct omap_hsmmc_plat {
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struct mmc_config cfg;
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struct hsmmc *base_addr;
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struct mmc mmc;
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struct mmc *mmc;
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bool cd_inverted;
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u32 controller_flags;
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const char *hw_rev;
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@ -239,6 +239,15 @@ config MMC_OMAP_HS
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If unsure, say N.
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config MMC_OMAP_HS_ADMA
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bool "ADMA support for OMAP HS MMC"
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depends on MMC_OMAP_HS && !OMAP34XX
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default y if !AM33XX
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help
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This enables support for the ADMA2 controller (SDA3.00 Part A2 DMA
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controller). If supported by the hardware, selecting this option will
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increase performances.
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config MMC_OMAP36XX_PINS
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bool "Enable MMC1 on OMAP36xx/37xx"
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depends on OMAP34XX && MMC_OMAP_HS
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@ -181,23 +181,18 @@ const char *mmc_mode_name(enum bus_mode mode)
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static uint mmc_mode2freq(struct mmc *mmc, enum bus_mode mode)
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{
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static const int freqs[] = {
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[MMC_LEGACY] = 25000000,
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[SD_LEGACY] = 25000000,
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[MMC_HS] = 26000000,
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[SD_HS] = 50000000,
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#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
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[MMC_HS_52] = 52000000,
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[MMC_DDR_52] = 52000000,
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[UHS_SDR12] = 25000000,
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[UHS_SDR25] = 50000000,
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[UHS_SDR50] = 100000000,
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[UHS_DDR50] = 50000000,
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#ifdef MMC_SUPPORTS_TUNING
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[UHS_SDR104] = 208000000,
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#endif
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#endif
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[MMC_HS_52] = 52000000,
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[MMC_DDR_52] = 52000000,
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#if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
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[MMC_HS_200] = 200000000,
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#endif
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};
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if (mode == MMC_LEGACY)
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@ -1974,7 +1969,7 @@ static int mmc_startup_v4(struct mmc *mmc)
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return -ENOMEM;
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memcpy(mmc->ext_csd, ext_csd, MMC_MAX_BLOCK_LEN);
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if (ext_csd[EXT_CSD_REV] > ARRAY_SIZE(mmc_versions))
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if (ext_csd[EXT_CSD_REV] >= ARRAY_SIZE(mmc_versions))
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return -EINVAL;
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mmc->version = mmc_versions[ext_csd[EXT_CSD_REV]];
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@ -2658,12 +2653,7 @@ void mmc_set_preinit(struct mmc *mmc, int preinit)
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mmc->preinit = preinit;
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}
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#if CONFIG_IS_ENABLED(DM_MMC) && defined(CONFIG_SPL_BUILD)
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static int mmc_probe(bd_t *bis)
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{
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return 0;
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}
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#elif CONFIG_IS_ENABLED(DM_MMC)
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#if CONFIG_IS_ENABLED(DM_MMC)
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static int mmc_probe(bd_t *bis)
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{
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int ret, i;
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@ -93,7 +93,7 @@ struct omap_hsmmc_data {
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enum bus_mode mode;
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#endif
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u8 controller_flags;
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#ifndef CONFIG_OMAP34XX
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#ifdef CONFIG_MMC_OMAP_HS_ADMA
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struct omap_hsmmc_adma_desc *adma_desc_table;
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uint desc_slot;
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#endif
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@ -117,7 +117,7 @@ struct omap_mmc_of_data {
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u8 controller_flags;
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};
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#ifndef CONFIG_OMAP34XX
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#ifdef CONFIG_MMC_OMAP_HS_ADMA
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struct omap_hsmmc_adma_desc {
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u8 attr;
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u8 reserved;
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@ -741,7 +741,7 @@ static int omap_hsmmc_init_setup(struct mmc *mmc)
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return -ETIMEDOUT;
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}
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}
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#ifndef CONFIG_OMAP34XX
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#ifdef CONFIG_MMC_OMAP_HS_ADMA
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reg_val = readl(&mmc_base->hl_hwinfo);
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if (reg_val & MADMA_EN)
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priv->controller_flags |= OMAP_HSMMC_USE_ADMA;
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@ -834,7 +834,7 @@ static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit)
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}
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}
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#ifndef CONFIG_OMAP34XX
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#ifdef CONFIG_MMC_OMAP_HS_ADMA
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static void omap_hsmmc_adma_desc(struct mmc *mmc, char *buf, u16 len, bool end)
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{
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struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
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@ -1037,7 +1037,7 @@ static int omap_hsmmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
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else
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flags |= (DP_DATA | DDIR_WRITE);
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#ifndef CONFIG_OMAP34XX
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#ifdef CONFIG_MMC_OMAP_HS_ADMA
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if ((priv->controller_flags & OMAP_HSMMC_USE_ADMA) &&
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!mmc_is_tuning_cmd(cmd->cmdidx)) {
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omap_hsmmc_prepare_data(mmc, data);
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@ -1082,7 +1082,7 @@ static int omap_hsmmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
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}
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}
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#ifndef CONFIG_OMAP34XX
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#ifdef CONFIG_MMC_OMAP_HS_ADMA
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if ((priv->controller_flags & OMAP_HSMMC_USE_ADMA) && data &&
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!mmc_is_tuning_cmd(cmd->cmdidx)) {
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u32 sz_mb, timeout;
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@ -1181,8 +1181,9 @@ static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size)
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return 0;
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}
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#if CONFIG_IS_ENABLED(MMC_WRITE)
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static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
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unsigned int size)
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unsigned int size)
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{
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unsigned int *input_buf = (unsigned int *)buf;
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unsigned int mmc_stat;
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@ -1235,7 +1236,13 @@ static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
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}
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return 0;
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}
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#else
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static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
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unsigned int size)
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{
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return -ENOTSUPP;
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}
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#endif
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static void omap_hsmmc_stop_clock(struct hsmmc *mmc_base)
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{
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writel(readl(&mmc_base->sysctl) & ~CEN_ENABLE, &mmc_base->sysctl);
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@ -1825,6 +1832,8 @@ static int omap_hsmmc_ofdata_to_platdata(struct udevice *dev)
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if (ret < 0)
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return ret;
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if (!cfg->f_max)
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cfg->f_max = 52000000;
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cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
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cfg->f_min = 400000;
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cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
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@ -1858,8 +1867,8 @@ static int omap_hsmmc_ofdata_to_platdata(struct udevice *dev)
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static int omap_hsmmc_bind(struct udevice *dev)
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{
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struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
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return mmc_bind(dev, &plat->mmc, &plat->cfg);
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plat->mmc = calloc(1, sizeof(struct mmc));
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return mmc_bind(dev, plat->mmc, &plat->cfg);
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}
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#endif
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static int omap_hsmmc_probe(struct udevice *dev)
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@ -1882,7 +1891,7 @@ static int omap_hsmmc_probe(struct udevice *dev)
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#endif
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#ifdef CONFIG_BLK
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mmc = &plat->mmc;
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mmc = plat->mmc;
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#else
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mmc = mmc_create(cfg, priv);
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if (mmc == NULL)
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