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https://github.com/Fishwaldo/u-boot.git
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video: starfive: Add StarFive JH7110 Devkits board support
Make the code be compatible with the StarFive Devkits board. The code is ported from tag JH7110_DVK_515_v3.9.3 of Devkits repo. Signed-off-by: Keith Zhao <keith.zhao@starfivetech.com> Signed-off-by: Shengyang Chen <shengyang.chen@starfivetech.com> Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
This commit is contained in:
Hal Feng
parent
b5cb74c260
commit
4bf24b4717
4 changed files with 199 additions and 28 deletions
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@ -220,7 +220,7 @@ static ssize_t cdns_dsi_transfer(struct mipi_dsi_host *host,
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ret = wait_for_send_done(dsi, MIPI_FIFO_TIMEOUT);
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if (!ret) {
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printf("wait tx done timeout!\n");
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debug("wait tx done timeout!\n");
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return -ETIMEDOUT;
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}
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udelay(10);
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@ -285,7 +285,7 @@ static int mipi_dsi_northwest_init(struct udevice *dev,
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priv->phy_base = (void *)dev_read_addr_name(device->dev, "phy");
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if ((fdt_addr_t)priv->dsi_base == FDT_ADDR_T_NONE || (fdt_addr_t)priv->phy_base == FDT_ADDR_T_NONE) {
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printf("dsi dt register address error\n");
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debug("dsi dt register address error\n");
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return -EINVAL;
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}
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priv->link_initialized = false;
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@ -300,21 +300,38 @@ static int mipi_dsi_enable(struct udevice *dev)
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priv->phy_ops->init(priv->device);
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priv->phy_ops->post_set_mode(priv->device, MIPI_DSI_MODE_VIDEO);
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cdns_dsi_init_link(priv, priv->device);
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writel(0x00670067, priv->dsi_base + 0x000000c0);
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writel(0x00cb0960, priv->dsi_base + 0x000000c4);
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writel(0x0003b145, priv->dsi_base + 0x000000b4);
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writel(0x000001e0, priv->dsi_base + 0x000000b8);
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writel(0x00000a9e, priv->dsi_base + 0x000000d0);
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writel(0x0a980000, priv->dsi_base + 0x000000f8);
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writel(0x00000b0f, priv->dsi_base + 0x000000cc);
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writel(0x7c3c0aae, priv->dsi_base + 0x000000dc);
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writel(0x0032dcd3, priv->dsi_base + 0x00000014);
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writel(0x00032dcd, priv->dsi_base + 0x00000018);
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writel(0x80b8fe00, priv->dsi_base + 0x000000b0);
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writel(0x00020027, priv->dsi_base + 0x00000004);
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writel(0x00004018, priv->dsi_base + 0x0000000c);
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debug("priv->timings.hactive.typ %d----\n",priv->timings.hactive.typ);
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debug("priv->timings.vactive.typ %d----\n",priv->timings.vactive.typ);
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if (priv->timings.hactive.typ == 800)
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{
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writel(0x00670067, priv->dsi_base + 0x000000c0);
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writel(0x00cb0960, priv->dsi_base + 0x000000c4);
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writel(0x0003b145, priv->dsi_base + 0x000000b4);
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writel(0x000001e0, priv->dsi_base + 0x000000b8);
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writel(0x00000a9e, priv->dsi_base + 0x000000d0);
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writel(0x0a980000, priv->dsi_base + 0x000000f8);
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writel(0x00000b0f, priv->dsi_base + 0x000000cc);
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writel(0x7c3c0aae, priv->dsi_base + 0x000000dc);
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writel(0x0032dcd3, priv->dsi_base + 0x00000014);
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writel(0x00032dcd, priv->dsi_base + 0x00000018);
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writel(0x80b8fe00, priv->dsi_base + 0x000000b0);
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writel(0x00020027, priv->dsi_base + 0x00000004);
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writel(0x00004018, priv->dsi_base + 0x0000000c);
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}else if (priv->timings.hactive.typ == 1920){
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writel(0x01d30081, priv->dsi_base + 0x000000c0);
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writel(0x01171680, priv->dsi_base + 0x000000c4);
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writel(0x00003905, priv->dsi_base + 0x000000b4);
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writel(0x00000438, priv->dsi_base + 0x000000b8);
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writel(0x00001976, priv->dsi_base + 0x000000d0);
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writel(0x19700000, priv->dsi_base + 0x000000f8);
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writel(0x00001a01, priv->dsi_base + 0x000000cc);
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writel(0x98900661, priv->dsi_base + 0x000000dc);
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writel(0x003f9403, priv->dsi_base + 0x00000014);
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writel(0x0003f940, priv->dsi_base + 0x00000018);
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writel(0x80b8fe00, priv->dsi_base + 0x000000b0);
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writel(0x00020027, priv->dsi_base + 0x00000004);
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writel(0x000040f8, priv->dsi_base + 0x0000000c);
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}
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return 0;
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}
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@ -114,7 +114,13 @@ static void dsi_phy_post_set_mode(void *priv_data, unsigned long mode_flags)
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if (!priv)
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return;
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bitrate = 750000000;//1188M 60fps
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// bitrate = 750000000;//1188M 60fps
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debug("dsi_phy_post_set_mode priv->timings.hactive.typ %d----\n",priv->timings.hactive.typ);
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debug("dsi_phy_post_set_mode priv->timings.vactive.typ %d----\n",priv->timings.vactive.typ);
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if (priv->timings.hactive.typ == 800)
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bitrate = 750000000;
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else if(priv->timings.hactive.typ == 1920)
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bitrate = 900000000;//1188M 60fps
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sf_dphy_set_reg(priv->phy_reg + 0x8, 0x10,
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RG_CDTX_L0N_HSTX_RES_SHIFT, RG_CDTX_L0N_HSTX_RES_MASK);
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@ -255,11 +261,24 @@ static int dsi_sf_attach(struct udevice *dev)
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struct display_timing timings;
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int ret;
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#if CONFIG_IS_ENABLED(TARGET_STARFIVE_DEVKITS)
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ret = uclass_get_device_by_name(UCLASS_PANEL, "seeed_panel@45", &priv->panel);
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if (ret) {
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debug("Could not get seeed_panel@45: %d\n", ret);
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ret = uclass_get_device_by_name(UCLASS_PANEL, "lt8911exb_i2c@29", &priv->panel);
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if (ret) {
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debug("Could not get lt8911exb_i2c@29: %d\n", ret);
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return ret;
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}
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}
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#else
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ret = uclass_first_device(UCLASS_PANEL, &priv->panel);
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if (ret) {
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debug("panel device error %d\n", ret);
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return ret;
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}
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#endif
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debug("%s,priv->panel->name = %s\n", __func__,priv->panel->name);
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mplat = dev_get_plat(priv->panel);
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@ -273,14 +292,15 @@ static int dsi_sf_attach(struct udevice *dev)
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ret = ofnode_decode_display_timing(dev_ofnode(priv->panel),
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0, &timings);
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if (ret) {
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printf("decode display timing error %d\n", ret);
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debug("decode display timing error %d\n", ret);
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return ret;
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}
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}
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priv->timings = timings;
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ret = uclass_get_device(UCLASS_DSI_HOST, 0, &priv->dsi_host);
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if (ret) {
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printf("No video dsi host detected %d\n", ret);
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debug("No video dsi host detected %d\n", ret);
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return ret;
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}
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@ -288,7 +308,7 @@ static int dsi_sf_attach(struct udevice *dev)
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mplat->lanes,
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&dsi_stm_phy_ops);
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if (ret) {
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printf("failed to initialize mipi dsi host\n");
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debug("failed to initialize mipi dsi host\n");
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return ret;
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}
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@ -302,13 +322,13 @@ static int dsi_sf_set_backlight(struct udevice *dev, int percent)
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ret = dsi_host_enable(priv->dsi_host);
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if (ret) {
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printf("failed to enable mipi dsi host\n");
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debug("failed to enable mipi dsi host\n");
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return ret;
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}
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ret = panel_enable_backlight(priv->panel);
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if (ret) {
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printf("panel %s enable backlight error %d\n",
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debug("panel %s enable backlight error %d\n",
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priv->panel->name, ret);
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return ret;
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}
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@ -442,7 +462,7 @@ static int dsi_sf_probe(struct udevice *dev)
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ret = dev_read_u32(dev, "data-lanes-num", &priv->data_lanes);
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if (ret) {
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printf("fail to get data lanes property %d\n", ret);
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debug("fail to get data lanes property %d\n", ret);
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return 0;
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}
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@ -508,13 +528,13 @@ static int dsi_sf_probe(struct udevice *dev)
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debug("%s ok: ID_REG val = %08x\n", __func__, val);
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if (REV_VENDOR_ID(val) != 0xcad) {
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printf("invalid vendor id\n");
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debug("invalid vendor id\n");
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ret = -EINVAL;
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}
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ret = cdns_check_register_access(dev);
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if (ret) {
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printf("error: r/w test generic reg failed\n");
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debug("error: r/w test generic reg failed\n");
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}
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val = readl(priv->dsi_reg + IP_CONF);
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@ -786,6 +786,7 @@ struct dsi_sf_priv {
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struct udevice *panel;
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struct udevice *dsi_host;
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unsigned int data_lanes;
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struct display_timing timings;
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struct clk dsi_sys_clk;
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struct clk apb_clk;
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@ -29,6 +29,7 @@
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#include <panel.h>
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#include "sf_vop.h"
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#include "sf_mipi.h"
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DECLARE_GLOBAL_DATA_PTR;
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@ -398,7 +399,9 @@ static int sf_display_init(struct udevice *dev, ulong fbbase, ofnode ep_node)
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debug("%s(%s, 0x%lx, %s)\n", __func__,
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dev_read_name(dev), fbbase, ofnode_get_name(ep_node));
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#if CONFIG_IS_ENABLED(TARGET_STARFIVE_EVB) || CONFIG_IS_ENABLED(TARGET_STARFIVE_VISIONFIVE2)
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struct udevice *panel = NULL;
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#endif
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ret = ofnode_read_u32(ep_node, "remote-endpoint", &remote_phandle);
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if (ret)
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@ -579,6 +582,7 @@ static int sf_display_init(struct udevice *dev, ulong fbbase, ofnode ep_node)
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return ret;
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}
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#if CONFIG_IS_ENABLED(TARGET_STARFIVE_EVB) || CONFIG_IS_ENABLED(TARGET_STARFIVE_VISIONFIVE2)
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ret = uclass_first_device_err(UCLASS_PANEL, &panel);
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if (ret) {
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if (ret != -ENODEV)
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@ -595,6 +599,7 @@ static int sf_display_init(struct udevice *dev, ulong fbbase, ofnode ep_node)
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return ret;
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}
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}
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#endif
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int err = clk_set_parent(&priv->dc_pix0, &priv->dc_pix_src);
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if (err) {
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@ -603,17 +608,40 @@ static int sf_display_init(struct udevice *dev, ulong fbbase, ofnode ep_node)
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return err;
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}
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#if CONFIG_IS_ENABLED(TARGET_STARFIVE_EVB) || CONFIG_IS_ENABLED(TARGET_STARFIVE_VISIONFIVE2)
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ulong new_rate = clk_set_rate(&priv->dc_pix_src, timing.pixelclock.typ);
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debug("new_rate %ld\n", new_rate);
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#endif
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dc_hw_init(dev);
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#if CONFIG_IS_ENABLED(TARGET_STARFIVE_EVB) || CONFIG_IS_ENABLED(TARGET_STARFIVE_VISIONFIVE2)
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uc_priv->xsize = timing.hactive.typ;
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uc_priv->ysize = timing.vactive.typ;
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if (IS_ENABLED(CONFIG_VIDEO_COPY))
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uc_plat->copy_base = uc_plat->base - uc_plat->size / 2;
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#else
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struct dsi_sf_priv *private = dev_get_priv(disp);
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uc_priv->xsize = private->timings.hactive.typ;
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uc_priv->ysize = private->timings.vactive.typ;
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debug("uc_priv->xsize %d\n", uc_priv->xsize);
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debug("uc_priv->ysize %d\n", uc_priv->ysize);
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if(uc_priv->xsize == 800)
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{
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ulong new_rate = clk_set_rate(&priv->dc_pix_src, 29700000);
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debug("new_rate %ld\n", new_rate);
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}
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if(uc_priv->xsize == 1920)
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{
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ulong new_rate = clk_set_rate(&priv->dc_pix_src, 148500000);
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debug("new_rate %ld\n", new_rate);
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}
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#endif
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#if CONFIG_IS_ENABLED(TARGET_STARFIVE_EVB) || CONFIG_IS_ENABLED(TARGET_STARFIVE_VISIONFIVE2)
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writel(0xc0001fff, priv->regs_hi+0x00000014); //csr_reg
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writel(0x000000e8, priv->regs_hi+0x00001a38); //csr_reg
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writel(0x00002000, priv->regs_hi+0x00001cc0); //csr_reg
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@ -663,10 +691,115 @@ static int sf_display_init(struct udevice *dev, ulong fbbase, ofnode ep_node)
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writel(0x00000000, priv->regs_hi+0x000024fc); //csr_reg
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writel(0x00011b25, priv->regs_hi+0x000024e8); //csr_reg
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writel(0x00000001, priv->regs_hi+0x00001ccc); //csr_reg
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priv->mipi_logo = true;
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return 0;
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#else
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if(uc_priv->xsize == 800)
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{
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writel(0xc0001fff, priv->regs_hi+0x00000014); //csr_reg
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writel(0x000000e8, priv->regs_hi+0x00001a38); //csr_reg
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writel(0x00002000, priv->regs_hi+0x00001cc0); //csr_reg
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writel(0x00000000, priv->regs_hi+0x000024d8); //csr_reg
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writel(0x03c00438, priv->regs_hi+0x000024e0); //csr_reg
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writel(0x03c00438, priv->regs_hi+0x00001810); //csr_reg
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writel(uc_plat->base, priv->regs_hi+0x00001400);
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writel(0x000010e0, priv->regs_hi+0x00001408); //csr_reg
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writel(0x000fb00b, priv->regs_hi+0x00001ce8); //csr_reg
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writel(0x0000a9a3, priv->regs_hi+0x00002510); //csr_reg
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writel(0x2c4e6f06, priv->regs_hi+0x00002508); //csr_reg
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writel(0xe6daec4f, priv->regs_hi+0x00002500); //csr_reg
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writel(0x18220000, priv->regs_hi+0x00001518); //csr_reg
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writel(0x00003000, priv->regs_hi+0x00001cc0); //csr_reg
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writel(0x00030000, priv->regs_hi+0x00001cc4); //csr_reg
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writel(0x00030000, priv->regs_hi+0x00001cc4); //csr_reg
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writel(0x00050c1a, priv->regs_hi+0x00001540); //csr_reg
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writel(0x00000001, priv->regs_hi+0x00002540); //csr_reg
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writel(0x00050c1a, priv->regs_hi+0x00001540); //csr_reg
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writel(0x4016120c, priv->regs_hi+0x00001544); //csr_reg
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writel(0x00000002, priv->regs_hi+0x00002544); //csr_reg
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writel(0x4016120c, priv->regs_hi+0x00001544); //csr_reg
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writel(0x001b1208, priv->regs_hi+0x00001548); //csr_reg
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writel(0x00000004, priv->regs_hi+0x00002548); //csr_reg
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writel(0x001b1208, priv->regs_hi+0x00001548); //csr_reg
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writel(0x0016110e, priv->regs_hi+0x0000154c); //csr_reg
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writel(0x00000005, priv->regs_hi+0x0000254c); //csr_reg
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writel(0x0016110e, priv->regs_hi+0x0000154c); //csr_reg
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writel(0x00000001, priv->regs_hi+0x00002518); //csr_reg
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writel(0x00000000, priv->regs_hi+0x00001a28); //csr_reg
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writel(0x03840320, priv->regs_hi+0x00001430); //csr_reg, hsize, htotal
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writel(0xc1bf837a, priv->regs_hi+0x00001438); //csr_reg, hsize blanking
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writel(0x022601e0, priv->regs_hi+0x00001440); //csr_reg, vsize
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writel(0xc110021c, priv->regs_hi+0x00001448); //csr_reg, vsize blanking
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writel(0x00000000, priv->regs_hi+0x000014b0); //csr_reg
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writel(0x000000e2, priv->regs_hi+0x00001cd0); //csr_reg
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writel(0x000000af, priv->regs_hi+0x000014d0); //csr_reg
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writel(0x00000005, priv->regs_hi+0x000014b8); //csr_reg
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writel(0x8dd0b774, priv->regs_hi+0x00001528); //csr_reg
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writel(0x00001111, priv->regs_hi+0x00001418); //csr_reg
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writel(0x00000000, priv->regs_hi+0x00001410); //csr_reg
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writel(0x00000000, priv->regs_hi+0x00002518); //csr_reg
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writel(0x00000006, priv->regs_hi+0x00001468); //csr_reg
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writel(0x00000000, priv->regs_hi+0x00001484); //csr_reg
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writel(0x00000006, priv->regs_hi+0x00001468); //csr_reg
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writel(0x00011b25, priv->regs_hi+0x000024e8); //csr_reg
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writel(0x00000000, priv->regs_hi+0x000024fc); //csr_reg
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writel(0x00011b25, priv->regs_hi+0x000024e8); //csr_reg
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writel(0x00000001, priv->regs_hi+0x00001ccc); //csr_reg
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}
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if(uc_priv->xsize == 1920)
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{
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writel(0xc0001fff, priv->regs_hi+0x00000014);
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writel(0x000000e8, priv->regs_hi+0x00001a38);
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writel(0x00002000, priv->regs_hi+0x00001cc0);
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writel(0x00000000, priv->regs_hi+0x000024d8);
|
||||
writel(0x04380780, priv->regs_hi+0x000024e0);
|
||||
writel(0x04380780, priv->regs_hi+0x00001810);
|
||||
writel(uc_plat->base, priv->regs_hi+0x00001400);
|
||||
writel(0x00001e00, priv->regs_hi+0x00001408);
|
||||
writel(0x00000000, priv->regs_hi+0x00001ce8);
|
||||
writel(0x0000a9a3, priv->regs_hi+0x00002510);
|
||||
writel(0x2c4e6f06, priv->regs_hi+0x00002508);
|
||||
writel(0xe6daec4f, priv->regs_hi+0x00002500);
|
||||
writel(0x18220000, priv->regs_hi+0x00001518);
|
||||
writel(0x00003000, priv->regs_hi+0x00001cc0);
|
||||
writel(0x00030000, priv->regs_hi+0x00001cc4);
|
||||
writel(0x00030000, priv->regs_hi+0x00001cc4);
|
||||
writel(0x00050c1a, priv->regs_hi+0x00001540);
|
||||
writel(0x00000001, priv->regs_hi+0x00002540);
|
||||
writel(0x00050c1a, priv->regs_hi+0x00001540);
|
||||
writel(0x4016120c, priv->regs_hi+0x00001544);
|
||||
writel(0x00000002, priv->regs_hi+0x00002544);
|
||||
writel(0x4016120c, priv->regs_hi+0x00001544);
|
||||
writel(0x001b1208, priv->regs_hi+0x00001548);
|
||||
writel(0x00000004, priv->regs_hi+0x00002548);
|
||||
writel(0x001b1208, priv->regs_hi+0x00001548);
|
||||
writel(0x0016110e, priv->regs_hi+0x0000154c);
|
||||
writel(0x00000005, priv->regs_hi+0x0000254c);
|
||||
writel(0x0016110e, priv->regs_hi+0x0000154c);
|
||||
writel(0x00000001, priv->regs_hi+0x00002518);
|
||||
writel(0x00000000, priv->regs_hi+0x00001a28);
|
||||
writel(0x08980780, priv->regs_hi+0x00001430);
|
||||
writel(0xc40207d8, priv->regs_hi+0x00001438);
|
||||
writel(0x04650438, priv->regs_hi+0x00001440);
|
||||
writel(0xc220843c, priv->regs_hi+0x00001448);
|
||||
writel(0x00000000, priv->regs_hi+0x000014b0);
|
||||
writel(0x000000e2, priv->regs_hi+0x00001cd0);
|
||||
writel(0x000000af, priv->regs_hi+0x000014d0);
|
||||
writel(0x00000005, priv->regs_hi+0x000014b8);
|
||||
writel(0x8dd0b774, priv->regs_hi+0x00001528);
|
||||
writel(0x00001111, priv->regs_hi+0x00001418);
|
||||
writel(0x00000000, priv->regs_hi+0x00001410);
|
||||
writel(0x00000000, priv->regs_hi+0x00002518);
|
||||
writel(0x00000006, priv->regs_hi+0x00001468);
|
||||
writel(0x00000000, priv->regs_hi+0x00001484);
|
||||
writel(0x00000006, priv->regs_hi+0x00001468);
|
||||
writel(0x00011b25, priv->regs_hi+0x000024e8);
|
||||
writel(0x00000000, priv->regs_hi+0x000024fc);
|
||||
writel(0x00011b25, priv->regs_hi+0x000024e8);
|
||||
writel(0x00000001, priv->regs_hi+0x00001ccc);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
priv->mipi_logo = true;
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue