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armv8: ls1088a: add PCIe dts node
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
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1 changed files with 48 additions and 0 deletions
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@ -75,4 +75,52 @@
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reg-names = "QuadSPI", "QuadSPI-memory";
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num-cs = <4>;
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};
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pcie@3400000 {
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compatible = "fsl,ls-pcie", "snps,dw-pcie";
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reg = <0x00 0x03400000 0x0 0x80000 /* dbi registers */
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0x00 0x03480000 0x0 0x80000 /* lut registers */
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0x00 0x034c0000 0x0 0x40000 /* pf controls registers */
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0x20 0x00000000 0x0 0x20000>; /* configuration space */
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reg-names = "dbi", "lut", "ctrl", "config";
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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num-lanes = <4>;
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bus-range = <0x0 0xff>;
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ranges = <0x81000000 0x0 0x00000000 0x20 0x00020000 0x0 0x00010000 /* downstream I/O */
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0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
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};
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pcie@3500000 {
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compatible = "fsl,ls-pcie", "snps,dw-pcie";
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reg = <0x00 0x03500000 0x0 0x80000 /* dbi registers */
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0x00 0x03580000 0x0 0x80000 /* lut registers */
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0x00 0x035c0000 0x0 0x40000 /* pf controls registers */
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0x28 0x00000000 0x0 0x20000>; /* configuration space */
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reg-names = "dbi", "lut", "ctrl", "config";
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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num-lanes = <4>;
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bus-range = <0x0 0xff>;
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ranges = <0x81000000 0x0 0x00000000 0x28 0x00020000 0x0 0x00010000 /* downstream I/O */
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0x82000000 0x0 0x40000000 0x28 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
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};
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pcie@3600000 {
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compatible = "fsl,ls-pcie", "snps,dw-pcie";
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reg = <0x00 0x03600000 0x0 0x80000 /* dbi registers */
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0x00 0x03680000 0x0 0x80000 /* lut registers */
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0x00 0x036c0000 0x0 0x40000 /* pf controls registers */
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0x30 0x00000000 0x0 0x20000>; /* configuration space */
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reg-names = "dbi", "lut", "ctrl", "config";
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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num-lanes = <8>;
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bus-range = <0x0 0xff>;
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ranges = <0x81000000 0x0 0x00000000 0x30 0x00020000 0x0 0x00010000 /* downstream I/O */
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0x82000000 0x0 0x40000000 0x30 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
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};
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};
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