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ColdFire: Multiple fixes for M5282EVB

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Incorrect CFG_HZ value, change 1000000 to 1000.
Rename #waring to #warning. RAMBAR1 uses twice
in start.S, rename the later to FLASHBAR. Insert
nop for DRAM setup. And, env_offset in linker file.

Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
This commit is contained in:
TsiChung Liew 2008-08-11 15:54:25 +00:00 • committed by John Rigby
parent 10db3a17a2
commit 4cb4e654ca
5 changed files with 12 additions and 6 deletions
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7
board/freescale/m5282evb/m5282evb.c
View file

@ -51,6 +51,7 @@ phys_size_t initdram (int board_type)
MCFSDRAMC_DCR = (0 MCFSDRAMC_DCR = (0
| MCFSDRAMC_DCR_RTIM_6 | MCFSDRAMC_DCR_RTIM_6
| MCFSDRAMC_DCR_RC((15 * dramclk)>>4)); | MCFSDRAMC_DCR_RC((15 * dramclk)>>4));
asm("nop");
/* Initialize DACR0 */ /* Initialize DACR0 */
MCFSDRAMC_DACR0 = (0 MCFSDRAMC_DACR0 = (0
@ -58,14 +59,17 @@ phys_size_t initdram (int board_type)
| MCFSDRAMC_DACR_CASL(1) | MCFSDRAMC_DACR_CASL(1)
| MCFSDRAMC_DACR_CBM(3) | MCFSDRAMC_DACR_CBM(3)
| MCFSDRAMC_DACR_PS_32); | MCFSDRAMC_DACR_PS_32);
asm("nop");
/* Initialize DMR0 */ /* Initialize DMR0 */
MCFSDRAMC_DMR0 = (0 MCFSDRAMC_DMR0 = (0
| ((dramsize - 1) & 0xFFFC0000) | ((dramsize - 1) & 0xFFFC0000)
| MCFSDRAMC_DMR_V); | MCFSDRAMC_DMR_V);
asm("nop");
/* Set IP (bit 3) in DACR */ /* Set IP (bit 3) in DACR */
MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_IP; MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_IP;
asm("nop");
/* Wait 30ns to allow banks to precharge */ /* Wait 30ns to allow banks to precharge */
for (i = 0; i < 5; i++) { for (i = 0; i < 5; i++) {
@ -74,9 +78,11 @@ phys_size_t initdram (int board_type)
/* Write to this block to initiate precharge */ /* Write to this block to initiate precharge */
*(u32 *)(CFG_SDRAM_BASE) = 0xA5A59696; *(u32 *)(CFG_SDRAM_BASE) = 0xA5A59696;
asm("nop");
/* Set RE (bit 15) in DACR */ /* Set RE (bit 15) in DACR */
MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_RE; MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_RE;
asm("nop");
/* Wait for at least 8 auto refresh cycles to occur */ /* Wait for at least 8 auto refresh cycles to occur */
for (i = 0; i < 2000; i++) { for (i = 0; i < 2000; i++) {
@ -85,6 +91,7 @@ phys_size_t initdram (int board_type)
/* Finish the configuration by issuing the IMRS. */ /* Finish the configuration by issuing the IMRS. */
MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_IMRS; MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_IMRS;
asm("nop");
/* Write to the SDRAM Mode Register */ /* Write to the SDRAM Mode Register */
*(u32 *)(CFG_SDRAM_BASE + 0x400) = 0xA5A59696; *(u32 *)(CFG_SDRAM_BASE + 0x400) = 0xA5A59696;

3
board/freescale/m5282evb/u-boot.lds
View file

@ -60,9 +60,8 @@ SECTIONS
lib_generic/string.o (.text) lib_generic/string.o (.text)
lib_generic/vsprintf.o (.text) lib_generic/vsprintf.o (.text)
lib_generic/crc32.o (.text) lib_generic/crc32.o (.text)
lib_generic/zlib.o (.text)
/* . = env_offset; */ . = env_offset;
common/environment.o(.text) common/environment.o(.text)
*(.text) *(.text)

2
cpu/mcf52x2/cpu_init.c
View file

@ -442,7 +442,7 @@ void cpu_init_f(void)
MCFCSM_CSMR0 = MCFCSM_CSMR_BAM(CFG_CS0_SIZE - 1) | MCFCSM_CSMR_V; MCFCSM_CSMR0 = MCFCSM_CSMR_BAM(CFG_CS0_SIZE - 1) | MCFCSM_CSMR_V;
#endif #endif
#else #else
#waring "Chip Select 0 are not initialized/used" #warning "Chip Select 0 are not initialized/used"
#endif #endif
#if defined(CFG_CS1_BASE) & defined(CFG_CS1_SIZE) & \ #if defined(CFG_CS1_BASE) & defined(CFG_CS1_SIZE) & \

2
cpu/mcf52x2/start.S
View file

@ -166,7 +166,7 @@ _after_flashbar_copy:
#else #else
/* Setup code to initialize FLASHBAR, if start from external Memory */ /* Setup code to initialize FLASHBAR, if start from external Memory */
move.l #(CFG_INT_FLASH_BASE + CFG_INT_FLASH_ENABLE), %d0 move.l #(CFG_INT_FLASH_BASE + CFG_INT_FLASH_ENABLE), %d0
movec %d0, %RAMBAR1 movec %d0, %FLASHBAR
#endif /* (TEXT_BASE == CFG_INT_FLASH_BASE) */ #endif /* (TEXT_BASE == CFG_INT_FLASH_BASE) */
#endif #endif

4
include/configs/M5282EVB.h
View file

@ -104,7 +104,7 @@
# define CONFIG_OVERWRITE_ETHADDR_ONCE # define CONFIG_OVERWRITE_ETHADDR_ONCE
#endif /* CONFIG_MCFFEC */ #endif /* CONFIG_MCFFEC */
#define CONFIG_HOSTNAME M5272C3 #define CONFIG_HOSTNAME M5282EVB
#define CONFIG_EXTRA_ENV_SETTINGS \ #define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \ "netdev=eth0\0" \
"loadaddr=10000\0" \ "loadaddr=10000\0" \
@ -134,7 +134,7 @@
#define CFG_MEMTEST_START 0x400 #define CFG_MEMTEST_START 0x400
#define CFG_MEMTEST_END 0x380000 #define CFG_MEMTEST_END 0x380000
#define CFG_HZ 1000000 #define CFG_HZ 1000
#define CFG_CLK 64000000 #define CFG_CLK 64000000
/* PLL Configuration: Ext Clock * 6 (see table 9-4 of MCF user manual) */ /* PLL Configuration: Ext Clock * 6 (see table 9-4 of MCF user manual) */