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bcm281xx: add support for "USB OTG clock"
enable this clock with the following: clk_usb_otg_enable((void *)HSOTG_BASE_ADDR) Signed-off-by: Steve Rae <srae@broadcom.com> Reviewed-by: Felipe Balbi <balbi@ti.com>
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parent
e38d1cb28c
commit
4d013d8fa8
6 changed files with 52 additions and 0 deletions
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@ -10,3 +10,4 @@ obj-y += clk-bcm281xx.o
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obj-y += clk-sdio.o
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obj-y += clk-sdio.o
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obj-y += clk-bsc.o
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obj-y += clk-bsc.o
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obj-$(CONFIG_BCM_SF2_ETH) += clk-eth.o
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obj-$(CONFIG_BCM_SF2_ETH) += clk-eth.o
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obj-y += clk-usb-otg.o
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@ -209,6 +209,10 @@ static struct peri_clk_data sdio4_sleep_data = {
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.gate = SW_ONLY_GATE(0x0360, 20, 4),
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.gate = SW_ONLY_GATE(0x0360, 20, 4),
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};
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};
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static struct bus_clk_data usb_otg_ahb_data = {
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.gate = HW_SW_GATE_AUTO(0x0348, 16, 0, 1),
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};
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static struct bus_clk_data sdio1_ahb_data = {
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static struct bus_clk_data sdio1_ahb_data = {
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.gate = HW_SW_GATE_AUTO(0x0358, 16, 0, 1),
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.gate = HW_SW_GATE_AUTO(0x0358, 16, 0, 1),
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};
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};
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@ -331,6 +335,17 @@ static struct ccu_clock esub_ccu_clk = {
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*/
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*/
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/* KPM bus clocks */
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/* KPM bus clocks */
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static struct bus_clock usb_otg_ahb_clk = {
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.clk = {
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.name = "usb_otg_ahb_clk",
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.parent = &kpm_ccu_clk.clk,
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.ops = &bus_clk_ops,
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.ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
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},
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.freq_tbl = master_ahb_freq_tbl,
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.data = &usb_otg_ahb_data,
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};
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static struct bus_clock sdio1_ahb_clk = {
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static struct bus_clock sdio1_ahb_clk = {
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.clk = {
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.clk = {
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.name = "sdio1_ahb_clk",
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.name = "sdio1_ahb_clk",
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@ -541,6 +556,7 @@ struct clk_lookup arch_clk_tbl[] = {
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CLK_LK(bsc2),
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CLK_LK(bsc2),
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CLK_LK(bsc3),
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CLK_LK(bsc3),
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/* Bus clocks */
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/* Bus clocks */
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CLK_LK(usb_otg_ahb),
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CLK_LK(sdio1_ahb),
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CLK_LK(sdio1_ahb),
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CLK_LK(sdio2_ahb),
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CLK_LK(sdio2_ahb),
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CLK_LK(sdio3_ahb),
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CLK_LK(sdio3_ahb),
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27
arch/arm/cpu/armv7/bcm281xx/clk-usb-otg.c
Normal file
27
arch/arm/cpu/armv7/bcm281xx/clk-usb-otg.c
Normal file
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@ -0,0 +1,27 @@
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/*
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* Copyright 2014 Broadcom Corporation.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/errno.h>
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#include <asm/arch/sysmap.h>
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#include "clk-core.h"
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/* Enable appropriate clocks for the USB OTG port */
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int clk_usb_otg_enable(void *base)
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{
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char *ahbstr;
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switch ((u32) base) {
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case HSOTG_BASE_ADDR:
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ahbstr = "usb_otg_ahb_clk";
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break;
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default:
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printf("%s: base 0x%p not found\n", __func__, base);
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return -EINVAL;
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}
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return clk_get_and_enable(ahbstr);
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}
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@ -19,3 +19,8 @@ int __weak clk_bsc_enable(void *base, u32 rate, u32 *actual_ratep)
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{
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{
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return 0;
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return 0;
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}
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}
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int __weak clk_usb_otg_enable(void *base)
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{
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return 0;
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}
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@ -13,6 +13,8 @@
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#define ESUB_CLK_BASE_ADDR 0x38000000
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#define ESUB_CLK_BASE_ADDR 0x38000000
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#define ESW_CONTRL_BASE_ADDR 0x38200000
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#define ESW_CONTRL_BASE_ADDR 0x38200000
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#define GPIO2_BASE_ADDR 0x35003000
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#define GPIO2_BASE_ADDR 0x35003000
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#define HSOTG_BASE_ADDR 0x3f120000
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#define HSOTG_CTRL_BASE_ADDR 0x3f130000
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#define KONA_MST_CLK_BASE_ADDR 0x3f001000
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#define KONA_MST_CLK_BASE_ADDR 0x3f001000
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#define KONA_SLV_CLK_BASE_ADDR 0x3e011000
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#define KONA_SLV_CLK_BASE_ADDR 0x3e011000
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#define PMU_BSC_BASE_ADDR 0x3500d000
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#define PMU_BSC_BASE_ADDR 0x3500d000
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@ -25,5 +25,6 @@ int clk_set_parent(struct clk *clk, struct clk *parent);
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struct clk *clk_get_parent(struct clk *clk);
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struct clk *clk_get_parent(struct clk *clk);
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int clk_sdio_enable(void *base, u32 rate, u32 *actual_ratep);
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int clk_sdio_enable(void *base, u32 rate, u32 *actual_ratep);
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int clk_bsc_enable(void *base);
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int clk_bsc_enable(void *base);
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int clk_usb_otg_enable(void *base);
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#endif
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#endif
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