GitHub-Mirror/u-boot
2
0
Fork 0
mirror of https://github.com/Fishwaldo/u-boot.git synced 2025-03-18 21:21:37 +00:00
Code Issues Projects Releases Packages Wiki Activity Actions

Merge branch 'fpga' of git://www.denx.de/git/u-boot-microblaze

Browse source
This commit is contained in:
Tom Rini 2014-05-22 14:38:19 -04:00
commit 4d16f67e7b
26 changed files with 297 additions and 33 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

13
README
View file

@ -2572,6 +2572,19 @@ CBFS (Coreboot Filesystem) support
Specify the number of FPGA devices to support.
CONFIG_CMD_FPGA_LOADMK
Enable support for fpga loadmk command
CONFIG_CMD_FPGA_LOADP
Enable support for fpga loadp command - load partial bitstream
CONFIG_CMD_FPGA_LOADBP
Enable support for fpga loadbp command - load partial bitstream
(Xilinx only)
CONFIG_SYS_FPGA_PROG_FEEDBACK
Enable printing of hash marks during FPGA configuration.

2
board/matrix_vision/common/mv_common.c
View file

@ -77,7 +77,7 @@ int mv_load_fpga(void)
return -1;
}
result = fpga_load(0, fpga_data, data_size);
result = fpga_load(0, fpga_data, data_size, BIT_FULL);
if (!result)
bootstage_mark(BOOTSTAGE_ID_START);

91
common/cmd_fpga.c
View file

@ -11,6 +11,7 @@
#include <common.h>
#include <command.h>
#include <fpga.h>
#include <fs.h>
#include <malloc.h>
/* Local functions */
@ -23,6 +24,9 @@ static int fpga_get_op(char *opstr);
#define FPGA_LOADB 2
#define FPGA_DUMP 3
#define FPGA_LOADMK 4
#define FPGA_LOADP 5
#define FPGA_LOADBP 6
#define FPGA_LOADFS 7
/* ------------------------------------------------------------------------- */
/* command form:
@ -45,6 +49,10 @@ int do_fpga(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
const char *fit_uname = NULL;
ulong fit_addr;
#endif
#if defined(CONFIG_CMD_FPGA_LOADFS)
fpga_fs_info fpga_fsinfo;
fpga_fsinfo.fstype = FS_TYPE_ANY;
#endif
if (devstr)
dev = (int) simple_strtoul(devstr, NULL, 16);
@ -52,6 +60,14 @@ int do_fpga(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
fpga_data = (void *)simple_strtoul(datastr, NULL, 16);
switch (argc) {
#if defined(CONFIG_CMD_FPGA_LOADFS)
case 9:
fpga_fsinfo.blocksize = (unsigned int)
simple_strtoul(argv[5], NULL, 16);
fpga_fsinfo.interface = argv[6];
fpga_fsinfo.dev_part = argv[7];
fpga_fsinfo.filename = argv[8];
#endif
case 5: /* fpga <op> <dev> <data> <datasize> */
data_size = simple_strtoul(argv[4], NULL, 16);
@ -120,16 +136,27 @@ int do_fpga(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
case FPGA_NONE:
case FPGA_INFO:
break;
#if defined(CONFIG_CMD_FPGA_LOADFS)
case FPGA_LOADFS:
/* Blocksize can be zero */
if (!fpga_fsinfo.interface || !fpga_fsinfo.dev_part ||
!fpga_fsinfo.filename)
wrong_parms = 1;
#endif
case FPGA_LOAD:
case FPGA_LOADP:
case FPGA_LOADB:
case FPGA_LOADBP:
case FPGA_DUMP:
if (!fpga_data || !data_size)
wrong_parms = 1;
break;
#if defined(CONFIG_CMD_FPGA_LOADMK)
case FPGA_LOADMK:
if (!fpga_data)
wrong_parms = 1;
break;
#endif
}
if (wrong_parms) {
@ -146,13 +173,32 @@ int do_fpga(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
break;
case FPGA_LOAD:
rc = fpga_load(dev, fpga_data, data_size);
rc = fpga_load(dev, fpga_data, data_size, BIT_FULL);
break;
#if defined(CONFIG_CMD_FPGA_LOADP)
case FPGA_LOADP:
rc = fpga_load(dev, fpga_data, data_size, BIT_PARTIAL);
break;
#endif
case FPGA_LOADB:
rc = fpga_loadbitstream(dev, fpga_data, data_size);
rc = fpga_loadbitstream(dev, fpga_data, data_size, BIT_FULL);
break;
#if defined(CONFIG_CMD_FPGA_LOADBP)
case FPGA_LOADBP:
rc = fpga_loadbitstream(dev, fpga_data, data_size, BIT_PARTIAL);
break;
#endif
#if defined(CONFIG_CMD_FPGA_LOADFS)
case FPGA_LOADFS:
rc = fpga_fsload(dev, fpga_data, data_size, &fpga_fsinfo);
break;
#endif
#if defined(CONFIG_CMD_FPGA_LOADMK)
case FPGA_LOADMK:
switch (genimg_get_format(fpga_data)) {
case IMAGE_FORMAT_LEGACY:
@ -179,7 +225,8 @@ int do_fpga(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
data = (ulong)image_get_data(hdr);
data_size = image_get_data_size(hdr);
}
rc = fpga_load(dev, (void *)data, data_size);
rc = fpga_load(dev, (void *)data, data_size,
BIT_FULL);
}
break;
#if defined(CONFIG_FIT)
@ -221,7 +268,8 @@ int do_fpga(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
return 1;
}
rc = fpga_load(dev, fit_data, data_size);
rc = fpga_load(dev, fit_data, data_size,
BIT_FULL);
}
break;
#endif
@ -231,6 +279,7 @@ int do_fpga(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
break;
}
break;
#endif
case FPGA_DUMP:
rc = fpga_dump(dev, fpga_data, data_size);
@ -257,8 +306,22 @@ static int fpga_get_op(char *opstr)
op = FPGA_LOADB;
else if (!strcmp("load", opstr))
op = FPGA_LOAD;
#if defined(CONFIG_CMD_FPGA_LOADP)
else if (!strcmp("loadp", opstr))
op = FPGA_LOADP;
#endif
#if defined(CONFIG_CMD_FPGA_LOADBP)
else if (!strcmp("loadbp", opstr))
op = FPGA_LOADBP;
#endif
#if defined(CONFIG_CMD_FPGA_LOADFS)
else if (!strcmp("loadfs", opstr))
op = FPGA_LOADFS;
#endif
#if defined(CONFIG_CMD_FPGA_LOADMK)
else if (!strcmp("loadmk", opstr))
op = FPGA_LOADMK;
#endif
else if (!strcmp("dump", opstr))
op = FPGA_DUMP;
@ -268,19 +331,39 @@ static int fpga_get_op(char *opstr)
return op;
}
#if defined(CONFIG_CMD_FPGA_LOADFS)
U_BOOT_CMD(fpga, 9, 1, do_fpga,
#else
U_BOOT_CMD(fpga, 6, 1, do_fpga,
#endif
"loadable FPGA image support",
"[operation type] [device number] [image address] [image size]\n"
"fpga operations:\n"
" dump\t[dev]\t\t\tLoad device to memory buffer\n"
" info\t[dev]\t\t\tlist known device information\n"
" load\t[dev] [address] [size]\tLoad device from memory buffer\n"
#if defined(CONFIG_CMD_FPGA_LOADP)
" loadp\t[dev] [address] [size]\t"
"Load device from memory buffer with partial bitstream\n"
#endif
" loadb\t[dev] [address] [size]\t"
"Load device from bitstream buffer (Xilinx only)\n"
#if defined(CONFIG_CMD_FPGA_LOADBP)
" loadbp\t[dev] [address] [size]\t"
"Load device from bitstream buffer with partial bitstream"
"(Xilinx only)\n"
#endif
#if defined(CONFIG_CMD_FPGA_LOADFS)
"Load device from filesystem (FAT by default) (Xilinx only)\n"
" loadfs [dev] [address] [image size] [blocksize] <interface>\n"
" [<dev[:part]>] <filename>\n"
#endif
#if defined(CONFIG_CMD_FPGA_LOADMK)
" loadmk [dev] [address]\tLoad device generated with mkimage"
#if defined(CONFIG_FIT)
"\n"
"\tFor loadmk operating on FIT format uImage address must include\n"
"\tsubimage unit name in the form of addr:<subimg_uname>"
#endif
#endif
);

36
drivers/fpga/fpga.c
View file

@ -173,16 +173,45 @@ int fpga_add(fpga_type devtype, void *desc)
/*
* Convert bitstream data and load into the fpga
*/
int __weak fpga_loadbitstream(int devnum, char *fpgadata, size_t size)
int __weak fpga_loadbitstream(int devnum, char *fpgadata, size_t size,
bitstream_type bstype)
{
printf("Bitstream support not implemented for this FPGA device\n");
return FPGA_FAIL;
}
#if defined(CONFIG_CMD_FPGA_LOADFS)
int fpga_fsload(int devnum, const void *buf, size_t size,
fpga_fs_info *fpga_fsinfo)
{
int ret_val = FPGA_FAIL; /* assume failure */
const fpga_desc *desc = fpga_validate(devnum, buf, size,
(char *)__func__);
if (desc) {
switch (desc->devtype) {
case fpga_xilinx:
#if defined(CONFIG_FPGA_XILINX)
ret_val = xilinx_loadfs(desc->devdesc, buf, size,
fpga_fsinfo);
#else
fpga_no_sup((char *)__func__, "Xilinx devices");
#endif
break;
default:
printf("%s: Invalid or unsupported device type %d\n",
__func__, desc->devtype);
}
}
return ret_val;
}
#endif
/*
* Generic multiplexing code
*/
int fpga_load(int devnum, const void *buf, size_t bsize)
int fpga_load(int devnum, const void *buf, size_t bsize, bitstream_type bstype)
{
int ret_val = FPGA_FAIL; /* assume failure */
const fpga_desc *desc = fpga_validate(devnum, buf, bsize,
@ -192,7 +221,8 @@ int fpga_load(int devnum, const void *buf, size_t bsize)
switch (desc->devtype) {
case fpga_xilinx:
#if defined(CONFIG_FPGA_XILINX)
ret_val = xilinx_load(desc->devdesc, buf, bsize);
ret_val = xilinx_load(desc->devdesc, buf, bsize,
bstype);
#else
fpga_no_sup((char *)__func__, "Xilinx devices");
#endif

3
drivers/fpga/spartan2.c
View file

@ -41,7 +41,8 @@ static int spartan2_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize);
/* ------------------------------------------------------------------------- */
/* Spartan-II Generic Implementation */
static int spartan2_load(xilinx_desc *desc, const void *buf, size_t bsize)
static int spartan2_load(xilinx_desc *desc, const void *buf, size_t bsize,
bitstream_type bstype)
{
int ret_val = FPGA_FAIL;

3
drivers/fpga/spartan3.c
View file

@ -45,7 +45,8 @@ static int spartan3_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize);
/* ------------------------------------------------------------------------- */
/* Spartan-II Generic Implementation */
static int spartan3_load(xilinx_desc *desc, const void *buf, size_t bsize)
static int spartan3_load(xilinx_desc *desc, const void *buf, size_t bsize,
bitstream_type bstype)
{
int ret_val = FPGA_FAIL;

3
drivers/fpga/virtex2.c
View file

@ -90,7 +90,8 @@ static int virtex2_ssm_dump(xilinx_desc *desc, const void *buf, size_t bsize);
static int virtex2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize);
static int virtex2_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize);
static int virtex2_load(xilinx_desc *desc, const void *buf, size_t bsize)
static int virtex2_load(xilinx_desc *desc, const void *buf, size_t bsize,
bitstream_type bstype)
{
int ret_val = FPGA_FAIL;

26
drivers/fpga/xilinx.c
View file

@ -24,7 +24,8 @@ static int xilinx_validate(xilinx_desc *desc, char *fn);
/* ------------------------------------------------------------------------- */
int fpga_loadbitstream(int devnum, char *fpgadata, size_t size)
int fpga_loadbitstream(int devnum, char *fpgadata, size_t size,
bitstream_type bstype)
{
unsigned int length;
unsigned int swapsize;
@ -127,19 +128,36 @@ int fpga_loadbitstream(int devnum, char *fpgadata, size_t size)
dataptr += 4;
printf(" bytes in bitstream = %d\n", swapsize);
return fpga_load(devnum, dataptr, swapsize);
return fpga_load(devnum, dataptr, swapsize, bstype);
}
int xilinx_load(xilinx_desc *desc, const void *buf, size_t bsize)
int xilinx_load(xilinx_desc *desc, const void *buf, size_t bsize,
bitstream_type bstype)
{
if (!xilinx_validate (desc, (char *)__FUNCTION__)) {
printf ("%s: Invalid device descriptor\n", __FUNCTION__);
return FPGA_FAIL;
}
return desc->operations->load(desc, buf, bsize);
return desc->operations->load(desc, buf, bsize, bstype);
}
#if defined(CONFIG_CMD_FPGA_LOADFS)
int xilinx_loadfs(xilinx_desc *desc, const void *buf, size_t bsize,
fpga_fs_info *fpga_fsinfo)
{
if (!xilinx_validate(desc, (char *)__func__)) {
printf("%s: Invalid device descriptor\n", __func__);
return FPGA_FAIL;
}
if (!desc->operations->loadfs)
return FPGA_FAIL;
return desc->operations->loadfs(desc, buf, bsize, fpga_fsinfo);
}
#endif
int xilinx_dump(xilinx_desc *desc, const void *buf, size_t bsize)
{
if (!xilinx_validate (desc, (char *)__FUNCTION__)) {

105
drivers/fpga/zynqpl.c
View file

@ -9,6 +9,7 @@
#include <common.h>
#include <asm/io.h>
#include <fs.h>
#include <zynqpl.h>
#include <linux/sizes.h>
#include <asm/arch/hardware.h>
@ -194,7 +195,7 @@ static int zynq_dma_transfer(u32 srcbuf, u32 srclen, u32 dstbuf, u32 dstlen)
return FPGA_SUCCESS;
}
static int zynq_dma_xfer_init(u32 partialbit)
static int zynq_dma_xfer_init(bitstream_type bstype)
{
u32 status, control, isr_status;
unsigned long ts;
@ -202,7 +203,7 @@ static int zynq_dma_xfer_init(u32 partialbit)
/* Clear loopback bit */
clrbits_le32(&devcfg_base->mctrl, DEVCFG_MCTRL_PCAP_LPBK);
if (!partialbit) {
if (bstype != BIT_PARTIAL) {
zynq_slcr_devcfg_disable();
/* Setting PCFG_PROG_B signal to high */
@ -322,16 +323,11 @@ static u32 *zynq_align_dma_buffer(u32 *buf, u32 len, u32 swap)
static int zynq_validate_bitstream(xilinx_desc *desc, const void *buf,
size_t bsize, u32 blocksize, u32 *swap,
u32 *partialbit)
bitstream_type *bstype)
{
u32 *buf_start;
u32 diff;
/* Detect if we are going working with partial or full bitstream */
if (bsize != desc->size) {
printf("%s: Working with partial bitstream\n", __func__);
*partialbit = 1;
}
buf_start = check_data((u8 *)buf, blocksize, swap);
if (!buf_start)
@ -351,17 +347,16 @@ static int zynq_validate_bitstream(xilinx_desc *desc, const void *buf,
return FPGA_FAIL;
}
if (zynq_dma_xfer_init(*partialbit))
if (zynq_dma_xfer_init(*bstype))
return FPGA_FAIL;
return 0;
}
static int zynq_load(xilinx_desc *desc, const void *buf, size_t bsize)
static int zynq_load(xilinx_desc *desc, const void *buf, size_t bsize,
bitstream_type bstype)
{
unsigned long ts; /* Timestamp */
u32 partialbit = 0;
u32 isr_status, swap;
/*
@ -369,7 +364,7 @@ static int zynq_load(xilinx_desc *desc, const void *buf, size_t bsize)
* in chunks
*/
if (zynq_validate_bitstream(desc, buf, bsize, bsize, &swap,
&partialbit))
&bstype))
return FPGA_FAIL;
buf = zynq_align_dma_buffer((u32 *)buf, bsize, swap);
@ -398,11 +393,92 @@ static int zynq_load(xilinx_desc *desc, const void *buf, size_t bsize)
debug("%s: FPGA config done\n", __func__);
if (bstype != BIT_PARTIAL)
zynq_slcr_devcfg_enable();
return FPGA_SUCCESS;
}
#if defined(CONFIG_CMD_FPGA_LOADFS)
static int zynq_loadfs(xilinx_desc *desc, const void *buf, size_t bsize,
fpga_fs_info *fsinfo)
{
unsigned long ts; /* Timestamp */
u32 isr_status, swap;
u32 partialbit = 0;
u32 blocksize;
u32 pos = 0;
int fstype;
char *interface, *dev_part, *filename;
blocksize = fsinfo->blocksize;
interface = fsinfo->interface;
dev_part = fsinfo->dev_part;
filename = fsinfo->filename;
fstype = fsinfo->fstype;
if (fs_set_blk_dev(interface, dev_part, fstype))
return FPGA_FAIL;
if (fs_read(filename, (u32) buf, pos, blocksize) < 0)
return FPGA_FAIL;
if (zynq_validate_bitstream(desc, buf, bsize, blocksize, &swap,
&partialbit))
return FPGA_FAIL;
dcache_disable();
do {
buf = zynq_align_dma_buffer((u32 *)buf, blocksize, swap);
if (zynq_dma_transfer((u32)buf | 1, blocksize >> 2,
0xffffffff, 0))
return FPGA_FAIL;
bsize -= blocksize;
pos += blocksize;
if (fs_set_blk_dev(interface, dev_part, fstype))
return FPGA_FAIL;
if (bsize > blocksize) {
if (fs_read(filename, (u32) buf, pos, blocksize) < 0)
return FPGA_FAIL;
} else {
if (fs_read(filename, (u32) buf, pos, bsize) < 0)
return FPGA_FAIL;
}
} while (bsize > blocksize);
buf = zynq_align_dma_buffer((u32 *)buf, blocksize, swap);
if (zynq_dma_transfer((u32)buf | 1, bsize >> 2, 0xffffffff, 0))
return FPGA_FAIL;
dcache_enable();
isr_status = readl(&devcfg_base->int_sts);
/* Check FPGA configuration completion */
ts = get_timer(0);
while (!(isr_status & DEVCFG_ISR_PCFG_DONE)) {
if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) {
printf("%s: Timeout wait for FPGA to config\n",
__func__);
return FPGA_FAIL;
}
isr_status = readl(&devcfg_base->int_sts);
}
debug("%s: FPGA config done\n", __func__);
if (!partialbit)
zynq_slcr_devcfg_enable();
return FPGA_SUCCESS;
}
#endif
static int zynq_dump(xilinx_desc *desc, const void *buf, size_t bsize)
{
@ -411,6 +487,9 @@ static int zynq_dump(xilinx_desc *desc, const void *buf, size_t bsize)
struct xilinx_fpga_op zynq_op = {
.load = zynq_load,
#if defined(CONFIG_CMD_FPGA_LOADFS)
.loadfs = zynq_loadfs,
#endif
.dump = zynq_dump,
.info = zynq_info,
};

1
include/configs/GEN860T.h
View file

@ -219,6 +219,7 @@
#define CONFIG_CMD_ELF
#define CONFIG_CMD_DATE
#define CONFIG_CMD_FPGA
#define CONFIG_CMD_FPGA_LOADMK
#define CONFIG_CMD_MII
#define CONFIG_CMD_BEDBUG

1
include/configs/MVBC_P.h
View file

@ -89,6 +89,7 @@
#define CONFIG_CMD_SDRAM
#define CONFIG_CMD_PCI
#define CONFIG_CMD_FPGA
#define CONFIG_CMD_FPGA_LOADMK
#define CONFIG_CMD_I2C
#undef CONFIG_WATCHDOG

1
include/configs/MVBLM7.h
View file

@ -267,6 +267,7 @@
#define CONFIG_CMD_PCI
#define CONFIG_CMD_I2C
#define CONFIG_CMD_FPGA
#define CONFIG_CMD_FPGA_LOADMK
#define CONFIG_CMD_USB
#define CONFIG_DOS_PARTITION

1
include/configs/MVSMR.h
View file

@ -74,6 +74,7 @@
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_FPGA
#define CONFIG_CMD_FPGA_LOADMK
#define CONFIG_CMD_I2C
#define CONFIG_CMD_MII
#define CONFIG_CMD_NET

1
include/configs/alpr.h
View file

@ -222,6 +222,7 @@
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_FPGA
#define CONFIG_CMD_FPGA_LOADMK
#define CONFIG_CMD_I2C
#undef CONFIG_CMD_LOADB
#undef CONFIG_CMD_LOADS

1
include/configs/astro_mcf5373l.h
View file

@ -88,6 +88,7 @@
#define CONFIG_CMD_LOADS
#define CONFIG_CMD_LOADB
#define CONFIG_CMD_FPGA
#define CONFIG_CMD_FPGA_LOADMK
#define CONFIG_CMDLINE_EDITING
#define CONFIG_SYS_HUSH_PARSER

1
include/configs/balloon3.h
View file

@ -54,6 +54,7 @@
#undef CONFIG_CMD_IMLS
#define CONFIG_CMD_USB
#define CONFIG_CMD_FPGA
#define CONFIG_CMD_FPGA_LOADMK
#undef CONFIG_LCD
/*

1
include/configs/coreboot.h
View file

@ -167,6 +167,7 @@
#define CONFIG_CMD_ECHO
#undef CONFIG_CMD_FLASH
#define CONFIG_CMD_FPGA
#define CONFIG_CMD_FPGA_LOADMK
#define CONFIG_CMD_GPIO
#define CONFIG_CMD_IMI
#undef CONFIG_CMD_IMLS

1
include/configs/grsim.h
View file

@ -53,6 +53,7 @@
#define CONFIG_CMD_DIAG
#define CONFIG_CMD_ECHO /* echo arguments */
#define CONFIG_CMD_FPGA /* FPGA configuration Support */
#define CONFIG_CMD_FPGA_LOADMK
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_ITEST /* Integer (and string) test */
#define CONFIG_CMD_LOADB /* loadb */

1
include/configs/grsim_leon2.h
View file

@ -51,6 +51,7 @@
#define CONFIG_CMD_DIAG
#define CONFIG_CMD_ECHO /* echo arguments */
#define CONFIG_CMD_FPGA /* FPGA configuration Support */
#define CONFIG_CMD_FPGA_LOADMK
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_ITEST /* Integer (and string) test */
#define CONFIG_CMD_LOADB /* loadb */

3
include/configs/iocon.h
View file

@ -62,7 +62,8 @@
* Commands additional to the ones defined in amcc-common.h
*/
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_FPGAD
#define CONFIG_CMD_FPGA
#define CONFIG_CMD_FPGA_LOADMK
#undef CONFIG_CMD_EEPROM
/*

1
include/configs/mt_ventoux.h
View file

@ -49,6 +49,7 @@
* FPGA
*/
#define CONFIG_CMD_FPGA
#define CONFIG_CMD_FPGA_LOADMK
#define CONFIG_FPGA
#define CONFIG_FPGA_XILINX
#define CONFIG_FPGA_SPARTAN3

1
include/configs/omap3_mvblx.h
View file

@ -127,6 +127,7 @@
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_PING
#define CONFIG_CMD_FPGA
#define CONFIG_CMD_FPGA_LOADMK
#define CONFIG_SYS_I2C
#define CONFIG_SYS_OMAP24_I2C_SPEED 100000

1
include/configs/x600.h
View file

@ -107,6 +107,7 @@
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_ENV
#define CONFIG_CMD_FPGA
#define CONFIG_CMD_FPGA_LOADMK
#define CONFIG_CMD_GPIO
#define CONFIG_CMD_I2C
#define CONFIG_CMD_MEMORY

4
include/configs/zynq-common.h
View file

@ -191,6 +191,10 @@
#define CONFIG_FPGA_XILINX
#define CONFIG_FPGA_ZYNQPL
#define CONFIG_CMD_FPGA
#define CONFIG_CMD_FPGA_LOADMK
#define CONFIG_CMD_FPGA_LOADP
#define CONFIG_CMD_FPGA_LOADBP
#define CONFIG_CMD_FPGA_LOADFS
/* Open Firmware flat tree */
#define CONFIG_OF_LIBFDT

20
include/fpga.h
View file

@ -35,13 +35,29 @@ typedef struct { /* typedef fpga_desc */
void *devdesc; /* real device descriptor */
} fpga_desc; /* end, typedef fpga_desc */
typedef struct { /* typedef fpga_desc */
unsigned int blocksize;
char *interface;
char *dev_part;
char *filename;
int fstype;
} fpga_fs_info;
typedef enum {
BIT_FULL = 0,
BIT_PARTIAL,
} bitstream_type;
/* root function definitions */
extern void fpga_init(void);
extern int fpga_add(fpga_type devtype, void *desc);
extern int fpga_count(void);
extern int fpga_load(int devnum, const void *buf, size_t bsize);
extern int fpga_loadbitstream(int devnum, char *fpgadata, size_t size);
extern int fpga_load(int devnum, const void *buf, size_t bsize,
bitstream_type bstype);
extern int fpga_fsload(int devnum, const void *buf, size_t size,
fpga_fs_info *fpga_fsinfo);
extern int fpga_loadbitstream(int devnum, char *fpgadata, size_t size,
bitstream_type bstype);
extern int fpga_dump(int devnum, const void *buf, size_t bsize);
extern int fpga_info(int devnum);
extern const fpga_desc *const fpga_validate(int devnum, const void *buf,

8
include/xilinx.h
View file

@ -45,16 +45,20 @@ typedef struct { /* typedef xilinx_desc */
} xilinx_desc; /* end, typedef xilinx_desc */
struct xilinx_fpga_op {
int (*load)(xilinx_desc *, const void *, size_t);
int (*load)(xilinx_desc *, const void *, size_t, bitstream_type);
int (*loadfs)(xilinx_desc *, const void *, size_t, fpga_fs_info *);
int (*dump)(xilinx_desc *, const void *, size_t);
int (*info)(xilinx_desc *);
};
/* Generic Xilinx Functions
*********************************************************************/
int xilinx_load(xilinx_desc *desc, const void *image, size_t size);
int xilinx_load(xilinx_desc *desc, const void *image, size_t size,
bitstream_type bstype);
int xilinx_dump(xilinx_desc *desc, const void *buf, size_t bsize);
int xilinx_info(xilinx_desc *desc);
int xilinx_loadfs(xilinx_desc *desc, const void *buf, size_t bsize,
fpga_fs_info *fpga_fsinfo);
/* Board specific implementation specific function types
*********************************************************************/