mirror of
https://github.com/Fishwaldo/u-boot.git
synced 2025-03-18 21:21:37 +00:00
Merge branch 'fpga' of git://www.denx.de/git/u-boot-microblaze
This commit is contained in:
commit
4d16f67e7b
26 changed files with 297 additions and 33 deletions
13
README
13
README
|
@ -2572,6 +2572,19 @@ CBFS (Coreboot Filesystem) support
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Specify the number of FPGA devices to support.
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Specify the number of FPGA devices to support.
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CONFIG_CMD_FPGA_LOADMK
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Enable support for fpga loadmk command
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CONFIG_CMD_FPGA_LOADP
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Enable support for fpga loadp command - load partial bitstream
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CONFIG_CMD_FPGA_LOADBP
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Enable support for fpga loadbp command - load partial bitstream
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(Xilinx only)
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CONFIG_SYS_FPGA_PROG_FEEDBACK
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CONFIG_SYS_FPGA_PROG_FEEDBACK
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Enable printing of hash marks during FPGA configuration.
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Enable printing of hash marks during FPGA configuration.
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@ -77,7 +77,7 @@ int mv_load_fpga(void)
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return -1;
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return -1;
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}
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}
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result = fpga_load(0, fpga_data, data_size);
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result = fpga_load(0, fpga_data, data_size, BIT_FULL);
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if (!result)
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if (!result)
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bootstage_mark(BOOTSTAGE_ID_START);
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bootstage_mark(BOOTSTAGE_ID_START);
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@ -11,6 +11,7 @@
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#include <common.h>
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#include <common.h>
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#include <command.h>
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#include <command.h>
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#include <fpga.h>
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#include <fpga.h>
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#include <fs.h>
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#include <malloc.h>
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#include <malloc.h>
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/* Local functions */
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/* Local functions */
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@ -23,6 +24,9 @@ static int fpga_get_op(char *opstr);
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#define FPGA_LOADB 2
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#define FPGA_LOADB 2
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#define FPGA_DUMP 3
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#define FPGA_DUMP 3
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#define FPGA_LOADMK 4
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#define FPGA_LOADMK 4
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#define FPGA_LOADP 5
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#define FPGA_LOADBP 6
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#define FPGA_LOADFS 7
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/* ------------------------------------------------------------------------- */
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/* ------------------------------------------------------------------------- */
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/* command form:
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/* command form:
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@ -45,6 +49,10 @@ int do_fpga(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
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const char *fit_uname = NULL;
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const char *fit_uname = NULL;
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ulong fit_addr;
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ulong fit_addr;
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#endif
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#endif
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#if defined(CONFIG_CMD_FPGA_LOADFS)
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fpga_fs_info fpga_fsinfo;
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fpga_fsinfo.fstype = FS_TYPE_ANY;
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#endif
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if (devstr)
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if (devstr)
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dev = (int) simple_strtoul(devstr, NULL, 16);
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dev = (int) simple_strtoul(devstr, NULL, 16);
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@ -52,6 +60,14 @@ int do_fpga(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
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fpga_data = (void *)simple_strtoul(datastr, NULL, 16);
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fpga_data = (void *)simple_strtoul(datastr, NULL, 16);
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switch (argc) {
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switch (argc) {
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#if defined(CONFIG_CMD_FPGA_LOADFS)
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case 9:
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fpga_fsinfo.blocksize = (unsigned int)
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simple_strtoul(argv[5], NULL, 16);
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fpga_fsinfo.interface = argv[6];
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fpga_fsinfo.dev_part = argv[7];
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fpga_fsinfo.filename = argv[8];
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#endif
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case 5: /* fpga <op> <dev> <data> <datasize> */
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case 5: /* fpga <op> <dev> <data> <datasize> */
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data_size = simple_strtoul(argv[4], NULL, 16);
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data_size = simple_strtoul(argv[4], NULL, 16);
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@ -120,16 +136,27 @@ int do_fpga(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
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case FPGA_NONE:
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case FPGA_NONE:
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case FPGA_INFO:
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case FPGA_INFO:
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break;
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break;
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#if defined(CONFIG_CMD_FPGA_LOADFS)
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case FPGA_LOADFS:
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/* Blocksize can be zero */
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if (!fpga_fsinfo.interface || !fpga_fsinfo.dev_part ||
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!fpga_fsinfo.filename)
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wrong_parms = 1;
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#endif
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case FPGA_LOAD:
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case FPGA_LOAD:
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case FPGA_LOADP:
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case FPGA_LOADB:
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case FPGA_LOADB:
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case FPGA_LOADBP:
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case FPGA_DUMP:
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case FPGA_DUMP:
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if (!fpga_data || !data_size)
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if (!fpga_data || !data_size)
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wrong_parms = 1;
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wrong_parms = 1;
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break;
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break;
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#if defined(CONFIG_CMD_FPGA_LOADMK)
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case FPGA_LOADMK:
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case FPGA_LOADMK:
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if (!fpga_data)
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if (!fpga_data)
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wrong_parms = 1;
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wrong_parms = 1;
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break;
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break;
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#endif
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}
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}
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if (wrong_parms) {
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if (wrong_parms) {
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@ -146,13 +173,32 @@ int do_fpga(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
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break;
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break;
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case FPGA_LOAD:
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case FPGA_LOAD:
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rc = fpga_load(dev, fpga_data, data_size);
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rc = fpga_load(dev, fpga_data, data_size, BIT_FULL);
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break;
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break;
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#if defined(CONFIG_CMD_FPGA_LOADP)
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case FPGA_LOADP:
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rc = fpga_load(dev, fpga_data, data_size, BIT_PARTIAL);
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break;
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#endif
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case FPGA_LOADB:
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case FPGA_LOADB:
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rc = fpga_loadbitstream(dev, fpga_data, data_size);
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rc = fpga_loadbitstream(dev, fpga_data, data_size, BIT_FULL);
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break;
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break;
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#if defined(CONFIG_CMD_FPGA_LOADBP)
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case FPGA_LOADBP:
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rc = fpga_loadbitstream(dev, fpga_data, data_size, BIT_PARTIAL);
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break;
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#endif
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#if defined(CONFIG_CMD_FPGA_LOADFS)
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case FPGA_LOADFS:
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rc = fpga_fsload(dev, fpga_data, data_size, &fpga_fsinfo);
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break;
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#endif
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#if defined(CONFIG_CMD_FPGA_LOADMK)
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case FPGA_LOADMK:
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case FPGA_LOADMK:
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switch (genimg_get_format(fpga_data)) {
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switch (genimg_get_format(fpga_data)) {
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case IMAGE_FORMAT_LEGACY:
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case IMAGE_FORMAT_LEGACY:
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@ -179,7 +225,8 @@ int do_fpga(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
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data = (ulong)image_get_data(hdr);
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data = (ulong)image_get_data(hdr);
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data_size = image_get_data_size(hdr);
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data_size = image_get_data_size(hdr);
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}
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}
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rc = fpga_load(dev, (void *)data, data_size);
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rc = fpga_load(dev, (void *)data, data_size,
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BIT_FULL);
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}
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}
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break;
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break;
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#if defined(CONFIG_FIT)
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#if defined(CONFIG_FIT)
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@ -221,7 +268,8 @@ int do_fpga(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
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return 1;
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return 1;
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}
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}
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rc = fpga_load(dev, fit_data, data_size);
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rc = fpga_load(dev, fit_data, data_size,
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BIT_FULL);
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}
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}
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break;
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break;
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#endif
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#endif
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@ -231,6 +279,7 @@ int do_fpga(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
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break;
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break;
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}
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}
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break;
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break;
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#endif
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case FPGA_DUMP:
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case FPGA_DUMP:
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rc = fpga_dump(dev, fpga_data, data_size);
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rc = fpga_dump(dev, fpga_data, data_size);
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@ -257,8 +306,22 @@ static int fpga_get_op(char *opstr)
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op = FPGA_LOADB;
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op = FPGA_LOADB;
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else if (!strcmp("load", opstr))
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else if (!strcmp("load", opstr))
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op = FPGA_LOAD;
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op = FPGA_LOAD;
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#if defined(CONFIG_CMD_FPGA_LOADP)
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else if (!strcmp("loadp", opstr))
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op = FPGA_LOADP;
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#endif
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#if defined(CONFIG_CMD_FPGA_LOADBP)
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else if (!strcmp("loadbp", opstr))
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op = FPGA_LOADBP;
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#endif
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#if defined(CONFIG_CMD_FPGA_LOADFS)
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else if (!strcmp("loadfs", opstr))
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op = FPGA_LOADFS;
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#endif
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#if defined(CONFIG_CMD_FPGA_LOADMK)
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else if (!strcmp("loadmk", opstr))
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else if (!strcmp("loadmk", opstr))
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op = FPGA_LOADMK;
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op = FPGA_LOADMK;
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#endif
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else if (!strcmp("dump", opstr))
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else if (!strcmp("dump", opstr))
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op = FPGA_DUMP;
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op = FPGA_DUMP;
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|
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@ -268,19 +331,39 @@ static int fpga_get_op(char *opstr)
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return op;
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return op;
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}
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}
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|
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#if defined(CONFIG_CMD_FPGA_LOADFS)
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U_BOOT_CMD(fpga, 9, 1, do_fpga,
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#else
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U_BOOT_CMD(fpga, 6, 1, do_fpga,
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U_BOOT_CMD(fpga, 6, 1, do_fpga,
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#endif
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"loadable FPGA image support",
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"loadable FPGA image support",
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"[operation type] [device number] [image address] [image size]\n"
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"[operation type] [device number] [image address] [image size]\n"
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"fpga operations:\n"
|
"fpga operations:\n"
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" dump\t[dev]\t\t\tLoad device to memory buffer\n"
|
" dump\t[dev]\t\t\tLoad device to memory buffer\n"
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" info\t[dev]\t\t\tlist known device information\n"
|
" info\t[dev]\t\t\tlist known device information\n"
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||||||
" load\t[dev] [address] [size]\tLoad device from memory buffer\n"
|
" load\t[dev] [address] [size]\tLoad device from memory buffer\n"
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||||||
|
#if defined(CONFIG_CMD_FPGA_LOADP)
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||||||
|
" loadp\t[dev] [address] [size]\t"
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|
"Load device from memory buffer with partial bitstream\n"
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||||||
|
#endif
|
||||||
" loadb\t[dev] [address] [size]\t"
|
" loadb\t[dev] [address] [size]\t"
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||||||
"Load device from bitstream buffer (Xilinx only)\n"
|
"Load device from bitstream buffer (Xilinx only)\n"
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||||||
|
#if defined(CONFIG_CMD_FPGA_LOADBP)
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||||||
|
" loadbp\t[dev] [address] [size]\t"
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|
"Load device from bitstream buffer with partial bitstream"
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|
"(Xilinx only)\n"
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||||||
|
#endif
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||||||
|
#if defined(CONFIG_CMD_FPGA_LOADFS)
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||||||
|
"Load device from filesystem (FAT by default) (Xilinx only)\n"
|
||||||
|
" loadfs [dev] [address] [image size] [blocksize] <interface>\n"
|
||||||
|
" [<dev[:part]>] <filename>\n"
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||||||
|
#endif
|
||||||
|
#if defined(CONFIG_CMD_FPGA_LOADMK)
|
||||||
" loadmk [dev] [address]\tLoad device generated with mkimage"
|
" loadmk [dev] [address]\tLoad device generated with mkimage"
|
||||||
#if defined(CONFIG_FIT)
|
#if defined(CONFIG_FIT)
|
||||||
"\n"
|
"\n"
|
||||||
"\tFor loadmk operating on FIT format uImage address must include\n"
|
"\tFor loadmk operating on FIT format uImage address must include\n"
|
||||||
"\tsubimage unit name in the form of addr:<subimg_uname>"
|
"\tsubimage unit name in the form of addr:<subimg_uname>"
|
||||||
#endif
|
#endif
|
||||||
|
#endif
|
||||||
);
|
);
|
||||||
|
|
|
@ -173,16 +173,45 @@ int fpga_add(fpga_type devtype, void *desc)
|
||||||
/*
|
/*
|
||||||
* Convert bitstream data and load into the fpga
|
* Convert bitstream data and load into the fpga
|
||||||
*/
|
*/
|
||||||
int __weak fpga_loadbitstream(int devnum, char *fpgadata, size_t size)
|
int __weak fpga_loadbitstream(int devnum, char *fpgadata, size_t size,
|
||||||
|
bitstream_type bstype)
|
||||||
{
|
{
|
||||||
printf("Bitstream support not implemented for this FPGA device\n");
|
printf("Bitstream support not implemented for this FPGA device\n");
|
||||||
return FPGA_FAIL;
|
return FPGA_FAIL;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
#if defined(CONFIG_CMD_FPGA_LOADFS)
|
||||||
|
int fpga_fsload(int devnum, const void *buf, size_t size,
|
||||||
|
fpga_fs_info *fpga_fsinfo)
|
||||||
|
{
|
||||||
|
int ret_val = FPGA_FAIL; /* assume failure */
|
||||||
|
const fpga_desc *desc = fpga_validate(devnum, buf, size,
|
||||||
|
(char *)__func__);
|
||||||
|
|
||||||
|
if (desc) {
|
||||||
|
switch (desc->devtype) {
|
||||||
|
case fpga_xilinx:
|
||||||
|
#if defined(CONFIG_FPGA_XILINX)
|
||||||
|
ret_val = xilinx_loadfs(desc->devdesc, buf, size,
|
||||||
|
fpga_fsinfo);
|
||||||
|
#else
|
||||||
|
fpga_no_sup((char *)__func__, "Xilinx devices");
|
||||||
|
#endif
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
printf("%s: Invalid or unsupported device type %d\n",
|
||||||
|
__func__, desc->devtype);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
return ret_val;
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Generic multiplexing code
|
* Generic multiplexing code
|
||||||
*/
|
*/
|
||||||
int fpga_load(int devnum, const void *buf, size_t bsize)
|
int fpga_load(int devnum, const void *buf, size_t bsize, bitstream_type bstype)
|
||||||
{
|
{
|
||||||
int ret_val = FPGA_FAIL; /* assume failure */
|
int ret_val = FPGA_FAIL; /* assume failure */
|
||||||
const fpga_desc *desc = fpga_validate(devnum, buf, bsize,
|
const fpga_desc *desc = fpga_validate(devnum, buf, bsize,
|
||||||
|
@ -192,7 +221,8 @@ int fpga_load(int devnum, const void *buf, size_t bsize)
|
||||||
switch (desc->devtype) {
|
switch (desc->devtype) {
|
||||||
case fpga_xilinx:
|
case fpga_xilinx:
|
||||||
#if defined(CONFIG_FPGA_XILINX)
|
#if defined(CONFIG_FPGA_XILINX)
|
||||||
ret_val = xilinx_load(desc->devdesc, buf, bsize);
|
ret_val = xilinx_load(desc->devdesc, buf, bsize,
|
||||||
|
bstype);
|
||||||
#else
|
#else
|
||||||
fpga_no_sup((char *)__func__, "Xilinx devices");
|
fpga_no_sup((char *)__func__, "Xilinx devices");
|
||||||
#endif
|
#endif
|
||||||
|
|
|
@ -41,7 +41,8 @@ static int spartan2_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize);
|
||||||
|
|
||||||
/* ------------------------------------------------------------------------- */
|
/* ------------------------------------------------------------------------- */
|
||||||
/* Spartan-II Generic Implementation */
|
/* Spartan-II Generic Implementation */
|
||||||
static int spartan2_load(xilinx_desc *desc, const void *buf, size_t bsize)
|
static int spartan2_load(xilinx_desc *desc, const void *buf, size_t bsize,
|
||||||
|
bitstream_type bstype)
|
||||||
{
|
{
|
||||||
int ret_val = FPGA_FAIL;
|
int ret_val = FPGA_FAIL;
|
||||||
|
|
||||||
|
|
|
@ -45,7 +45,8 @@ static int spartan3_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize);
|
||||||
|
|
||||||
/* ------------------------------------------------------------------------- */
|
/* ------------------------------------------------------------------------- */
|
||||||
/* Spartan-II Generic Implementation */
|
/* Spartan-II Generic Implementation */
|
||||||
static int spartan3_load(xilinx_desc *desc, const void *buf, size_t bsize)
|
static int spartan3_load(xilinx_desc *desc, const void *buf, size_t bsize,
|
||||||
|
bitstream_type bstype)
|
||||||
{
|
{
|
||||||
int ret_val = FPGA_FAIL;
|
int ret_val = FPGA_FAIL;
|
||||||
|
|
||||||
|
|
|
@ -90,7 +90,8 @@ static int virtex2_ssm_dump(xilinx_desc *desc, const void *buf, size_t bsize);
|
||||||
static int virtex2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize);
|
static int virtex2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize);
|
||||||
static int virtex2_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize);
|
static int virtex2_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize);
|
||||||
|
|
||||||
static int virtex2_load(xilinx_desc *desc, const void *buf, size_t bsize)
|
static int virtex2_load(xilinx_desc *desc, const void *buf, size_t bsize,
|
||||||
|
bitstream_type bstype)
|
||||||
{
|
{
|
||||||
int ret_val = FPGA_FAIL;
|
int ret_val = FPGA_FAIL;
|
||||||
|
|
||||||
|
|
|
@ -24,7 +24,8 @@ static int xilinx_validate(xilinx_desc *desc, char *fn);
|
||||||
|
|
||||||
/* ------------------------------------------------------------------------- */
|
/* ------------------------------------------------------------------------- */
|
||||||
|
|
||||||
int fpga_loadbitstream(int devnum, char *fpgadata, size_t size)
|
int fpga_loadbitstream(int devnum, char *fpgadata, size_t size,
|
||||||
|
bitstream_type bstype)
|
||||||
{
|
{
|
||||||
unsigned int length;
|
unsigned int length;
|
||||||
unsigned int swapsize;
|
unsigned int swapsize;
|
||||||
|
@ -127,19 +128,36 @@ int fpga_loadbitstream(int devnum, char *fpgadata, size_t size)
|
||||||
dataptr += 4;
|
dataptr += 4;
|
||||||
printf(" bytes in bitstream = %d\n", swapsize);
|
printf(" bytes in bitstream = %d\n", swapsize);
|
||||||
|
|
||||||
return fpga_load(devnum, dataptr, swapsize);
|
return fpga_load(devnum, dataptr, swapsize, bstype);
|
||||||
}
|
}
|
||||||
|
|
||||||
int xilinx_load(xilinx_desc *desc, const void *buf, size_t bsize)
|
int xilinx_load(xilinx_desc *desc, const void *buf, size_t bsize,
|
||||||
|
bitstream_type bstype)
|
||||||
{
|
{
|
||||||
if (!xilinx_validate (desc, (char *)__FUNCTION__)) {
|
if (!xilinx_validate (desc, (char *)__FUNCTION__)) {
|
||||||
printf ("%s: Invalid device descriptor\n", __FUNCTION__);
|
printf ("%s: Invalid device descriptor\n", __FUNCTION__);
|
||||||
return FPGA_FAIL;
|
return FPGA_FAIL;
|
||||||
}
|
}
|
||||||
|
|
||||||
return desc->operations->load(desc, buf, bsize);
|
return desc->operations->load(desc, buf, bsize, bstype);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
#if defined(CONFIG_CMD_FPGA_LOADFS)
|
||||||
|
int xilinx_loadfs(xilinx_desc *desc, const void *buf, size_t bsize,
|
||||||
|
fpga_fs_info *fpga_fsinfo)
|
||||||
|
{
|
||||||
|
if (!xilinx_validate(desc, (char *)__func__)) {
|
||||||
|
printf("%s: Invalid device descriptor\n", __func__);
|
||||||
|
return FPGA_FAIL;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (!desc->operations->loadfs)
|
||||||
|
return FPGA_FAIL;
|
||||||
|
|
||||||
|
return desc->operations->loadfs(desc, buf, bsize, fpga_fsinfo);
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
int xilinx_dump(xilinx_desc *desc, const void *buf, size_t bsize)
|
int xilinx_dump(xilinx_desc *desc, const void *buf, size_t bsize)
|
||||||
{
|
{
|
||||||
if (!xilinx_validate (desc, (char *)__FUNCTION__)) {
|
if (!xilinx_validate (desc, (char *)__FUNCTION__)) {
|
||||||
|
|
|
@ -9,6 +9,7 @@
|
||||||
|
|
||||||
#include <common.h>
|
#include <common.h>
|
||||||
#include <asm/io.h>
|
#include <asm/io.h>
|
||||||
|
#include <fs.h>
|
||||||
#include <zynqpl.h>
|
#include <zynqpl.h>
|
||||||
#include <linux/sizes.h>
|
#include <linux/sizes.h>
|
||||||
#include <asm/arch/hardware.h>
|
#include <asm/arch/hardware.h>
|
||||||
|
@ -194,7 +195,7 @@ static int zynq_dma_transfer(u32 srcbuf, u32 srclen, u32 dstbuf, u32 dstlen)
|
||||||
return FPGA_SUCCESS;
|
return FPGA_SUCCESS;
|
||||||
}
|
}
|
||||||
|
|
||||||
static int zynq_dma_xfer_init(u32 partialbit)
|
static int zynq_dma_xfer_init(bitstream_type bstype)
|
||||||
{
|
{
|
||||||
u32 status, control, isr_status;
|
u32 status, control, isr_status;
|
||||||
unsigned long ts;
|
unsigned long ts;
|
||||||
|
@ -202,7 +203,7 @@ static int zynq_dma_xfer_init(u32 partialbit)
|
||||||
/* Clear loopback bit */
|
/* Clear loopback bit */
|
||||||
clrbits_le32(&devcfg_base->mctrl, DEVCFG_MCTRL_PCAP_LPBK);
|
clrbits_le32(&devcfg_base->mctrl, DEVCFG_MCTRL_PCAP_LPBK);
|
||||||
|
|
||||||
if (!partialbit) {
|
if (bstype != BIT_PARTIAL) {
|
||||||
zynq_slcr_devcfg_disable();
|
zynq_slcr_devcfg_disable();
|
||||||
|
|
||||||
/* Setting PCFG_PROG_B signal to high */
|
/* Setting PCFG_PROG_B signal to high */
|
||||||
|
@ -322,16 +323,11 @@ static u32 *zynq_align_dma_buffer(u32 *buf, u32 len, u32 swap)
|
||||||
|
|
||||||
static int zynq_validate_bitstream(xilinx_desc *desc, const void *buf,
|
static int zynq_validate_bitstream(xilinx_desc *desc, const void *buf,
|
||||||
size_t bsize, u32 blocksize, u32 *swap,
|
size_t bsize, u32 blocksize, u32 *swap,
|
||||||
u32 *partialbit)
|
bitstream_type *bstype)
|
||||||
{
|
{
|
||||||
u32 *buf_start;
|
u32 *buf_start;
|
||||||
u32 diff;
|
u32 diff;
|
||||||
|
|
||||||
/* Detect if we are going working with partial or full bitstream */
|
|
||||||
if (bsize != desc->size) {
|
|
||||||
printf("%s: Working with partial bitstream\n", __func__);
|
|
||||||
*partialbit = 1;
|
|
||||||
}
|
|
||||||
buf_start = check_data((u8 *)buf, blocksize, swap);
|
buf_start = check_data((u8 *)buf, blocksize, swap);
|
||||||
|
|
||||||
if (!buf_start)
|
if (!buf_start)
|
||||||
|
@ -351,17 +347,16 @@ static int zynq_validate_bitstream(xilinx_desc *desc, const void *buf,
|
||||||
return FPGA_FAIL;
|
return FPGA_FAIL;
|
||||||
}
|
}
|
||||||
|
|
||||||
if (zynq_dma_xfer_init(*partialbit))
|
if (zynq_dma_xfer_init(*bstype))
|
||||||
return FPGA_FAIL;
|
return FPGA_FAIL;
|
||||||
|
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
static int zynq_load(xilinx_desc *desc, const void *buf, size_t bsize,
|
||||||
static int zynq_load(xilinx_desc *desc, const void *buf, size_t bsize)
|
bitstream_type bstype)
|
||||||
{
|
{
|
||||||
unsigned long ts; /* Timestamp */
|
unsigned long ts; /* Timestamp */
|
||||||
u32 partialbit = 0;
|
|
||||||
u32 isr_status, swap;
|
u32 isr_status, swap;
|
||||||
|
|
||||||
/*
|
/*
|
||||||
|
@ -369,7 +364,7 @@ static int zynq_load(xilinx_desc *desc, const void *buf, size_t bsize)
|
||||||
* in chunks
|
* in chunks
|
||||||
*/
|
*/
|
||||||
if (zynq_validate_bitstream(desc, buf, bsize, bsize, &swap,
|
if (zynq_validate_bitstream(desc, buf, bsize, bsize, &swap,
|
||||||
&partialbit))
|
&bstype))
|
||||||
return FPGA_FAIL;
|
return FPGA_FAIL;
|
||||||
|
|
||||||
buf = zynq_align_dma_buffer((u32 *)buf, bsize, swap);
|
buf = zynq_align_dma_buffer((u32 *)buf, bsize, swap);
|
||||||
|
@ -398,11 +393,92 @@ static int zynq_load(xilinx_desc *desc, const void *buf, size_t bsize)
|
||||||
|
|
||||||
debug("%s: FPGA config done\n", __func__);
|
debug("%s: FPGA config done\n", __func__);
|
||||||
|
|
||||||
|
if (bstype != BIT_PARTIAL)
|
||||||
|
zynq_slcr_devcfg_enable();
|
||||||
|
|
||||||
|
return FPGA_SUCCESS;
|
||||||
|
}
|
||||||
|
|
||||||
|
#if defined(CONFIG_CMD_FPGA_LOADFS)
|
||||||
|
static int zynq_loadfs(xilinx_desc *desc, const void *buf, size_t bsize,
|
||||||
|
fpga_fs_info *fsinfo)
|
||||||
|
{
|
||||||
|
unsigned long ts; /* Timestamp */
|
||||||
|
u32 isr_status, swap;
|
||||||
|
u32 partialbit = 0;
|
||||||
|
u32 blocksize;
|
||||||
|
u32 pos = 0;
|
||||||
|
int fstype;
|
||||||
|
char *interface, *dev_part, *filename;
|
||||||
|
|
||||||
|
blocksize = fsinfo->blocksize;
|
||||||
|
interface = fsinfo->interface;
|
||||||
|
dev_part = fsinfo->dev_part;
|
||||||
|
filename = fsinfo->filename;
|
||||||
|
fstype = fsinfo->fstype;
|
||||||
|
|
||||||
|
if (fs_set_blk_dev(interface, dev_part, fstype))
|
||||||
|
return FPGA_FAIL;
|
||||||
|
|
||||||
|
if (fs_read(filename, (u32) buf, pos, blocksize) < 0)
|
||||||
|
return FPGA_FAIL;
|
||||||
|
|
||||||
|
if (zynq_validate_bitstream(desc, buf, bsize, blocksize, &swap,
|
||||||
|
&partialbit))
|
||||||
|
return FPGA_FAIL;
|
||||||
|
|
||||||
|
dcache_disable();
|
||||||
|
|
||||||
|
do {
|
||||||
|
buf = zynq_align_dma_buffer((u32 *)buf, blocksize, swap);
|
||||||
|
|
||||||
|
if (zynq_dma_transfer((u32)buf | 1, blocksize >> 2,
|
||||||
|
0xffffffff, 0))
|
||||||
|
return FPGA_FAIL;
|
||||||
|
|
||||||
|
bsize -= blocksize;
|
||||||
|
pos += blocksize;
|
||||||
|
|
||||||
|
if (fs_set_blk_dev(interface, dev_part, fstype))
|
||||||
|
return FPGA_FAIL;
|
||||||
|
|
||||||
|
if (bsize > blocksize) {
|
||||||
|
if (fs_read(filename, (u32) buf, pos, blocksize) < 0)
|
||||||
|
return FPGA_FAIL;
|
||||||
|
} else {
|
||||||
|
if (fs_read(filename, (u32) buf, pos, bsize) < 0)
|
||||||
|
return FPGA_FAIL;
|
||||||
|
}
|
||||||
|
} while (bsize > blocksize);
|
||||||
|
|
||||||
|
buf = zynq_align_dma_buffer((u32 *)buf, blocksize, swap);
|
||||||
|
|
||||||
|
if (zynq_dma_transfer((u32)buf | 1, bsize >> 2, 0xffffffff, 0))
|
||||||
|
return FPGA_FAIL;
|
||||||
|
|
||||||
|
dcache_enable();
|
||||||
|
|
||||||
|
isr_status = readl(&devcfg_base->int_sts);
|
||||||
|
|
||||||
|
/* Check FPGA configuration completion */
|
||||||
|
ts = get_timer(0);
|
||||||
|
while (!(isr_status & DEVCFG_ISR_PCFG_DONE)) {
|
||||||
|
if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) {
|
||||||
|
printf("%s: Timeout wait for FPGA to config\n",
|
||||||
|
__func__);
|
||||||
|
return FPGA_FAIL;
|
||||||
|
}
|
||||||
|
isr_status = readl(&devcfg_base->int_sts);
|
||||||
|
}
|
||||||
|
|
||||||
|
debug("%s: FPGA config done\n", __func__);
|
||||||
|
|
||||||
if (!partialbit)
|
if (!partialbit)
|
||||||
zynq_slcr_devcfg_enable();
|
zynq_slcr_devcfg_enable();
|
||||||
|
|
||||||
return FPGA_SUCCESS;
|
return FPGA_SUCCESS;
|
||||||
}
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
static int zynq_dump(xilinx_desc *desc, const void *buf, size_t bsize)
|
static int zynq_dump(xilinx_desc *desc, const void *buf, size_t bsize)
|
||||||
{
|
{
|
||||||
|
@ -411,6 +487,9 @@ static int zynq_dump(xilinx_desc *desc, const void *buf, size_t bsize)
|
||||||
|
|
||||||
struct xilinx_fpga_op zynq_op = {
|
struct xilinx_fpga_op zynq_op = {
|
||||||
.load = zynq_load,
|
.load = zynq_load,
|
||||||
|
#if defined(CONFIG_CMD_FPGA_LOADFS)
|
||||||
|
.loadfs = zynq_loadfs,
|
||||||
|
#endif
|
||||||
.dump = zynq_dump,
|
.dump = zynq_dump,
|
||||||
.info = zynq_info,
|
.info = zynq_info,
|
||||||
};
|
};
|
||||||
|
|
|
@ -219,6 +219,7 @@
|
||||||
#define CONFIG_CMD_ELF
|
#define CONFIG_CMD_ELF
|
||||||
#define CONFIG_CMD_DATE
|
#define CONFIG_CMD_DATE
|
||||||
#define CONFIG_CMD_FPGA
|
#define CONFIG_CMD_FPGA
|
||||||
|
#define CONFIG_CMD_FPGA_LOADMK
|
||||||
#define CONFIG_CMD_MII
|
#define CONFIG_CMD_MII
|
||||||
#define CONFIG_CMD_BEDBUG
|
#define CONFIG_CMD_BEDBUG
|
||||||
|
|
||||||
|
|
|
@ -89,6 +89,7 @@
|
||||||
#define CONFIG_CMD_SDRAM
|
#define CONFIG_CMD_SDRAM
|
||||||
#define CONFIG_CMD_PCI
|
#define CONFIG_CMD_PCI
|
||||||
#define CONFIG_CMD_FPGA
|
#define CONFIG_CMD_FPGA
|
||||||
|
#define CONFIG_CMD_FPGA_LOADMK
|
||||||
#define CONFIG_CMD_I2C
|
#define CONFIG_CMD_I2C
|
||||||
|
|
||||||
#undef CONFIG_WATCHDOG
|
#undef CONFIG_WATCHDOG
|
||||||
|
|
|
@ -267,6 +267,7 @@
|
||||||
#define CONFIG_CMD_PCI
|
#define CONFIG_CMD_PCI
|
||||||
#define CONFIG_CMD_I2C
|
#define CONFIG_CMD_I2C
|
||||||
#define CONFIG_CMD_FPGA
|
#define CONFIG_CMD_FPGA
|
||||||
|
#define CONFIG_CMD_FPGA_LOADMK
|
||||||
#define CONFIG_CMD_USB
|
#define CONFIG_CMD_USB
|
||||||
#define CONFIG_DOS_PARTITION
|
#define CONFIG_DOS_PARTITION
|
||||||
|
|
||||||
|
|
|
@ -74,6 +74,7 @@
|
||||||
#define CONFIG_CMD_CACHE
|
#define CONFIG_CMD_CACHE
|
||||||
#define CONFIG_CMD_DHCP
|
#define CONFIG_CMD_DHCP
|
||||||
#define CONFIG_CMD_FPGA
|
#define CONFIG_CMD_FPGA
|
||||||
|
#define CONFIG_CMD_FPGA_LOADMK
|
||||||
#define CONFIG_CMD_I2C
|
#define CONFIG_CMD_I2C
|
||||||
#define CONFIG_CMD_MII
|
#define CONFIG_CMD_MII
|
||||||
#define CONFIG_CMD_NET
|
#define CONFIG_CMD_NET
|
||||||
|
|
|
@ -222,6 +222,7 @@
|
||||||
#define CONFIG_CMD_DHCP
|
#define CONFIG_CMD_DHCP
|
||||||
#define CONFIG_CMD_EEPROM
|
#define CONFIG_CMD_EEPROM
|
||||||
#define CONFIG_CMD_FPGA
|
#define CONFIG_CMD_FPGA
|
||||||
|
#define CONFIG_CMD_FPGA_LOADMK
|
||||||
#define CONFIG_CMD_I2C
|
#define CONFIG_CMD_I2C
|
||||||
#undef CONFIG_CMD_LOADB
|
#undef CONFIG_CMD_LOADB
|
||||||
#undef CONFIG_CMD_LOADS
|
#undef CONFIG_CMD_LOADS
|
||||||
|
|
|
@ -88,6 +88,7 @@
|
||||||
#define CONFIG_CMD_LOADS
|
#define CONFIG_CMD_LOADS
|
||||||
#define CONFIG_CMD_LOADB
|
#define CONFIG_CMD_LOADB
|
||||||
#define CONFIG_CMD_FPGA
|
#define CONFIG_CMD_FPGA
|
||||||
|
#define CONFIG_CMD_FPGA_LOADMK
|
||||||
#define CONFIG_CMDLINE_EDITING
|
#define CONFIG_CMDLINE_EDITING
|
||||||
|
|
||||||
#define CONFIG_SYS_HUSH_PARSER
|
#define CONFIG_SYS_HUSH_PARSER
|
||||||
|
|
|
@ -54,6 +54,7 @@
|
||||||
#undef CONFIG_CMD_IMLS
|
#undef CONFIG_CMD_IMLS
|
||||||
#define CONFIG_CMD_USB
|
#define CONFIG_CMD_USB
|
||||||
#define CONFIG_CMD_FPGA
|
#define CONFIG_CMD_FPGA
|
||||||
|
#define CONFIG_CMD_FPGA_LOADMK
|
||||||
#undef CONFIG_LCD
|
#undef CONFIG_LCD
|
||||||
|
|
||||||
/*
|
/*
|
||||||
|
|
|
@ -167,6 +167,7 @@
|
||||||
#define CONFIG_CMD_ECHO
|
#define CONFIG_CMD_ECHO
|
||||||
#undef CONFIG_CMD_FLASH
|
#undef CONFIG_CMD_FLASH
|
||||||
#define CONFIG_CMD_FPGA
|
#define CONFIG_CMD_FPGA
|
||||||
|
#define CONFIG_CMD_FPGA_LOADMK
|
||||||
#define CONFIG_CMD_GPIO
|
#define CONFIG_CMD_GPIO
|
||||||
#define CONFIG_CMD_IMI
|
#define CONFIG_CMD_IMI
|
||||||
#undef CONFIG_CMD_IMLS
|
#undef CONFIG_CMD_IMLS
|
||||||
|
|
|
@ -53,6 +53,7 @@
|
||||||
#define CONFIG_CMD_DIAG
|
#define CONFIG_CMD_DIAG
|
||||||
#define CONFIG_CMD_ECHO /* echo arguments */
|
#define CONFIG_CMD_ECHO /* echo arguments */
|
||||||
#define CONFIG_CMD_FPGA /* FPGA configuration Support */
|
#define CONFIG_CMD_FPGA /* FPGA configuration Support */
|
||||||
|
#define CONFIG_CMD_FPGA_LOADMK
|
||||||
#define CONFIG_CMD_IRQ
|
#define CONFIG_CMD_IRQ
|
||||||
#define CONFIG_CMD_ITEST /* Integer (and string) test */
|
#define CONFIG_CMD_ITEST /* Integer (and string) test */
|
||||||
#define CONFIG_CMD_LOADB /* loadb */
|
#define CONFIG_CMD_LOADB /* loadb */
|
||||||
|
|
|
@ -51,6 +51,7 @@
|
||||||
#define CONFIG_CMD_DIAG
|
#define CONFIG_CMD_DIAG
|
||||||
#define CONFIG_CMD_ECHO /* echo arguments */
|
#define CONFIG_CMD_ECHO /* echo arguments */
|
||||||
#define CONFIG_CMD_FPGA /* FPGA configuration Support */
|
#define CONFIG_CMD_FPGA /* FPGA configuration Support */
|
||||||
|
#define CONFIG_CMD_FPGA_LOADMK
|
||||||
#define CONFIG_CMD_IRQ
|
#define CONFIG_CMD_IRQ
|
||||||
#define CONFIG_CMD_ITEST /* Integer (and string) test */
|
#define CONFIG_CMD_ITEST /* Integer (and string) test */
|
||||||
#define CONFIG_CMD_LOADB /* loadb */
|
#define CONFIG_CMD_LOADB /* loadb */
|
||||||
|
|
|
@ -62,7 +62,8 @@
|
||||||
* Commands additional to the ones defined in amcc-common.h
|
* Commands additional to the ones defined in amcc-common.h
|
||||||
*/
|
*/
|
||||||
#define CONFIG_CMD_CACHE
|
#define CONFIG_CMD_CACHE
|
||||||
#define CONFIG_CMD_FPGAD
|
#define CONFIG_CMD_FPGA
|
||||||
|
#define CONFIG_CMD_FPGA_LOADMK
|
||||||
#undef CONFIG_CMD_EEPROM
|
#undef CONFIG_CMD_EEPROM
|
||||||
|
|
||||||
/*
|
/*
|
||||||
|
|
|
@ -49,6 +49,7 @@
|
||||||
* FPGA
|
* FPGA
|
||||||
*/
|
*/
|
||||||
#define CONFIG_CMD_FPGA
|
#define CONFIG_CMD_FPGA
|
||||||
|
#define CONFIG_CMD_FPGA_LOADMK
|
||||||
#define CONFIG_FPGA
|
#define CONFIG_FPGA
|
||||||
#define CONFIG_FPGA_XILINX
|
#define CONFIG_FPGA_XILINX
|
||||||
#define CONFIG_FPGA_SPARTAN3
|
#define CONFIG_FPGA_SPARTAN3
|
||||||
|
|
|
@ -127,6 +127,7 @@
|
||||||
#define CONFIG_CMD_DHCP
|
#define CONFIG_CMD_DHCP
|
||||||
#define CONFIG_CMD_PING
|
#define CONFIG_CMD_PING
|
||||||
#define CONFIG_CMD_FPGA
|
#define CONFIG_CMD_FPGA
|
||||||
|
#define CONFIG_CMD_FPGA_LOADMK
|
||||||
|
|
||||||
#define CONFIG_SYS_I2C
|
#define CONFIG_SYS_I2C
|
||||||
#define CONFIG_SYS_OMAP24_I2C_SPEED 100000
|
#define CONFIG_SYS_OMAP24_I2C_SPEED 100000
|
||||||
|
|
|
@ -107,6 +107,7 @@
|
||||||
#define CONFIG_CMD_DHCP
|
#define CONFIG_CMD_DHCP
|
||||||
#define CONFIG_CMD_ENV
|
#define CONFIG_CMD_ENV
|
||||||
#define CONFIG_CMD_FPGA
|
#define CONFIG_CMD_FPGA
|
||||||
|
#define CONFIG_CMD_FPGA_LOADMK
|
||||||
#define CONFIG_CMD_GPIO
|
#define CONFIG_CMD_GPIO
|
||||||
#define CONFIG_CMD_I2C
|
#define CONFIG_CMD_I2C
|
||||||
#define CONFIG_CMD_MEMORY
|
#define CONFIG_CMD_MEMORY
|
||||||
|
|
|
@ -191,6 +191,10 @@
|
||||||
#define CONFIG_FPGA_XILINX
|
#define CONFIG_FPGA_XILINX
|
||||||
#define CONFIG_FPGA_ZYNQPL
|
#define CONFIG_FPGA_ZYNQPL
|
||||||
#define CONFIG_CMD_FPGA
|
#define CONFIG_CMD_FPGA
|
||||||
|
#define CONFIG_CMD_FPGA_LOADMK
|
||||||
|
#define CONFIG_CMD_FPGA_LOADP
|
||||||
|
#define CONFIG_CMD_FPGA_LOADBP
|
||||||
|
#define CONFIG_CMD_FPGA_LOADFS
|
||||||
|
|
||||||
/* Open Firmware flat tree */
|
/* Open Firmware flat tree */
|
||||||
#define CONFIG_OF_LIBFDT
|
#define CONFIG_OF_LIBFDT
|
||||||
|
|
|
@ -35,13 +35,29 @@ typedef struct { /* typedef fpga_desc */
|
||||||
void *devdesc; /* real device descriptor */
|
void *devdesc; /* real device descriptor */
|
||||||
} fpga_desc; /* end, typedef fpga_desc */
|
} fpga_desc; /* end, typedef fpga_desc */
|
||||||
|
|
||||||
|
typedef struct { /* typedef fpga_desc */
|
||||||
|
unsigned int blocksize;
|
||||||
|
char *interface;
|
||||||
|
char *dev_part;
|
||||||
|
char *filename;
|
||||||
|
int fstype;
|
||||||
|
} fpga_fs_info;
|
||||||
|
|
||||||
|
typedef enum {
|
||||||
|
BIT_FULL = 0,
|
||||||
|
BIT_PARTIAL,
|
||||||
|
} bitstream_type;
|
||||||
|
|
||||||
/* root function definitions */
|
/* root function definitions */
|
||||||
extern void fpga_init(void);
|
extern void fpga_init(void);
|
||||||
extern int fpga_add(fpga_type devtype, void *desc);
|
extern int fpga_add(fpga_type devtype, void *desc);
|
||||||
extern int fpga_count(void);
|
extern int fpga_count(void);
|
||||||
extern int fpga_load(int devnum, const void *buf, size_t bsize);
|
extern int fpga_load(int devnum, const void *buf, size_t bsize,
|
||||||
extern int fpga_loadbitstream(int devnum, char *fpgadata, size_t size);
|
bitstream_type bstype);
|
||||||
|
extern int fpga_fsload(int devnum, const void *buf, size_t size,
|
||||||
|
fpga_fs_info *fpga_fsinfo);
|
||||||
|
extern int fpga_loadbitstream(int devnum, char *fpgadata, size_t size,
|
||||||
|
bitstream_type bstype);
|
||||||
extern int fpga_dump(int devnum, const void *buf, size_t bsize);
|
extern int fpga_dump(int devnum, const void *buf, size_t bsize);
|
||||||
extern int fpga_info(int devnum);
|
extern int fpga_info(int devnum);
|
||||||
extern const fpga_desc *const fpga_validate(int devnum, const void *buf,
|
extern const fpga_desc *const fpga_validate(int devnum, const void *buf,
|
||||||
|
|
|
@ -45,16 +45,20 @@ typedef struct { /* typedef xilinx_desc */
|
||||||
} xilinx_desc; /* end, typedef xilinx_desc */
|
} xilinx_desc; /* end, typedef xilinx_desc */
|
||||||
|
|
||||||
struct xilinx_fpga_op {
|
struct xilinx_fpga_op {
|
||||||
int (*load)(xilinx_desc *, const void *, size_t);
|
int (*load)(xilinx_desc *, const void *, size_t, bitstream_type);
|
||||||
|
int (*loadfs)(xilinx_desc *, const void *, size_t, fpga_fs_info *);
|
||||||
int (*dump)(xilinx_desc *, const void *, size_t);
|
int (*dump)(xilinx_desc *, const void *, size_t);
|
||||||
int (*info)(xilinx_desc *);
|
int (*info)(xilinx_desc *);
|
||||||
};
|
};
|
||||||
|
|
||||||
/* Generic Xilinx Functions
|
/* Generic Xilinx Functions
|
||||||
*********************************************************************/
|
*********************************************************************/
|
||||||
int xilinx_load(xilinx_desc *desc, const void *image, size_t size);
|
int xilinx_load(xilinx_desc *desc, const void *image, size_t size,
|
||||||
|
bitstream_type bstype);
|
||||||
int xilinx_dump(xilinx_desc *desc, const void *buf, size_t bsize);
|
int xilinx_dump(xilinx_desc *desc, const void *buf, size_t bsize);
|
||||||
int xilinx_info(xilinx_desc *desc);
|
int xilinx_info(xilinx_desc *desc);
|
||||||
|
int xilinx_loadfs(xilinx_desc *desc, const void *buf, size_t bsize,
|
||||||
|
fpga_fs_info *fpga_fsinfo);
|
||||||
|
|
||||||
/* Board specific implementation specific function types
|
/* Board specific implementation specific function types
|
||||||
*********************************************************************/
|
*********************************************************************/
|
||||||
|
|
Loading…
Add table
Reference in a new issue