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powerpc/85xx: Add support for RMan LIODN initialization

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This patch is intended to initialize RMan LIODN related registers on
P2041, P304S and P5020 SocS. It also adds the "rman@0" child node to
qman-portal nodes, adds "fsl,liodn" property to RMan inbound block nodes.

Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Kumar Gala 2011-10-14 13:28:52 -05:00
parent 9c42ef6145
commit 4d28db8a1e
11 changed files with 115 additions and 0 deletions
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39
arch/powerpc/cpu/mpc85xx/liodn.c
View file

@ -148,6 +148,34 @@ static void setup_raide_liodn_base(void)
}
#endif
#ifdef CONFIG_SYS_DPAA_RMAN
static void set_rman_liodn(struct liodn_id_table *tbl, int size)
{
int i;
struct ccsr_rman *rman = (void *)CONFIG_SYS_FSL_CORENET_RMAN_ADDR;
for (i = 0; i < size; i++) {
/* write the RMan block number */
out_be32(&rman->mmitar, i);
/* write the liodn offset corresponding to the block */
out_be32((u32 *)(tbl[i].reg_offset), tbl[i].id[0]);
}
}
static void setup_rman_liodn_base(struct liodn_id_table *tbl, int size)
{
int i;
struct ccsr_rman *rman = (void *)CONFIG_SYS_FSL_CORENET_RMAN_ADDR;
u32 base = liodn_bases[FSL_HW_PORTAL_RMAN].id[0];
out_be32(&rman->mmliodnbr, base);
/* update liodn offset */
for (i = 0; i < size; i++)
tbl[i].id[0] += base;
}
#endif
void set_liodns(void)
{
/* setup general liodn offsets */
@ -182,6 +210,13 @@ void set_liodns(void)
set_liodn(raide_liodn_tbl, raide_liodn_tbl_sz);
setup_raide_liodn_base();
#endif
#ifdef CONFIG_SYS_DPAA_RMAN
/* setup RMan liodn offsets */
set_rman_liodn(rman_liodn_tbl, rman_liodn_tbl_sz);
/* setup RMan liodn base */
setup_rman_liodn_base(rman_liodn_tbl, rman_liodn_tbl_sz);
#endif
}
static void fdt_fixup_srio_liodn(void *blob, struct srio_liodn_id_table *tbl)
@ -256,4 +291,8 @@ void fdt_fixup_liodn(void *blob)
#ifdef CONFIG_SYS_FSL_RAID_ENGINE
fdt_fixup_liodn_tbl(blob, raide_liodn_tbl, raide_liodn_tbl_sz);
#endif
#ifdef CONFIG_SYS_DPAA_RMAN
fdt_fixup_liodn_tbl(blob, rman_liodn_tbl, rman_liodn_tbl_sz);
#endif
}

14
arch/powerpc/cpu/mpc85xx/p2041_ids.c
View file

@ -104,6 +104,17 @@ struct liodn_id_table sec_liodn_tbl[] = {
};
int sec_liodn_tbl_sz = ARRAY_SIZE(sec_liodn_tbl);
#ifdef CONFIG_SYS_DPAA_RMAN
struct liodn_id_table rman_liodn_tbl[] = {
/* Set RMan block 0-3 liodn offset */
SET_RMAN_LIODN(0, 6),
SET_RMAN_LIODN(1, 7),
SET_RMAN_LIODN(2, 8),
SET_RMAN_LIODN(3, 9),
};
int rman_liodn_tbl_sz = ARRAY_SIZE(rman_liodn_tbl);
#endif
struct liodn_id_table liodn_bases[] = {
[FSL_HW_PORTAL_SEC] = SET_LIODN_BASE_2(64, 100),
#ifdef CONFIG_SYS_DPAA_FMAN
@ -112,4 +123,7 @@ struct liodn_id_table liodn_bases[] = {
#ifdef CONFIG_SYS_DPAA_PME
[FSL_HW_PORTAL_PME] = SET_LIODN_BASE_2(136, 172),
#endif
#ifdef CONFIG_SYS_DPAA_RMAN
[FSL_HW_PORTAL_RMAN] = SET_LIODN_BASE_1(80),
#endif
};

14
arch/powerpc/cpu/mpc85xx/p3041_ids.c
View file

@ -103,6 +103,17 @@ struct liodn_id_table sec_liodn_tbl[] = {
};
int sec_liodn_tbl_sz = ARRAY_SIZE(sec_liodn_tbl);
#ifdef CONFIG_SYS_DPAA_RMAN
struct liodn_id_table rman_liodn_tbl[] = {
/* Set RMan block 0-3 liodn offset */
SET_RMAN_LIODN(0, 6),
SET_RMAN_LIODN(1, 7),
SET_RMAN_LIODN(2, 8),
SET_RMAN_LIODN(3, 9),
};
int rman_liodn_tbl_sz = ARRAY_SIZE(rman_liodn_tbl);
#endif
struct liodn_id_table liodn_bases[] = {
[FSL_HW_PORTAL_SEC] = SET_LIODN_BASE_2(64, 100),
#ifdef CONFIG_SYS_DPAA_FMAN
@ -111,4 +122,7 @@ struct liodn_id_table liodn_bases[] = {
#ifdef CONFIG_SYS_DPAA_PME
[FSL_HW_PORTAL_PME] = SET_LIODN_BASE_2(136, 172),
#endif
#ifdef CONFIG_SYS_DPAA_RMAN
[FSL_HW_PORTAL_RMAN] = SET_LIODN_BASE_1(80),
#endif
};

14
arch/powerpc/cpu/mpc85xx/p5020_ids.c
View file

@ -113,6 +113,17 @@ struct liodn_id_table raide_liodn_tbl[] = {
int raide_liodn_tbl_sz = ARRAY_SIZE(raide_liodn_tbl);
#endif
#ifdef CONFIG_SYS_DPAA_RMAN
struct liodn_id_table rman_liodn_tbl[] = {
/* Set RMan block 0-3 liodn offset */
SET_RMAN_LIODN(0, 6),
SET_RMAN_LIODN(1, 7),
SET_RMAN_LIODN(2, 8),
SET_RMAN_LIODN(3, 9),
};
int rman_liodn_tbl_sz = ARRAY_SIZE(rman_liodn_tbl);
#endif
struct liodn_id_table liodn_bases[] = {
[FSL_HW_PORTAL_SEC] = SET_LIODN_BASE_2(64, 100),
#ifdef CONFIG_SYS_DPAA_FMAN
@ -124,4 +135,7 @@ struct liodn_id_table liodn_bases[] = {
#ifdef CONFIG_SYS_FSL_RAID_ENGINE
[FSL_HW_PORTAL_RAID_ENGINE] = SET_LIODN_BASE_1(47),
#endif
#ifdef CONFIG_SYS_DPAA_RMAN
[FSL_HW_PORTAL_RMAN] = SET_LIODN_BASE_1(80),
#endif
};

6
arch/powerpc/cpu/mpc85xx/portals.c
View file

@ -245,6 +245,12 @@ void fdt_fixup_qportals(void *blob)
goto err;
}
#endif
#ifdef CONFIG_SYS_DPAA_RMAN
err = fdt_qportal(blob, off, i, "rman@0",
FSL_HW_PORTAL_RMAN, 1);
if (err < 0)
goto err;
#endif
err:
if (err < 0) {

8
arch/powerpc/include/asm/fsl_liodn.h
View file

@ -175,12 +175,20 @@ extern void fdt_fixup_liodn(void *blob);
offsetof(struct ccsr_raide, jq[jqNum].ring[rNum].cfg0) + \
CONFIG_SYS_FSL_RAID_ENGINE_OFFSET)
#define SET_RMAN_LIODN(ibNum, liodn) \
SET_LIODN_ENTRY_1("fsl,rman-inbound-block", liodn, \
offsetof(struct ccsr_rman, mmitdr) + \
CONFIG_SYS_FSL_CORENET_RMAN_OFFSET, \
CONFIG_SYS_FSL_CORENET_RMAN_OFFSET + ibNum * 0x1000)
extern struct liodn_id_table liodn_tbl[], liodn_bases[], sec_liodn_tbl[];
extern struct liodn_id_table raide_liodn_tbl[];
extern struct liodn_id_table fman1_liodn_tbl[], fman2_liodn_tbl[];
extern struct srio_liodn_id_table srio_liodn_tbl[];
extern struct liodn_id_table rman_liodn_tbl[];
extern int liodn_tbl_sz, sec_liodn_tbl_sz, raide_liodn_tbl_sz;
extern int fman1_liodn_tbl_sz, fman2_liodn_tbl_sz;
extern int srio_liodn_tbl_sz;
extern int rman_liodn_tbl_sz;
#endif

4
arch/powerpc/include/asm/fsl_portals.h
View file

@ -38,6 +38,10 @@ enum fsl_dpaa_dev {
#ifdef CONFIG_SYS_FSL_RAID_ENGINE
FSL_HW_PORTAL_RAID_ENGINE,
#endif
#ifdef CONFIG_SYS_DPAA_RMAN
FSL_HW_PORTAL_RMAN,
#endif
};
struct qportal_info {

13
arch/powerpc/include/asm/immap_85xx.h
View file

@ -2339,6 +2339,16 @@ struct ccsr_raide {
};
#endif
#ifdef CONFIG_SYS_DPAA_RMAN
struct ccsr_rman {
u8 res0[0xf64];
u32 mmliodnbr; /* Message Manager LIODN Base Register */
u32 mmitar; /* RMAN Inbound Translation Address Register */
u32 mmitdr; /* RMAN Inbound Translation Data Register */
u8 res4[0x1f090];
};
#endif
#ifdef CONFIG_FSL_CORENET
#define CONFIG_SYS_FSL_CORENET_CCM_OFFSET 0x0000
#define CONFIG_SYS_MPC85xx_DDR_OFFSET 0x8000
@ -2354,6 +2364,7 @@ struct ccsr_raide {
#define CONFIG_SYS_MPC85xx_ESDHC_OFFSET 0x114000
#define CONFIG_SYS_MPC85xx_LBC_OFFSET 0x124000
#define CONFIG_SYS_MPC85xx_GPIO_OFFSET 0x130000
#define CONFIG_SYS_FSL_CORENET_RMAN_OFFSET 0x1e0000
#define CONFIG_SYS_MPC85xx_PCIE1_OFFSET 0x200000
#define CONFIG_SYS_MPC85xx_PCIE2_OFFSET 0x201000
#define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0x202000
@ -2442,6 +2453,8 @@ struct ccsr_raide {
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_PME_OFFSET)
#define CONFIG_SYS_FSL_RAID_ENGINE_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_RAID_ENGINE_OFFSET)
#define CONFIG_SYS_FSL_CORENET_RMAN_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_RMAN_OFFSET)
#define CONFIG_SYS_MPC85xx_GUTS_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_GUTS_OFFSET)
#define CONFIG_SYS_FSL_CORENET_CCM_ADDR \

1
include/configs/P2041RDB.h
View file

@ -66,6 +66,7 @@
#define CONFIG_SYS_SRIO
#define CONFIG_SRIO1 /* SRIO port 1 */
#define CONFIG_SRIO2 /* SRIO port 2 */
#define CONFIG_SYS_DPAA_RMAN /* RMan */
#define CONFIG_FSL_LAW /* Use common FSL init code */

1
include/configs/P3041DS.h
View file

@ -35,6 +35,7 @@
#define CONFIG_FSL_SATA_V2
#define CONFIG_PCIE3
#define CONFIG_PCIE4
#define CONFIG_SYS_DPAA_RMAN
#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */

1
include/configs/P5020DS.h
View file

@ -36,6 +36,7 @@
#define CONFIG_PCIE3
#define CONFIG_PCIE4
#define CONFIG_SYS_FSL_RAID_ENGINE
#define CONFIG_SYS_DPAA_RMAN
#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */