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Merge branch 'master' of git://www.denx.de/git/u-boot-imx

Browse source
This commit is contained in:
Tom Rini 2015-06-08 08:37:02 -04:00
commit 4d80051b63
38 changed files with 794 additions and 114 deletions
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10
arch/arm/cpu/arm926ejs/mxs/spl_power_init.c
View file

@ -332,6 +332,11 @@ static void mxs_enable_4p2_dcdc_input(int xfer)
debug("SPL: %s 4P2 DC-DC Input\n", xfer ? "Enabling" : "Disabling");
if (xfer && (readl(&power_regs->hw_power_5vctrl) &
POWER_5VCTRL_ENABLE_DCDC)) {
return;
}
prev_5v_brnout = readl(&power_regs->hw_power_5vctrl) &
POWER_5VCTRL_PWDN_5VBRNOUT;
prev_5v_droop = readl(&power_regs->hw_power_ctrl) &
@ -343,11 +348,6 @@ static void mxs_enable_4p2_dcdc_input(int xfer)
clrbits_le32(&power_regs->hw_power_ctrl, POWER_CTRL_ENIRQ_VDD5V_DROOP);
if (xfer && (readl(&power_regs->hw_power_5vctrl) &
POWER_5VCTRL_ENABLE_DCDC)) {
return;
}
/*
* Recording orignal values that will be modified temporarlily
* to handle a chip bug. See chip errata for CQ ENGR00115837

7
arch/arm/cpu/armv7/vf610/generic.c
View file

@ -198,6 +198,11 @@ static u32 get_i2c_clk(void)
return get_ipg_clk();
}
static u32 get_dspi_clk(void)
{
return get_ipg_clk();
}
unsigned int mxc_get_clock(enum mxc_clock clk)
{
switch (clk) {
@ -215,6 +220,8 @@ unsigned int mxc_get_clock(enum mxc_clock clk)
return get_fec_clk();
case MXC_I2C_CLK:
return get_i2c_clk();
case MXC_DSPI_CLK:
return get_dspi_clk();
default:
break;
}

3
arch/arm/dts/Makefile
View file

@ -133,6 +133,9 @@ dtb-$(CONFIG_MACH_SUN9I) += \
sun9i-a80-optimus.dtb \
sun9i-a80-cubieboard4.dtb
dtb-$(CONFIG_VF610) += vf500-colibri.dtb \
vf610-colibri.dtb
targets += $(dtb-y)
DTC_FLAGS += -R 4 -p 0x1000

21
arch/arm/dts/vf-colibri.dtsi Normal file
View file

@ -0,0 +1,21 @@
/*
* Copyright 2014 Toradex AG
*
* SPDX-License-Identifier: GPL-2.0+ or X11
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#include "vf.dtsi"
&dspi1 {
status = "okay";
bus-num = <1>;
spi_cmd: sspi@0 {
reg = <0>;
spi-max-frequency = <50000000>;
};
};

100
arch/arm/dts/vf.dtsi Normal file
View file

@ -0,0 +1,100 @@
/*
* Copyright 2013 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+ or X11
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
/include/ "skeleton.dtsi"
/ {
aliases {
gpio0 = &gpio0;
gpio1 = &gpio1;
gpio2 = &gpio2;
gpio3 = &gpio3;
gpio4 = &gpio4;
spi0 = &dspi0;
spi1 = &dspi1;
};
soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
ranges;
aips0: aips-bus@40000000 {
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
dspi0: dspi0@4002c000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,vf610-dspi";
reg = <0x4002c000 0x1000>;
num-cs = <5>;
status = "disabled";
};
dspi1: dspi1@4002d000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,vf610-dspi";
reg = <0x4002d000 0x1000>;
num-cs = <5>;
status = "disabled";
};
qspi0: quadspi@40044000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,vf610-qspi";
reg = <0x40044000 0x1000>;
status = "disabled";
};
gpio0: gpio@40049000 {
compatible = "fsl,vf610-gpio";
reg = <0x400ff000 0x40>;
#gpio-cells = <2>;
};
gpio1: gpio@4004a000 {
compatible = "fsl,vf610-gpio";
reg = <0x400ff040 0x40>;
#gpio-cells = <2>;
};
gpio2: gpio@4004b000 {
compatible = "fsl,vf610-gpio";
reg = <0x400ff080 0x40>;
#gpio-cells = <2>;
};
gpio3: gpio@4004c000 {
compatible = "fsl,vf610-gpio";
reg = <0x400ff0c0 0x40>;
#gpio-cells = <2>;
};
gpio4: gpio@4004d000 {
compatible = "fsl,vf610-gpio";
reg = <0x400ff100 0x40>;
#gpio-cells = <2>;
};
};
aips1: aips-bus@40080000 {
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
};
};
};

18
arch/arm/dts/vf500-colibri.dts Normal file
View file

@ -0,0 +1,18 @@
/*
* Copyright 2014 Toradex AG
*
* SPDX-License-Identifier: GPL-2.0+ or X11
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
/dts-v1/;
#include "vf-colibri.dtsi"
/ {
model = "Toradex Colibri VF50";
compatible = "toradex,vf500-colibri_vf50", "toradex,vf500-colibri_vf50", "fsl,vf500";
};

18
arch/arm/dts/vf610-colibri.dts Normal file
View file

@ -0,0 +1,18 @@
/*
* Copyright 2014 Toradex AG
*
* SPDX-License-Identifier: GPL-2.0+ or X11
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
/dts-v1/;
#include "vf-colibri.dtsi"
/ {
model = "Toradex Colibri VF61";
compatible = "toradex,vf610-colibri_vf61", "toradex,vf610-colibri_vf61", "fsl,vf610";
};

3
arch/arm/imx-common/cpu.c
View file

@ -145,7 +145,8 @@ const char *get_imx_type(u32 imxtype)
int print_cpuinfo(void)
{
u32 cpurev, max_freq;
u32 cpurev;
__maybe_unused u32 max_freq;
#if defined(CONFIG_MX6) && defined(CONFIG_IMX6_THERMAL)
struct udevice *thermal_dev;

26
arch/arm/imx-common/iomux-v3.c
View file

@ -92,3 +92,29 @@ void imx_iomux_set_gpr_register(int group, int start_bit,
reg |= (value << start_bit);
writel(reg, base + group * 4);
}
#ifdef CONFIG_IOMUX_SHARE_CONF_REG
void imx_iomux_gpio_set_direction(unsigned int gpio,
unsigned int direction)
{
u32 reg;
/*
* Only on Vybrid the input/output buffer enable flags
* are part of the shared mux/conf register.
*/
reg = readl(base + (gpio << 2));
if (direction)
reg |= 0x2;
else
reg &= ~0x2;
writel(reg, base + (gpio << 2));
}
void imx_iomux_gpio_get_function(unsigned int gpio, u32 *gpio_state)
{
*gpio_state = readl(base + (gpio << 2)) &
((0X07 << PAD_MUX_MODE_SHIFT) | PAD_CTL_OBE_IBE_ENABLE);
}
#endif

1
arch/arm/include/asm/arch-vf610/clock.h
View file

@ -17,6 +17,7 @@ enum mxc_clock {
MXC_ESDHC_CLK,
MXC_FEC_CLK,
MXC_I2C_CLK,
MXC_DSPI_CLK,
};
void enable_ocotp_clk(unsigned char enable);

4
arch/arm/include/asm/arch-vf610/crm_regs.h
View file

@ -189,6 +189,8 @@ struct anadig_reg {
#define CCM_REG_CTRL_MASK 0xffffffff
#define CCM_CCGR0_UART0_CTRL_MASK (0x3 << 14)
#define CCM_CCGR0_UART1_CTRL_MASK (0x3 << 16)
#define CCM_CCGR0_DSPI0_CTRL_MASK (0x3 << 24)
#define CCM_CCGR0_DSPI1_CTRL_MASK (0x3 << 26)
#define CCM_CCGR1_USBC0_CTRL_MASK (0x3 << 8)
#define CCM_CCGR1_PIT_CTRL_MASK (0x3 << 14)
#define CCM_CCGR1_WDOGA5_CTRL_MASK (0x3 << 28)
@ -206,6 +208,8 @@ struct anadig_reg {
#define CCM_CCGR4_GPC_CTRL_MASK (0x3 << 24)
#define CCM_CCGR4_I2C0_CTRL_MASK (0x3 << 12)
#define CCM_CCGR6_OCOTP_CTRL_MASK (0x3 << 10)
#define CCM_CCGR6_DSPI2_CTRL_MASK (0x3 << 24)
#define CCM_CCGR6_DSPI3_CTRL_MASK (0x3 << 26)
#define CCM_CCGR6_DDRMC_CTRL_MASK (0x3 << 28)
#define CCM_CCGR7_SDHC1_CTRL_MASK (0x3 << 4)
#define CCM_CCGR7_USBC1_CTRL_MASK (0x3 << 8)

29
arch/arm/include/asm/arch-vf610/gpio.h Normal file
View file

@ -0,0 +1,29 @@
/*
* Copyright (C) 2015
* Bhuvanchandra DV, Toradex, Inc.
*
* SPDX-License-Identifier: GPL-2.0
*/
#ifndef __ASM_ARCH_VF610_GPIO_H
#define __ASM_ARCH_VF610_GPIO_H
#define VYBRID_GPIO_COUNT 32
#define VF610_GPIO_DIRECTION_IN 0x0
#define VF610_GPIO_DIRECTION_OUT 0x1
/* GPIO registers */
struct vybrid_gpio_regs {
u32 gpio_pdor;
u32 gpio_psor;
u32 gpio_pcor;
u32 gpio_ptor;
u32 gpio_pdir;
};
struct vybrid_gpio_platdata {
unsigned int chip;
u32 base;
const char *port_name;
};
#endif /* __ASM_ARCH_VF610_GPIO_H */

5
arch/arm/include/asm/arch-vf610/imx-regs.h
View file

@ -81,6 +81,11 @@
#define VREG_DIG_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006D000)
#define SRC_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006E000)
#define CMU_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006F000)
#define GPIO0_BASE_ADDR (AIPS0_BASE_ADDR + 0x000FF000)
#define GPIO1_BASE_ADDR (AIPS0_BASE_ADDR + 0x000FF040)
#define GPIO2_BASE_ADDR (AIPS0_BASE_ADDR + 0x000FF080)
#define GPIO3_BASE_ADDR (AIPS0_BASE_ADDR + 0x000FF0C0)
#define GPIO4_BASE_ADDR (AIPS0_BASE_ADDR + 0x000FF100)
/* AIPS 1 */
#define OCOTP_BASE_ADDR (AIPS1_BASE_ADDR + 0x00025000)

59
arch/arm/include/asm/arch-vf610/iomux-vf610.h
View file

@ -32,22 +32,61 @@
#define VF610_QSPI_PAD_CTRL (PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_150ohm | \
PAD_CTL_PUS_22K_UP | PAD_CTL_OBE_IBE_ENABLE)
#define VF610_GPIO_PAD_CTRL (PAD_CTL_SPEED_MED | PAD_CTL_DSE_50ohm | \
PAD_CTL_PUS_47K_UP | PAD_CTL_IBE_ENABLE)
#define VF610_DSPI_PAD_CTRL (PAD_CTL_OBE_ENABLE | PAD_CTL_DSE_20ohm | \
PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_HIGH)
#define VF610_DSPI_SIN_PAD_CTRL (PAD_CTL_IBE_ENABLE | PAD_CTL_DSE_20ohm | \
PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_HIGH)
enum {
VF610_PAD_PTA6__RMII0_CLKIN = IOMUX_PAD(0x0000, 0x0000, 2, __NA_, 0, VF610_ENET_PAD_CTRL),
VF610_PAD_PTA6__RMII0_CLKOUT = IOMUX_PAD(0x0000, 0x0000, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
VF610_PAD_PTA7__GPIO_134 = IOMUX_PAD(0x0218, 0x0218, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
VF610_PAD_PTA17__GPIO_7 = IOMUX_PAD(0x001c, 0x001c, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
VF610_PAD_PTA20__GPIO_10 = IOMUX_PAD(0x0028, 0x0028, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
VF610_PAD_PTA21__GPIO_11 = IOMUX_PAD(0x002c, 0x002c, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
VF610_PAD_PTA30__GPIO_20 = IOMUX_PAD(0x0050, 0x0050, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
VF610_PAD_PTA31__GPIO_21 = IOMUX_PAD(0x0054, 0x0054, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
VF610_PAD_PTB0__GPIO_22 = IOMUX_PAD(0x0058, 0x0058, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
VF610_PAD_PTB1__GPIO_23 = IOMUX_PAD(0x005C, 0x005C, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
VF610_PAD_PTB4__UART1_TX = IOMUX_PAD(0x0068, 0x0068, 2, 0x0380, 0, VF610_UART_PAD_CTRL),
VF610_PAD_PTB5__UART1_RX = IOMUX_PAD(0x006c, 0x006c, 2, 0x037c, 0, VF610_UART_PAD_CTRL),
VF610_PAD_PTB6__GPIO_28 = IOMUX_PAD(0x0070, 0x0070, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
VF610_PAD_PTB7__GPIO_29 = IOMUX_PAD(0x0074, 0x0074, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
VF610_PAD_PTB8__GPIO_30 = IOMUX_PAD(0x0078, 0x0078, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
VF610_PAD_PTB9__GPIO_31 = IOMUX_PAD(0x007C, 0x007C, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
VF610_PAD_PTB10__UART0_TX = IOMUX_PAD(0x0080, 0x0080, 1, __NA_, 0, VF610_UART_PAD_CTRL),
VF610_PAD_PTB11__UART0_RX = IOMUX_PAD(0x0084, 0x0084, 1, __NA_, 0, VF610_UART_PAD_CTRL),
VF610_PAD_PTB12__GPIO_34 = IOMUX_PAD(0x0088, 0x0088, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
VF610_PAD_PTB13__GPIO_35 = IOMUX_PAD(0x008c, 0x008c, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
VF610_PAD_PTB16__GPIO_38 = IOMUX_PAD(0x0098, 0x0098, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
VF610_PAD_PTB17__GPIO_39 = IOMUX_PAD(0x009c, 0x009c, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
VF610_PAD_PTB18__GPIO_40 = IOMUX_PAD(0x00a0, 0x00a0, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
VF610_PAD_PTB21__GPIO_43 = IOMUX_PAD(0x00ac, 0x00ac, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
VF610_PAD_PTB22__GPIO_44 = IOMUX_PAD(0x00b0, 0x00b0, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
VF610_PAD_PTB23__GPIO_93 = IOMUX_PAD(0x0174, 0x0174, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
VF610_PAD_PTB26__GPIO_96 = IOMUX_PAD(0x0180, 0x0180, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
VF610_PAD_PTB28__GPIO_98 = IOMUX_PAD(0x0188, 0x0188, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
VF610_PAD_PTC1__GPIO_46 = IOMUX_PAD(0x00b8, 0x00b8, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
VF610_PAD_PTC1__RMII0_MDIO = IOMUX_PAD(0x00b8, 0x00b8, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
VF610_PAD_PTC0__GPIO_45 = IOMUX_PAD(0x00b4, 0x00b4, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
VF610_PAD_PTC0__RMII0_MDC = IOMUX_PAD(0x00b4, 0x00b4, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
VF610_PAD_PTC2__RMII0_CRS_DV = IOMUX_PAD(0x00bc, 0x00bc, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
VF610_PAD_PTC2__GPIO_47 = IOMUX_PAD(0x00bc, 0x00bc, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
VF610_PAD_PTC3__RMII0_RD1 = IOMUX_PAD(0x00c0, 0x00c0, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
VF610_PAD_PTC3__GPIO_48 = IOMUX_PAD(0x00c0, 0x00c0, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
VF610_PAD_PTC4__RMII0_RD0 = IOMUX_PAD(0x00c4, 0x00c4, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
VF610_PAD_PTC4__GPIO_49 = IOMUX_PAD(0x00c4, 0x00c4, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
VF610_PAD_PTC5__RMII0_RXER = IOMUX_PAD(0x00c8, 0x00c8, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
VF610_PAD_PTC5__GPIO_50 = IOMUX_PAD(0x00c8, 0x00c8, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
VF610_PAD_PTC6__RMII0_TD1 = IOMUX_PAD(0x00cc, 0x00cc, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
VF610_PAD_PTC6__GPIO_51 = IOMUX_PAD(0x00cc, 0x00cc, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
VF610_PAD_PTC7__RMII0_TD0 = IOMUX_PAD(0x00D0, 0x00D0, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
VF610_PAD_PTC7__GPIO_52 = IOMUX_PAD(0x00D0, 0x00D0, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
VF610_PAD_PTC8__RMII0_TXEN = IOMUX_PAD(0x00D4, 0x00D4, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
VF610_PAD_PTC8__GPIO_53 = IOMUX_PAD(0x00D4, 0x00D4, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
VF610_PAD_PTC10__RMII1_MDIO = IOMUX_PAD(0x00dc, 0x00dc, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
VF610_PAD_PTC9__RMII1_MDC = IOMUX_PAD(0x00d8, 0x00d8, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
VF610_PAD_PTC11__RMII1_CRS_DV = IOMUX_PAD(0x00e0, 0x00e0, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
@ -57,6 +96,12 @@ enum {
VF610_PAD_PTC15__RMII1_TD1 = IOMUX_PAD(0x00f0, 0x00f0, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
VF610_PAD_PTC16__RMII1_TD0 = IOMUX_PAD(0x00f4, 0x00f4, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
VF610_PAD_PTC17__RMII1_TXEN = IOMUX_PAD(0x00f8, 0x00f8, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
VF610_PAD_PTD5__DSPI1_CS0 = IOMUX_PAD(0x0150, 0x0150, 3, 0x300, 1, VF610_DSPI_PAD_CTRL),
VF610_PAD_PTD6__DSPI1_SIN = IOMUX_PAD(0x0154, 0x0154, 3, 0x2fc, 1, VF610_DSPI_SIN_PAD_CTRL),
VF610_PAD_PTD7__DSPI1_SOUT = IOMUX_PAD(0x0158, 0x0158, 3, __NA_, 0, VF610_DSPI_PAD_CTRL),
VF610_PAD_PTD8__DSPI1_SCK = IOMUX_PAD(0x015c, 0x015c, 3, 0x2f8, 1, VF610_DSPI_PAD_CTRL),
VF610_PAD_PTC29__GPIO_102 = IOMUX_PAD(0x0198, 0x0198, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
VF610_PAD_PTC30__GPIO_103 = IOMUX_PAD(0x019c, 0x019c, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
VF610_PAD_PTA24__ESDHC1_CLK = IOMUX_PAD(0x0038, 0x0038, 5, __NA_, 0, VF610_SDHC_PAD_CTRL),
VF610_PAD_PTA25__ESDHC1_CMD = IOMUX_PAD(0x003c, 0x003c, 5, __NA_, 0, VF610_SDHC_PAD_CTRL),
VF610_PAD_PTA26__ESDHC1_DAT0 = IOMUX_PAD(0x0040, 0x0040, 5, __NA_, 0, VF610_SDHC_PAD_CTRL),
@ -66,26 +111,40 @@ enum {
VF610_PAD_PTB14__I2C0_SCL = IOMUX_PAD(0x0090, 0x0090, 2, 0x033c, 1, VF610_I2C_PAD_CTRL),
VF610_PAD_PTB15__I2C0_SDA = IOMUX_PAD(0x0094, 0x0094, 2, 0x0340, 1, VF610_I2C_PAD_CTRL),
VF610_PAD_PTD31__NF_IO15 = IOMUX_PAD(0x00fc, 0x00fc, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL),
VF610_PAD_PTD31__GPIO_63 = IOMUX_PAD(0x00fc, 0x00fc, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
VF610_PAD_PTD30__NF_IO14 = IOMUX_PAD(0x0100, 0x0100, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL),
VF610_PAD_PTD30__GPIO_64 = IOMUX_PAD(0x0100, 0x0100, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
VF610_PAD_PTD29__NF_IO13 = IOMUX_PAD(0x0104, 0x0104, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL),
VF610_PAD_PTD29__GPIO_65 = IOMUX_PAD(0x0104, 0x0104, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
VF610_PAD_PTD28__NF_IO12 = IOMUX_PAD(0x0108, 0x0108, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL),
VF610_PAD_PTD28__GPIO_66 = IOMUX_PAD(0x0108, 0x0108, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
VF610_PAD_PTD27__NF_IO11 = IOMUX_PAD(0x010c, 0x010c, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL),
VF610_PAD_PTD27__GPIO_67 = IOMUX_PAD(0x010c, 0x010c, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
VF610_PAD_PTD26__NF_IO10 = IOMUX_PAD(0x0110, 0x0110, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL),
VF610_PAD_PTD26__GPIO_68 = IOMUX_PAD(0x0110, 0x0110, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
VF610_PAD_PTD25__NF_IO9 = IOMUX_PAD(0x0114, 0x0114, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL),
VF610_PAD_PTD25__GPIO_69 = IOMUX_PAD(0x0114, 0x0114, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
VF610_PAD_PTD24__NF_IO8 = IOMUX_PAD(0x0118, 0x0118, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL),
VF610_PAD_PTD24__GPIO_70 = IOMUX_PAD(0x0118, 0x0118, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
VF610_PAD_PTD23__NF_IO7 = IOMUX_PAD(0x011c, 0x011c, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL),
VF610_PAD_PTD0__QSPI0_A_QSCK = IOMUX_PAD(0x013c, 0x013c, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
VF610_PAD_PTD1__QSPI0_A_CS0 = IOMUX_PAD(0x0140, 0x0140, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
VF610_PAD_PTD2__QSPI0_A_DATA3 = IOMUX_PAD(0x0144, 0x0144, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
VF610_PAD_PTD3__QSPI0_A_DATA2 = IOMUX_PAD(0x0148, 0x0148, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
VF610_PAD_PTD4__GPIO_83 = IOMUX_PAD(0x014C, 0x014C, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
VF610_PAD_PTD4__QSPI0_A_DATA1 = IOMUX_PAD(0x014c, 0x014c, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
VF610_PAD_PTD5__QSPI0_A_DATA0 = IOMUX_PAD(0x0150, 0x0150, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
VF610_PAD_PTD7__QSPI0_B_QSCK = IOMUX_PAD(0x0158, 0x0158, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
VF610_PAD_PTD8__QSPI0_B_CS0 = IOMUX_PAD(0x015c, 0x015c, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
VF610_PAD_PTD9__QSPI0_B_DATA3 = IOMUX_PAD(0x0160, 0x0160, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
VF610_PAD_PTD9__GPIO_88 = IOMUX_PAD(0x0160, 0x0160, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
VF610_PAD_PTD10__QSPI0_B_DATA2 = IOMUX_PAD(0x0164, 0x0164, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
VF610_PAD_PTD10__GPIO_89 = IOMUX_PAD(0x0164, 0x0164, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
VF610_PAD_PTD11__QSPI0_B_DATA1 = IOMUX_PAD(0x0168, 0x0168, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
VF610_PAD_PTD11__GPIO_90 = IOMUX_PAD(0x0168, 0x0168, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
VF610_PAD_PTD12__QSPI0_B_DATA0 = IOMUX_PAD(0x016c, 0x016c, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
VF610_PAD_PTD12__GPIO_91 = IOMUX_PAD(0x016c, 0x016c, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
VF610_PAD_PTD13__GPIO_92 = IOMUX_PAD(0x0170, 0x0170, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
VF610_PAD_PTD22__NF_IO6 = IOMUX_PAD(0x0120, 0x0120, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL),
VF610_PAD_PTD21__NF_IO5 = IOMUX_PAD(0x0124, 0x0124, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL),
VF610_PAD_PTD20__NF_IO4 = IOMUX_PAD(0x0128, 0x0128, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL),

6
arch/arm/include/asm/imx-common/iomux-v3.h
View file

@ -187,6 +187,12 @@ void imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const *pad_list,
*/
void imx_iomux_set_gpr_register(int group, int start_bit,
int num_bits, int value);
#ifdef CONFIG_IOMUX_SHARE_CONF_REG
void imx_iomux_gpio_set_direction(unsigned int gpio,
unsigned int direction);
void imx_iomux_gpio_get_function(unsigned int gpio,
u32 *gpio_state);
#endif
/* macros for declaring and using pinmux array */
#if defined(CONFIG_MX6QDL)

55
board/bachmann/ot1200/ot1200.c
View file

@ -120,6 +120,42 @@ static void setup_iomux_features(void)
ARRAY_SIZE(feature_pads));
}
#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
/* I2C2 - EEPROM */
static struct i2c_pads_info i2c_pad_info1 = {
.scl = {
.i2c_mode = MX6_PAD_EIM_EB2__I2C2_SCL | PC,
.gpio_mode = MX6_PAD_EIM_EB2__GPIO2_IO30 | PC,
.gp = IMX_GPIO_NR(2, 30)
},
.sda = {
.i2c_mode = MX6_PAD_EIM_D16__I2C2_SDA | PC,
.gpio_mode = MX6_PAD_EIM_D16__GPIO3_IO16 | PC,
.gp = IMX_GPIO_NR(3, 16)
}
};
/* I2C3 - IO expander */
static struct i2c_pads_info i2c_pad_info2 = {
.scl = {
.i2c_mode = MX6_PAD_EIM_D17__I2C3_SCL | PC,
.gpio_mode = MX6_PAD_EIM_D17__GPIO3_IO17 | PC,
.gp = IMX_GPIO_NR(3, 17)
},
.sda = {
.i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC,
.gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 | PC,
.gp = IMX_GPIO_NR(3, 18)
}
};
static void setup_iomux_i2c(void)
{
setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
}
static void ccgr_init(void)
{
struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
@ -151,6 +187,7 @@ int board_early_init_f(void)
setup_iomux_uart();
setup_iomux_spi();
setup_iomux_i2c();
setup_iomux_features();
return 0;
@ -236,22 +273,6 @@ int board_mmc_init(bd_t *bis)
return 0;
}
#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
/* I2C3 - IO expander */
static struct i2c_pads_info i2c_pad_info2 = {
.scl = {
.i2c_mode = MX6_PAD_EIM_D17__I2C3_SCL | PC,
.gpio_mode = MX6_PAD_EIM_D17__GPIO3_IO17 | PC,
.gp = IMX_GPIO_NR(3, 17)
},
.sda = {
.i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC,
.gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 | PC,
.gp = IMX_GPIO_NR(3, 18)
}
};
static iomux_v3_cfg_t const pwm_pad[] = {
MX6_PAD_SD1_CMD__PWM4_OUT | MUX_PAD_CTRL(OUTPUT_40OHM),
};
@ -315,8 +336,6 @@ int board_init(void)
backlight_lcd_off();
setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
leds_on();
#ifdef CONFIG_CMD_SATA

92
board/gateworks/gw_ventana/common.c
View file

@ -191,7 +191,8 @@ static iomux_v3_cfg_t const gw52xx_gpio_pads[] = {
IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG),
/* IOEXP_IRQ# */
IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
/* CAN_STBY */
IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09 | DIO_PAD_CFG),
/* MX6_LOCLED# */
IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG),
/* GPS_SHDN */
@ -204,11 +205,17 @@ static iomux_v3_cfg_t const gw52xx_gpio_pads[] = {
IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG),
/* PCI_RST# (GW522x) */
IOMUX_PADS(PAD_EIM_D23__GPIO3_IO23 | DIO_PAD_CFG),
/* RS485_EN */
IOMUX_PADS(PAD_SD3_DAT4__GPIO7_IO01 | DIO_PAD_CFG),
/* PCIESKT_WDIS# */
IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
};
static iomux_v3_cfg_t const gw53xx_gpio_pads[] = {
/* CAN_STBY */
IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG),
/* USB_HUBRST# */
IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09 | DIO_PAD_CFG),
/* PANLEDG# */
IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
/* PANLEDR# */
@ -227,36 +234,46 @@ static iomux_v3_cfg_t const gw53xx_gpio_pads[] = {
IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG),
/* PCI_RST# */
IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG),
/* RS485_EN */
IOMUX_PADS(PAD_SD3_DAT4__GPIO7_IO01 | DIO_PAD_CFG),
/* PCIESKT_WDIS# */
IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
};
static iomux_v3_cfg_t const gw54xx_gpio_pads[] = {
/* CAN_STBY */
IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG),
/* PANLEDG# */
IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
/* PANLEDR# */
IOMUX_PADS(PAD_KEY_COL2__GPIO4_IO10 | DIO_PAD_CFG),
IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
/* MX6_LOCLED# */
IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG),
/* USB_HUBRST# */
IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16 | DIO_PAD_CFG),
/* MIPI_DIO */
IOMUX_PADS(PAD_SD1_DAT3__GPIO1_IO21 | DIO_PAD_CFG),
/* RS485_EN */
IOMUX_PADS(PAD_EIM_D24__GPIO3_IO24 | DIO_PAD_CFG),
/* IOEXP_PWREN# */
IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG),
/* IOEXP_IRQ# */
IOMUX_PADS(PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
/* DIOI2C_DIS# */
IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG),
/* PCI_RST# */
IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG),
/* VID_EN */
IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG),
/* RS485_EN */
IOMUX_PADS(PAD_SD3_DAT4__GPIO7_IO01 | DIO_PAD_CFG),
/* PCIESKT_WDIS# */
IOMUX_PADS(PAD_DISP0_DAT23__GPIO5_IO17 | DIO_PAD_CFG),
};
static iomux_v3_cfg_t const gw551x_gpio_pads[] = {
/* CAN_STBY */
IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09 | DIO_PAD_CFG),
/* PANLED# */
IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
/* PCI_RST# */
@ -266,6 +283,10 @@ static iomux_v3_cfg_t const gw551x_gpio_pads[] = {
};
static iomux_v3_cfg_t const gw552x_gpio_pads[] = {
/* USBOTG_SEL */
IOMUX_PADS(PAD_GPIO_7__GPIO1_IO07 | DIO_PAD_CFG),
/* USB_HUBRST# */
IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09 | DIO_PAD_CFG),
/* PANLEDG# */
IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
/* PANLEDR# */
@ -520,6 +541,32 @@ struct ventana gpio_cfg[GW_UNKNOWN] = {
{
.gpio_pads = gw551x_gpio_pads,
.num_pads = ARRAY_SIZE(gw551x_gpio_pads)/2,
.dio_cfg = {
{
{ IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
IMX_GPIO_NR(1, 19),
{ IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
2
},
{
{ IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
IMX_GPIO_NR(1, 17),
{ IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
3
},
},
.num_gpios = 2,
.leds = {
IMX_GPIO_NR(4, 7),
},
.pcie_rst = IMX_GPIO_NR(1, 0),
.wdis = IMX_GPIO_NR(7, 12),
},
/* GW552x */
{
.gpio_pads = gw552x_gpio_pads,
.num_pads = ARRAY_SIZE(gw552x_gpio_pads)/2,
.dio_cfg = {
{
{ IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
@ -540,36 +587,10 @@ struct ventana gpio_cfg[GW_UNKNOWN] = {
3
},
{
{ IOMUX_PADS(PAD_SD1_CMD__GPIO1_IO18) },
IMX_GPIO_NR(1, 18),
{ IOMUX_PADS(PAD_SD1_CMD__PWM4_OUT) },
4
},
},
.num_gpios = 2,
.leds = {
IMX_GPIO_NR(4, 7),
},
.pcie_rst = IMX_GPIO_NR(1, 0),
.wdis = IMX_GPIO_NR(7, 12),
},
/* GW552x */
{
.gpio_pads = gw552x_gpio_pads,
.num_pads = ARRAY_SIZE(gw552x_gpio_pads)/2,
.dio_cfg = {
{
{ IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
IMX_GPIO_NR(1, 19),
{ IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
2
},
{
{ IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
IMX_GPIO_NR(1, 17),
{ IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
3
{IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) },
IMX_GPIO_NR(1, 20),
{ 0, 0 },
0
},
},
.num_gpios = 4,
@ -579,6 +600,7 @@ struct ventana gpio_cfg[GW_UNKNOWN] = {
IMX_GPIO_NR(4, 15),
},
.pcie_rst = IMX_GPIO_NR(1, 29),
.usb_sel = IMX_GPIO_NR(1, 7),
.wdis = IMX_GPIO_NR(7, 12),
},
};
@ -712,7 +734,7 @@ void setup_board_gpio(int board, struct ventana_board_info *info)
* Configure DIO pinmux/padctl registers
* see IMX6DQRM/IMX6SDLRM IOMUXC_SW_PAD_CTL_PAD_* register definitions
*/
for (i = 0; i < 4; i++) {
for (i = 0; i < gpio_cfg[board].num_gpios; i++) {
struct dio_cfg *cfg = &gpio_cfg[board].dio_cfg[i];
iomux_v3_cfg_t ctrl = DIO_PAD_CFG;
unsigned cputype = is_cpu_type(MXC_CPU_MX6Q) ? 0 : 1;

6
board/gateworks/gw_ventana/common.h
View file

@ -34,10 +34,6 @@
PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED | \
PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
#define DIO_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
PAD_CTL_DSE_34ohm | PAD_CTL_HYS | PAD_CTL_SRE_FAST)
#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
PAD_CTL_ODE | PAD_CTL_SRE_FAST)
@ -46,7 +42,7 @@
PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
PAD_CTL_DSE_34ohm | PAD_CTL_HYS | PAD_CTL_SRE_FAST)
#define DIO_PAD_CFG (MUX_PAD_CTRL(DIO_PAD_CTRL) | MUX_MODE_SION)
#define DIO_PAD_CFG (MUX_PAD_CTRL(IRQ_PAD_CTRL) | MUX_MODE_SION)
#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)

41
board/gateworks/gw_ventana/gw_ventana.c
View file

@ -157,20 +157,18 @@ static iomux_v3_cfg_t const usb_pads[] = {
int board_ehci_hcd_init(int port)
{
struct ventana_board_info *info = &ventana_info;
int gpio;
SETUP_IOMUX_PADS(usb_pads);
/* Reset USB HUB (present on GW54xx/GW53xx) */
switch (info->model[3]) {
case '3': /* GW53xx */
case '5': /* GW552x */
SETUP_IOMUX_PAD(PAD_GPIO_9__GPIO1_IO09 | DIO_PAD_CFG);
/* Reset USB HUB */
switch (board_type) {
case GW53xx:
case GW552x:
gpio = (IMX_GPIO_NR(1, 9));
break;
case '4': /* GW54xx */
SETUP_IOMUX_PAD(PAD_SD1_DAT0__GPIO1_IO16 | DIO_PAD_CFG);
case GW54proto:
case GW54xx:
gpio = (IMX_GPIO_NR(1, 16));
break;
default:
@ -687,8 +685,7 @@ int misc_init_r(void)
memset(str, 0, sizeof(str));
for (i = 0; i < (sizeof(str)-1) && info->model[i]; i++)
str[i] = tolower(info->model[i]);
if (!getenv("model"))
setenv("model", str);
setenv("model", str);
if (!getenv("fdt_file")) {
sprintf(fdt, "%s-%s.dtb", cputype, str);
setenv("fdt_file", fdt);
@ -698,18 +695,14 @@ int misc_init_r(void)
*p++ = 0;
setenv("model_base", str);
if (!getenv("fdt_file1")) {
sprintf(fdt, "%s-%s.dtb", cputype, str);
setenv("fdt_file1", fdt);
}
sprintf(fdt, "%s-%s.dtb", cputype, str);
setenv("fdt_file1", fdt);
if (board_type != GW551x && board_type != GW552x)
str[4] = 'x';
str[5] = 'x';
str[6] = 0;
if (!getenv("fdt_file2")) {
sprintf(fdt, "%s-%s.dtb", cputype, str);
setenv("fdt_file2", fdt);
}
sprintf(fdt, "%s-%s.dtb", cputype, str);
setenv("fdt_file2", fdt);
}
/* initialize env from EEPROM */
@ -818,9 +811,11 @@ int ft_board_setup(void *blob, bd_t *bd)
return 0;
}
/* Update partition nodes using info from mtdparts env var */
puts(" Updating MTD partitions...\n");
fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
if (test_bit(EECONFIG_NAND, info->config)) {
/* Update partition nodes using info from mtdparts env var */
puts(" Updating MTD partitions...\n");
fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
}
/* Update display timings from display env var */
if (display) {
@ -829,10 +824,6 @@ int ft_board_setup(void *blob, bd_t *bd)
printf(" Set display timings for %s...\n", display);
}
if (!model) {
puts("invalid board info: Leaving FDT fully enabled\n");
return 0;
}
printf(" Adjusting FDT per EEPROM for %s...\n", model);
/* board serial number */

6
board/gateworks/gw_ventana/gw_ventana_spl.c
View file

@ -515,10 +515,8 @@ void board_init_f(ulong dummy)
setup_iomux_gpio(board_model, &ventana_info);
/* provide some some default: 32bit 128MB */
if (GW_UNKNOWN == board_model) {
ventana_info.sdram_width = 2;
ventana_info.sdram_size = 3;
}
if (GW_UNKNOWN == board_model)
hang();
/* configure MMDC for SDRAM width/size and per-model calibration */
spl_dram_init(8 << ventana_info.sdram_width,

4
board/toradex/colibri_vf/MAINTAINERS
View file

@ -4,3 +4,7 @@ S: Maintained
F: board/toradex/colibri_vf/
F: include/configs/colibri_vf.h
F: configs/colibri_vf_defconfig
F: configs/colibri_vf_dtb_defconfig
F: arch/arm/dts/vf-colibri.dtsi
F: arch/arm/dts/vf500-colibri.dts
F: arch/arm/dts/vf610-colibri.dts

106
board/toradex/colibri_vf/colibri_vf.c
View file

@ -20,6 +20,7 @@
#include <netdev.h>
#include <i2c.h>
#include <g_dnl.h>
#include <asm/gpio.h>
DECLARE_GLOBAL_DATA_PTR;
@ -32,6 +33,12 @@ DECLARE_GLOBAL_DATA_PTR;
#define ENET_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_HIGH | \
PAD_CTL_DSE_50ohm | PAD_CTL_OBE_IBE_ENABLE)
#define USB_PEN_GPIO 83
static const iomux_v3_cfg_t usb_pads[] = {
VF610_PAD_PTD4__GPIO_83,
};
int dram_init(void)
{
static const struct ddr3_jedec_timings timings = {
@ -146,6 +153,76 @@ static void setup_iomux_nfc(void)
}
#endif
#ifdef CONFIG_FSL_DSPI
static void setup_iomux_dspi(void)
{
static const iomux_v3_cfg_t dspi1_pads[] = {
VF610_PAD_PTD5__DSPI1_CS0,
VF610_PAD_PTD6__DSPI1_SIN,
VF610_PAD_PTD7__DSPI1_SOUT,
VF610_PAD_PTD8__DSPI1_SCK,
};
imx_iomux_v3_setup_multiple_pads(dspi1_pads, ARRAY_SIZE(dspi1_pads));
}
#endif
#ifdef CONFIG_VYBRID_GPIO
static void setup_iomux_gpio(void)
{
static const iomux_v3_cfg_t gpio_pads[] = {
VF610_PAD_PTA17__GPIO_7,
VF610_PAD_PTA20__GPIO_10,
VF610_PAD_PTA21__GPIO_11,
VF610_PAD_PTA30__GPIO_20,
VF610_PAD_PTA31__GPIO_21,
VF610_PAD_PTB0__GPIO_22,
VF610_PAD_PTB1__GPIO_23,
VF610_PAD_PTB6__GPIO_28,
VF610_PAD_PTB7__GPIO_29,
VF610_PAD_PTB8__GPIO_30,
VF610_PAD_PTB9__GPIO_31,
VF610_PAD_PTB12__GPIO_34,
VF610_PAD_PTB13__GPIO_35,
VF610_PAD_PTB16__GPIO_38,
VF610_PAD_PTB17__GPIO_39,
VF610_PAD_PTB18__GPIO_40,
VF610_PAD_PTB21__GPIO_43,
VF610_PAD_PTB22__GPIO_44,
VF610_PAD_PTC0__GPIO_45,
VF610_PAD_PTC1__GPIO_46,
VF610_PAD_PTC2__GPIO_47,
VF610_PAD_PTC3__GPIO_48,
VF610_PAD_PTC4__GPIO_49,
VF610_PAD_PTC5__GPIO_50,
VF610_PAD_PTC6__GPIO_51,
VF610_PAD_PTC7__GPIO_52,
VF610_PAD_PTC8__GPIO_53,
VF610_PAD_PTD31__GPIO_63,
VF610_PAD_PTD30__GPIO_64,
VF610_PAD_PTD29__GPIO_65,
VF610_PAD_PTD28__GPIO_66,
VF610_PAD_PTD27__GPIO_67,
VF610_PAD_PTD26__GPIO_68,
VF610_PAD_PTD25__GPIO_69,
VF610_PAD_PTD24__GPIO_70,
VF610_PAD_PTD9__GPIO_88,
VF610_PAD_PTD10__GPIO_89,
VF610_PAD_PTD11__GPIO_90,
VF610_PAD_PTD12__GPIO_91,
VF610_PAD_PTD13__GPIO_92,
VF610_PAD_PTB23__GPIO_93,
VF610_PAD_PTB26__GPIO_96,
VF610_PAD_PTB28__GPIO_98,
VF610_PAD_PTC29__GPIO_102,
VF610_PAD_PTC30__GPIO_103,
VF610_PAD_PTA7__GPIO_134,
};
imx_iomux_v3_setup_multiple_pads(gpio_pads, ARRAY_SIZE(gpio_pads));
}
#endif
#ifdef CONFIG_FSL_ESDHC
struct fsl_esdhc_cfg esdhc_cfg[1] = {
{ESDHC1_BASE_ADDR},
@ -196,6 +273,9 @@ static void clock_init(void)
clrsetbits_le32(&ccm->ccgr0, CCM_REG_CTRL_MASK,
CCM_CCGR0_UART0_CTRL_MASK);
#ifdef CONFIG_FSL_DSPI
setbits_le32(&ccm->ccgr0, CCM_CCGR0_DSPI1_CTRL_MASK);
#endif
clrsetbits_le32(&ccm->ccgr1, CCM_REG_CTRL_MASK,
CCM_CCGR1_PIT_CTRL_MASK | CCM_CCGR1_WDOGA5_CTRL_MASK);
clrsetbits_le32(&ccm->ccgr2, CCM_REG_CTRL_MASK,
@ -304,6 +384,14 @@ int board_early_init_f(void)
setup_iomux_nfc();
#endif
#ifdef CONFIG_VYBRID_GPIO
setup_iomux_gpio();
#endif
#ifdef CONFIG_FSL_DSPI
setup_iomux_dspi();
#endif
return 0;
}
@ -383,3 +471,21 @@ int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name)
return 0;
}
#ifdef CONFIG_USB_EHCI_VF
int board_ehci_hcd_init(int port)
{
imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads));
switch (port) {
case 0:
/* USBC does not have PEN, also configured as USB client only */
break;
case 1:
gpio_request(USB_PEN_GPIO, "usb-pen-gpio");
gpio_direction_output(USB_PEN_GPIO, 0);
break;
}
return 0;
}
#endif

26
board/wandboard/wandboard.c
View file

@ -50,6 +50,7 @@ DECLARE_GLOBAL_DATA_PTR;
#define USDHC1_CD_GPIO IMX_GPIO_NR(1, 2)
#define USDHC3_CD_GPIO IMX_GPIO_NR(3, 9)
#define ETH_PHY_RESET IMX_GPIO_NR(3, 29)
#define REV_DETECTION IMX_GPIO_NR(2, 28)
int dram_init(void)
{
@ -105,6 +106,10 @@ static iomux_v3_cfg_t const enet_pads[] = {
IOMUX_PADS(PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL)),
};
static iomux_v3_cfg_t const rev_detection_pad[] = {
IOMUX_PADS(PAD_EIM_EB0__GPIO2_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL)),
};
static void setup_iomux_uart(void)
{
SETUP_IOMUX_PADS(uart1_pads);
@ -393,6 +398,17 @@ static const struct boot_mode board_boot_modes[] = {
};
#endif
static bool is_revc1(void)
{
SETUP_IOMUX_PADS(rev_detection_pad);
gpio_direction_input(REV_DETECTION);
if (gpio_get_value(REV_DETECTION))
return true;
else
return false;
}
int board_late_init(void)
{
#ifdef CONFIG_CMD_BMODE
@ -404,6 +420,11 @@ int board_late_init(void)
setenv("board_rev", "MX6Q");
else
setenv("board_rev", "MX6DL");
if (is_revc1())
setenv("board_name", "C1");
else
setenv("board_name", "B1");
#endif
return 0;
}
@ -424,7 +445,10 @@ int board_init(void)
int checkboard(void)
{
puts("Board: Wandboard\n");
if (is_revc1())
puts("Board: Wandboard rev C1\n");
else
puts("Board: Wandboard rev B1\n");
return 0;
}

2
board/warp/README
View file

@ -34,7 +34,7 @@ Then U-boot should start and its messages will appear in the console program.
Use the default environment variables:
=> env default -f -a
=> save
=> saveenv
Run the DFU command:
=> dfu 0 mmc 0

1
configs/colibri_vf_defconfig
View file

@ -4,3 +4,4 @@ CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/colibri_vf/imximage.cfg,ENV_I
CONFIG_CMD_NET=y
CONFIG_NAND_VF610_NFC=y
CONFIG_SYS_NAND_VF610_NFC_60_ECC_BYTES=y
CONFIG_DM=y

8
configs/colibri_vf_dtb_defconfig Normal file
View file

@ -0,0 +1,8 @@
CONFIG_ARM=y
CONFIG_TARGET_COLIBRI_VF=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/colibri_vf/imximage.cfg,ENV_IS_IN_NAND,IMX_NAND"
CONFIG_NAND_VF610_NFC=y
CONFIG_SYS_NAND_VF610_NFC_60_ECC_BYTES=y
CONFIG_DM=y
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="vf610-colibri"

7
drivers/gpio/Kconfig
View file

@ -35,3 +35,10 @@ config SANDBOX_GPIO_COUNT
are specified using the device tree. But you can also have a number
of 'anonymous' GPIOs that do not belong to any device or bank.
Select a suitable value depending on your needs.
config VYBRID_GPIO
bool "Vybrid GPIO driver"
depends on DM
default n
help
Say yes here to support Vybrid vf610 GPIOs.

1
drivers/gpio/Makefile
View file

@ -45,3 +45,4 @@ obj-$(CONFIG_SUNXI_GPIO) += sunxi_gpio.o
obj-$(CONFIG_LPC32XX_GPIO) += lpc32xx_gpio.o
obj-$(CONFIG_STM32_GPIO) += stm32_gpio.o
obj-$(CONFIG_ZYNQ_GPIO) += zynq_gpio.o
obj-$(CONFIG_VYBRID_GPIO) += vybrid_gpio.o

1
drivers/gpio/gpio-uclass.c
View file

@ -757,6 +757,7 @@ static int gpio_pre_remove(struct udevice *dev)
UCLASS_DRIVER(gpio) = {
.id = UCLASS_GPIO,
.name = "gpio",
.flags = DM_UC_FLAG_SEQ_ALIAS,
.post_probe = gpio_post_probe,
.pre_remove = gpio_pre_remove,
.per_device_auto_alloc_size = sizeof(struct gpio_dev_priv),

169
drivers/gpio/vybrid_gpio.c Normal file
View file

@ -0,0 +1,169 @@
/*
* Copyright (C) 2015
* Bhuvanchandra DV, Toradex, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <dm.h>
#include <errno.h>
#include <fdtdec.h>
#include <asm/gpio.h>
#include <asm/imx-common/iomux-v3.h>
#include <asm/io.h>
#include <malloc.h>
DECLARE_GLOBAL_DATA_PTR;
struct vybrid_gpios {
unsigned int chip;
struct vybrid_gpio_regs *reg;
};
static int vybrid_gpio_direction_input(struct udevice *dev, unsigned gpio)
{
const struct vybrid_gpios *gpios = dev_get_priv(dev);
gpio = gpio + (gpios->chip * VYBRID_GPIO_COUNT);
imx_iomux_gpio_set_direction(gpio, VF610_GPIO_DIRECTION_IN);
return 0;
}
static int vybrid_gpio_direction_output(struct udevice *dev, unsigned gpio,
int value)
{
const struct vybrid_gpios *gpios = dev_get_priv(dev);
gpio = gpio + (gpios->chip * VYBRID_GPIO_COUNT);
gpio_set_value(gpio, value);
imx_iomux_gpio_set_direction(gpio, VF610_GPIO_DIRECTION_OUT);
return 0;
}
static int vybrid_gpio_get_value(struct udevice *dev, unsigned gpio)
{
const struct vybrid_gpios *gpios = dev_get_priv(dev);
return ((readl(&gpios->reg->gpio_pdir) & (1 << gpio))) ? 1 : 0;
}
static int vybrid_gpio_set_value(struct udevice *dev, unsigned gpio,
int value)
{
const struct vybrid_gpios *gpios = dev_get_priv(dev);
if (value)
writel((1 << gpio), &gpios->reg->gpio_psor);
else
writel((1 << gpio), &gpios->reg->gpio_pcor);
return 0;
}
static int vybrid_gpio_get_function(struct udevice *dev, unsigned gpio)
{
const struct vybrid_gpios *gpios = dev_get_priv(dev);
u32 g_state = 0;
gpio = gpio + (gpios->chip * VYBRID_GPIO_COUNT);
imx_iomux_gpio_get_function(gpio, &g_state);
if (((g_state & (0x07 << PAD_MUX_MODE_SHIFT)) >> PAD_MUX_MODE_SHIFT) > 0)
return GPIOF_FUNC;
if (g_state & PAD_CTL_OBE_ENABLE)
return GPIOF_OUTPUT;
if (g_state & PAD_CTL_IBE_ENABLE)
return GPIOF_INPUT;
if (!(g_state & PAD_CTL_OBE_IBE_ENABLE))
return GPIOF_UNUSED;
return GPIOF_UNKNOWN;
}
static const struct dm_gpio_ops gpio_vybrid_ops = {
.direction_input = vybrid_gpio_direction_input,
.direction_output = vybrid_gpio_direction_output,
.get_value = vybrid_gpio_get_value,
.set_value = vybrid_gpio_set_value,
.get_function = vybrid_gpio_get_function,
};
static int vybrid_gpio_probe(struct udevice *dev)
{
struct vybrid_gpios *gpios = dev_get_priv(dev);
struct vybrid_gpio_platdata *plat = dev_get_platdata(dev);
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
uc_priv->bank_name = plat->port_name;
uc_priv->gpio_count = VYBRID_GPIO_COUNT;
gpios->reg = (struct vybrid_gpio_regs *)plat->base;
gpios->chip = plat->chip;
return 0;
}
static int vybrid_gpio_bind(struct udevice *dev)
{
struct vybrid_gpio_platdata *plat = dev->platdata;
fdt_addr_t base_addr;
if (plat)
return 0;
base_addr = dev_get_addr(dev);
if (base_addr == FDT_ADDR_T_NONE)
return -ENODEV;
/*
* TODO:
* When every board is converted to driver model and DT is
* supported, this can be done by auto-alloc feature, but
* not using calloc to alloc memory for platdata.
*/
plat = calloc(1, sizeof(*plat));
if (!plat)
return -ENOMEM;
plat->base = base_addr;
plat->chip = dev->req_seq;
plat->port_name = fdt_get_name(gd->fdt_blob, dev->of_offset, NULL);
dev->platdata = plat;
return 0;
}
#ifndef CONFIG_OF_CONTROL
static const struct vybrid_gpio_platdata vybrid_gpio[] = {
{0, GPIO0_BASE_ADDR, "GPIO0 "},
{1, GPIO1_BASE_ADDR, "GPIO1 "},
{2, GPIO2_BASE_ADDR, "GPIO2 "},
{3, GPIO3_BASE_ADDR, "GPIO3 "},
{4, GPIO4_BASE_ADDR, "GPIO4 "},
};
U_BOOT_DEVICES(vybrid_gpio) = {
{ "gpio_vybrid", &vybrid_gpio[0] },
{ "gpio_vybrid", &vybrid_gpio[1] },
{ "gpio_vybrid", &vybrid_gpio[2] },
{ "gpio_vybrid", &vybrid_gpio[3] },
{ "gpio_vybrid", &vybrid_gpio[4] },
};
#endif
static const struct udevice_id vybrid_gpio_ids[] = {
{ .compatible = "fsl,vf610-gpio" },
{ }
};
U_BOOT_DRIVER(gpio_vybrid) = {
.name = "gpio_vybrid",
.id = UCLASS_GPIO,
.ops = &gpio_vybrid_ops,
.probe = vybrid_gpio_probe,
.priv_auto_alloc_size = sizeof(struct vybrid_gpios),
.of_match = vybrid_gpio_ids,
.bind = vybrid_gpio_bind,
};

4
drivers/pci/pcie_imx.c
View file

@ -588,7 +588,9 @@ static int imx_pcie_link_up(void)
udelay(10);
count++;
if (count >= 2000) {
debug("phy link never came up\n");
#ifdef CONFIG_PCI_SCAN_SHOW
puts("PCI: pcie phy link never came up\n");
#endif
debug("DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n",
readl(MX6_DBI_ADDR + PCIE_PHY_DEBUG_R0),
readl(MX6_DBI_ADDR + PCIE_PHY_DEBUG_R1));

8
drivers/usb/host/ehci-vf.c
View file

@ -121,6 +121,11 @@ static void usb_oc_config(int index)
setbits_le32(ctrl, UCTRL_OVER_CUR_DIS);
}
int __weak board_ehci_hcd_init(int port)
{
return 0;
}
int ehci_hcd_init(int index, enum usb_init_type init,
struct ehci_hccr **hccr, struct ehci_hcor **hcor)
{
@ -136,6 +141,9 @@ int ehci_hcd_init(int index, enum usb_init_type init,
ehci = (struct usb_ehci *)nc_reg_bases[index];
/* Do board specific initialisation */
board_ehci_hcd_init(index);
usb_power_config(index);
usb_oc_config(index);
usb_internal_phy_clock_gate(index);

12
include/configs/colibri_vf.h
View file

@ -54,6 +54,11 @@
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR
/* GPIO support */
#define CONFIG_DM_GPIO
#define CONFIG_CMD_GPIO
#define CONFIG_VYBRID_GPIO
/* Dynamic MTD partition support */
#define CONFIG_CMD_MTDPARTS /* Enable 'mtdparts' command line support */
#define CONFIG_MTD_PARTITIONS
@ -266,4 +271,11 @@
#define CONFIG_USB_GADGET_MASS_STORAGE
#define CONFIG_CMD_USB_MASS_STORAGE
/* Enable SPI support */
#ifdef CONFIG_OF_CONTROL
#define CONFIG_DM_SPI
#define CONFIG_CMD_SPI
#define CONFIG_FSL_DSPI
#endif
#endif /* __CONFIG_H */

10
include/configs/mx6_common.h
View file

@ -53,11 +53,19 @@
#define CONFIG_REVISION_TAG
/* Boot options */
#if (defined(CONFIG_MX6SX) || defined(CONFIG_MX6SL))
#define CONFIG_LOADADDR 0x82000000
#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE 0x87800000
#endif
#else
#define CONFIG_LOADADDR 0x12000000
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE 0x17800000
#endif
#endif
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
#ifndef CONFIG_BOOTDELAY
#define CONFIG_BOOTDELAY 3
#endif

18
include/configs/tqma6.h
View file

@ -22,6 +22,13 @@
/* #endif */
/* place code in last 4 MiB of RAM */
#if defined(CONFIG_MX6DL) || defined(CONFIG_MX6S)
#define CONFIG_SYS_TEXT_BASE 0x2fc00000
#elif defined(CONFIG_MX6Q) || defined(CONFIG_MX6D)
#define CONFIG_SYS_TEXT_BASE 0x4fc00000
#endif
#include "mx6_common.h"
#if defined(CONFIG_MX6DL) || defined(CONFIG_MX6S)
@ -116,13 +123,6 @@
#define CONFIG_CMD_BMODE
#define CONFIG_CMD_ITEST
/* place code in last 4 MiB of RAM */
#if defined(CONFIG_MX6DL) || defined(CONFIG_MX6S)
#define CONFIG_SYS_TEXT_BASE 0x2fc00000
#elif defined(CONFIG_MX6Q) || defined(CONFIG_MX6D)
#define CONFIG_SYS_TEXT_BASE 0x4fc00000
#endif
#define CONFIG_ENV_SIZE (SZ_8K)
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * SZ_1M)
@ -367,10 +367,6 @@
"panicboot=echo No boot device !!! reset\0" \
TQMA6_EXTRA_BOOTDEV_ENV_SETTINGS \
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_STACKSIZE (128u * SZ_1K)
/* Physical Memory Map */

4
include/configs/tqma6_mba6.h
View file

@ -1,5 +1,5 @@
/*
* Copyright (C) 2013, 2014 Markus Niebel <Markus.Niebel@tq-group.com>
* Copyright (C) 2013 - 2015 Markus Niebel <Markus.Niebel@tq-group.com>
*
* Configuration settings for the TQ Systems TQMa6<Q,S> module.
*
@ -11,7 +11,7 @@
#if defined(CONFIG_MX6DL) || defined(CONFIG_MX6S)
#define CONFIG_DEFAULT_FDT_FILE "imx6dl-mba6x.dtb"
#elif defined(CONFIG_MX6Q) || defined(CONFIG_MX6Q)
#elif defined(CONFIG_MX6Q) || defined(CONFIG_MX6D)
#define CONFIG_DEFAULT_FDT_FILE "imx6q-mba6x.dtb"
#endif

8
include/configs/wandboard.h
View file

@ -192,10 +192,14 @@
"bootz; " \
"fi;\0" \
"findfdt="\
"if test $board_rev = MX6Q ; then " \
"if test $board_name = C1 && test $board_rev = MX6Q ; then " \
"setenv fdtfile imx6q-wandboard.dtb; fi; " \
"if test $board_rev = MX6DL ; then " \
"if test $board_name = C1 && test $board_rev = MX6DL ; then " \
"setenv fdtfile imx6dl-wandboard.dtb; fi; " \
"if test $board_name = B1 && test $board_rev = MX6Q ; then " \
"setenv fdtfile imx6q-wandboard-revb1.dtb; fi; " \
"if test $board_name = B1 && test $board_rev = MX6DL ; then " \
"setenv fdtfile imx6dl-wandboard-revb1.dtb; fi; " \
"if test $fdtfile = undefined; then " \
"echo WARNING: Could not determine dtb to use; fi; \0" \

9
include/configs/warp.h
View file

@ -25,9 +25,10 @@
#define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR
/* MMC Configs */
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
#define CONFIG_SYS_FSL_ESDHC_FORCE_VSELECT
#define CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE
#define CONFIG_SUPPORT_EMMC_BOOT
/* Command definition */
#undef CONFIG_CMD_NFS
@ -93,9 +94,13 @@
#define CONFIG_CMD_DFU
#define CONFIG_DFU_FUNCTION
#define CONFIG_DFU_MMC
#define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_32M
#define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_16M
#define DFU_DEFAULT_POLL_TIMEOUT 300
/* Fuses */
#define CONFIG_CMD_FUSE
#define CONFIG_MXC_OCOTP
#define CONFIG_EXTRA_ENV_SETTINGS \
"script=boot.scr\0" \
"image=zImage\0" \