mirror of
https://github.com/Fishwaldo/u-boot.git
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aspeed: Add I2C Driver
Add Device Model based I2C driver for ast2500/ast2400 SoCs. The driver is very limited, it only supports master mode and synchronous byte-by-byte reads/writes, no DMA or Pool Buffers. Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Heiko Schocher <hs@denx.de>
This commit is contained in:
maxims@google.com
Tom Rini
parent
4999bb06cc
commit
4dc038f3a1
4 changed files with 499 additions and 0 deletions
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@ -114,6 +114,15 @@ config SYS_I2C_DW_ENABLE_STATUS_UNSUPPORTED
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enable status register. This config option can be enabled in such
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cases.
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config SYS_I2C_ASPEED
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bool "Aspeed I2C Controller"
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depends on DM_I2C && ARCH_ASPEED
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help
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Say yes here to select Aspeed I2C Host Controller. The driver
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supports AST2500 and AST2400 controllers, but is very limited.
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Only single master mode is supported and only byte-by-byte
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synchronous reads and writes are supported, no Pool Buffers or DMA.
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config SYS_I2C_INTEL
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bool "Intel I2C/SMBUS driver"
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depends on DM_I2C
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@ -15,6 +15,7 @@ obj-$(CONFIG_I2C_MV) += mv_i2c.o
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obj-$(CONFIG_TSI108_I2C) += tsi108_i2c.o
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obj-$(CONFIG_SH_SH7734_I2C) += sh_sh7734_i2c.o
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obj-$(CONFIG_SYS_I2C) += i2c_core.o
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obj-$(CONFIG_SYS_I2C_ASPEED) += ast_i2c.o
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obj-$(CONFIG_SYS_I2C_AT91) += at91_i2c.o
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obj-$(CONFIG_SYS_I2C_CADENCE) += i2c-cdns.o
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obj-$(CONFIG_SYS_I2C_DAVINCI) += davinci_i2c.o
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357
drivers/i2c/ast_i2c.c
Normal file
357
drivers/i2c/ast_i2c.c
Normal file
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@ -0,0 +1,357 @@
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/*
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* Copyright (C) 2012-2020 ASPEED Technology Inc.
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* Copyright 2016 IBM Corporation
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* Copyright 2017 Google, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <clk.h>
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#include <dm.h>
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#include <errno.h>
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#include <fdtdec.h>
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#include <i2c.h>
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#include <asm/io.h>
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#include <asm/arch/scu_ast2500.h>
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#include "ast_i2c.h"
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#define I2C_TIMEOUT_US 100000
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#define I2C_SLEEP_STEP_US 20
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#define HIGHSPEED_TTIMEOUT 3
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DECLARE_GLOBAL_DATA_PTR;
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/*
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* Device private data
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*/
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struct ast_i2c_priv {
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/* This device's clock */
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struct clk clk;
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/* Device registers */
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struct ast_i2c_regs *regs;
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/* I2C speed in Hz */
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int speed;
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};
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/*
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* Given desired divider ratio, return the value that needs to be set
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* in Clock and AC Timing Control register
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*/
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static u32 get_clk_reg_val(ulong divider_ratio)
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{
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ulong inc = 0, div;
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ulong scl_low, scl_high, data;
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for (div = 0; divider_ratio >= 16; div++) {
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inc |= (divider_ratio & 1);
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divider_ratio >>= 1;
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}
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divider_ratio += inc;
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scl_low = (divider_ratio >> 1) - 1;
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scl_high = divider_ratio - scl_low - 2;
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data = I2CD_CACTC_BASE
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| (scl_high << I2CD_TCKHIGH_SHIFT)
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| (scl_low << I2CD_TCKLOW_SHIFT)
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| (div << I2CD_BASE_DIV_SHIFT);
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return data;
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}
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static void ast_i2c_clear_interrupts(struct udevice *dev)
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{
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struct ast_i2c_priv *priv = dev_get_priv(dev);
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writel(~0, &priv->regs->isr);
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}
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static void ast_i2c_init_bus(struct udevice *dev)
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{
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struct ast_i2c_priv *priv = dev_get_priv(dev);
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/* Reset device */
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writel(0, &priv->regs->fcr);
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/* Enable Master Mode. Assuming single-master */
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writel(I2CD_MASTER_EN
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| I2CD_M_SDA_LOCK_EN
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| I2CD_MULTI_MASTER_DIS | I2CD_M_SCL_DRIVE_EN,
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&priv->regs->fcr);
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/* Enable Interrupts */
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writel(I2CD_INTR_TX_ACK
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| I2CD_INTR_TX_NAK
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| I2CD_INTR_RX_DONE
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| I2CD_INTR_BUS_RECOVER_DONE
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| I2CD_INTR_NORMAL_STOP
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| I2CD_INTR_ABNORMAL, &priv->regs->icr);
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}
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static int ast_i2c_ofdata_to_platdata(struct udevice *dev)
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{
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struct ast_i2c_priv *priv = dev_get_priv(dev);
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int ret;
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priv->regs = dev_get_addr_ptr(dev);
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if (IS_ERR(priv->regs))
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return PTR_ERR(priv->regs);
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ret = clk_get_by_index(dev, 0, &priv->clk);
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if (ret < 0) {
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debug("%s: Can't get clock for %s: %d\n", __func__, dev->name,
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ret);
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return ret;
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}
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return 0;
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}
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static int ast_i2c_probe(struct udevice *dev)
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{
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struct ast2500_scu *scu;
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debug("Enabling I2C%u\n", dev->seq);
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/*
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* Get all I2C devices out of Reset.
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* Only needs to be done once, but doing it for every
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* device does not hurt.
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*/
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scu = ast_get_scu();
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ast_scu_unlock(scu);
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clrbits_le32(&scu->sysreset_ctrl1, SCU_SYSRESET_I2C);
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ast_scu_lock(scu);
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ast_i2c_init_bus(dev);
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return 0;
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}
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static int ast_i2c_wait_isr(struct udevice *dev, u32 flag)
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{
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struct ast_i2c_priv *priv = dev_get_priv(dev);
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int timeout = I2C_TIMEOUT_US;
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while (!(readl(&priv->regs->isr) & flag) && timeout > 0) {
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udelay(I2C_SLEEP_STEP_US);
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timeout -= I2C_SLEEP_STEP_US;
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}
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ast_i2c_clear_interrupts(dev);
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if (timeout <= 0)
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return -ETIMEDOUT;
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return 0;
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}
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static int ast_i2c_send_stop(struct udevice *dev)
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{
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struct ast_i2c_priv *priv = dev_get_priv(dev);
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writel(I2CD_M_STOP_CMD, &priv->regs->csr);
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return ast_i2c_wait_isr(dev, I2CD_INTR_NORMAL_STOP);
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}
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static int ast_i2c_wait_tx(struct udevice *dev)
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{
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struct ast_i2c_priv *priv = dev_get_priv(dev);
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int timeout = I2C_TIMEOUT_US;
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u32 flag = I2CD_INTR_TX_ACK | I2CD_INTR_TX_NAK;
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u32 status = readl(&priv->regs->isr) & flag;
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int ret = 0;
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while (!status && timeout > 0) {
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status = readl(&priv->regs->isr) & flag;
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udelay(I2C_SLEEP_STEP_US);
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timeout -= I2C_SLEEP_STEP_US;
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}
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if (status == I2CD_INTR_TX_NAK)
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ret = -EREMOTEIO;
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if (timeout <= 0)
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ret = -ETIMEDOUT;
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ast_i2c_clear_interrupts(dev);
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return ret;
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}
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static int ast_i2c_start_txn(struct udevice *dev, uint devaddr)
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{
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struct ast_i2c_priv *priv = dev_get_priv(dev);
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/* Start and Send Device Address */
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writel(devaddr, &priv->regs->trbbr);
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writel(I2CD_M_START_CMD | I2CD_M_TX_CMD, &priv->regs->csr);
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return ast_i2c_wait_tx(dev);
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}
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static int ast_i2c_read_data(struct udevice *dev, u8 chip_addr, u8 *buffer,
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size_t len, bool send_stop)
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{
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struct ast_i2c_priv *priv = dev_get_priv(dev);
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u32 i2c_cmd = I2CD_M_RX_CMD;
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int ret;
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ret = ast_i2c_start_txn(dev, (chip_addr << 1) | I2C_M_RD);
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if (ret < 0)
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return ret;
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for (; len > 0; len--, buffer++) {
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if (len == 1)
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i2c_cmd |= I2CD_M_S_RX_CMD_LAST;
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writel(i2c_cmd, &priv->regs->csr);
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ret = ast_i2c_wait_isr(dev, I2CD_INTR_RX_DONE);
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if (ret < 0)
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return ret;
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*buffer = (readl(&priv->regs->trbbr) & I2CD_RX_DATA_MASK)
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>> I2CD_RX_DATA_SHIFT;
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}
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ast_i2c_clear_interrupts(dev);
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if (send_stop)
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return ast_i2c_send_stop(dev);
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return 0;
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}
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static int ast_i2c_write_data(struct udevice *dev, u8 chip_addr, u8
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*buffer, size_t len, bool send_stop)
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{
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struct ast_i2c_priv *priv = dev_get_priv(dev);
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int ret;
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ret = ast_i2c_start_txn(dev, (chip_addr << 1));
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if (ret < 0)
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return ret;
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for (; len > 0; len--, buffer++) {
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writel(*buffer, &priv->regs->trbbr);
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writel(I2CD_M_TX_CMD, &priv->regs->csr);
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ret = ast_i2c_wait_tx(dev);
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if (ret < 0)
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return ret;
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}
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if (send_stop)
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return ast_i2c_send_stop(dev);
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return 0;
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}
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static int ast_i2c_deblock(struct udevice *dev)
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{
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struct ast_i2c_priv *priv = dev_get_priv(dev);
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struct ast_i2c_regs *regs = priv->regs;
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u32 csr = readl(®s->csr);
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bool sda_high = csr & I2CD_SDA_LINE_STS;
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bool scl_high = csr & I2CD_SCL_LINE_STS;
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int ret = 0;
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if (sda_high && scl_high) {
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/* Bus is idle, no deblocking needed. */
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return 0;
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} else if (sda_high) {
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/* Send stop command */
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debug("Unterminated TXN in (%x), sending stop\n", csr);
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ret = ast_i2c_send_stop(dev);
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} else if (scl_high) {
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/* Possibly stuck slave */
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debug("Bus stuck (%x), attempting recovery\n", csr);
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writel(I2CD_BUS_RECOVER_CMD, ®s->csr);
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ret = ast_i2c_wait_isr(dev, I2CD_INTR_BUS_RECOVER_DONE);
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} else {
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/* Just try to reinit the device. */
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ast_i2c_init_bus(dev);
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}
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return ret;
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}
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static int ast_i2c_xfer(struct udevice *dev, struct i2c_msg *msg, int nmsgs)
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{
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int ret;
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ret = ast_i2c_deblock(dev);
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if (ret < 0)
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return ret;
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debug("i2c_xfer: %d messages\n", nmsgs);
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for (; nmsgs > 0; nmsgs--, msg++) {
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if (msg->flags & I2C_M_RD) {
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debug("i2c_read: chip=0x%x, len=0x%x, flags=0x%x\n",
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msg->addr, msg->len, msg->flags);
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ret = ast_i2c_read_data(dev, msg->addr, msg->buf,
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msg->len, (nmsgs == 1));
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} else {
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debug("i2c_write: chip=0x%x, len=0x%x, flags=0x%x\n",
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msg->addr, msg->len, msg->flags);
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ret = ast_i2c_write_data(dev, msg->addr, msg->buf,
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msg->len, (nmsgs == 1));
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}
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if (ret) {
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debug("%s: error (%d)\n", __func__, ret);
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return -EREMOTEIO;
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}
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}
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return 0;
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}
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static int ast_i2c_set_speed(struct udevice *dev, unsigned int speed)
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{
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struct ast_i2c_priv *priv = dev_get_priv(dev);
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struct ast_i2c_regs *regs = priv->regs;
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ulong i2c_rate, divider;
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debug("Setting speed for I2C%d to <%u>\n", dev->seq, speed);
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if (!speed) {
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debug("No valid speed specified\n");
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return -EINVAL;
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}
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i2c_rate = clk_get_rate(&priv->clk);
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divider = i2c_rate / speed;
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priv->speed = speed;
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if (speed > I2C_HIGHSPEED_RATE) {
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debug("Enable High Speed\n");
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setbits_le32(®s->fcr, I2CD_M_HIGH_SPEED_EN
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| I2CD_M_SDA_DRIVE_1T_EN
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| I2CD_SDA_DRIVE_1T_EN);
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writel(HIGHSPEED_TTIMEOUT, ®s->cactcr2);
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} else {
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debug("Enabling Normal Speed\n");
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writel(I2CD_NO_TIMEOUT_CTRL, ®s->cactcr2);
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}
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writel(get_clk_reg_val(divider), ®s->cactcr1);
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ast_i2c_clear_interrupts(dev);
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return 0;
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}
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static const struct dm_i2c_ops ast_i2c_ops = {
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.xfer = ast_i2c_xfer,
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.set_bus_speed = ast_i2c_set_speed,
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.deblock = ast_i2c_deblock,
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};
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static const struct udevice_id ast_i2c_ids[] = {
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{ .compatible = "aspeed,ast2400-i2c-bus" },
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{ .compatible = "aspeed,ast2500-i2c-bus" },
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{ },
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};
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U_BOOT_DRIVER(ast_i2c) = {
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.name = "ast_i2c",
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.id = UCLASS_I2C,
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.of_match = ast_i2c_ids,
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.probe = ast_i2c_probe,
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.ofdata_to_platdata = ast_i2c_ofdata_to_platdata,
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.priv_auto_alloc_size = sizeof(struct ast_i2c_priv),
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.ops = &ast_i2c_ops,
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};
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132
drivers/i2c/ast_i2c.h
Normal file
132
drivers/i2c/ast_i2c.h
Normal file
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@ -0,0 +1,132 @@
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/*
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* Copyright (C) 2012-2020 ASPEED Technology Inc.
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* Copyright 2016 IBM Corporation
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* Copyright 2017 Google, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __AST_I2C_H_
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#define __AST_I2C_H_
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struct ast_i2c_regs {
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u32 fcr;
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u32 cactcr1;
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u32 cactcr2;
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u32 icr;
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u32 isr;
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u32 csr;
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u32 sdar;
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u32 pbcr;
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u32 trbbr;
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#ifdef CONFIG_ASPEED_AST2500
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u32 dma_mbar;
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u32 dma_tlr;
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#endif
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};
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/* Device Register Definition */
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/* 0x00 : I2CD Function Control Register */
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#define I2CD_BUFF_SEL_MASK (0x7 << 20)
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#define I2CD_BUFF_SEL(x) (x << 20)
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#define I2CD_M_SDA_LOCK_EN (0x1 << 16)
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#define I2CD_MULTI_MASTER_DIS (0x1 << 15)
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#define I2CD_M_SCL_DRIVE_EN (0x1 << 14)
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#define I2CD_MSB_STS (0x1 << 9)
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#define I2CD_SDA_DRIVE_1T_EN (0x1 << 8)
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#define I2CD_M_SDA_DRIVE_1T_EN (0x1 << 7)
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#define I2CD_M_HIGH_SPEED_EN (0x1 << 6)
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#define I2CD_DEF_ADDR_EN (0x1 << 5)
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#define I2CD_DEF_ALERT_EN (0x1 << 4)
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#define I2CD_DEF_ARP_EN (0x1 << 3)
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#define I2CD_DEF_GCALL_EN (0x1 << 2)
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#define I2CD_SLAVE_EN (0x1 << 1)
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#define I2CD_MASTER_EN (0x1)
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/* 0x04 : I2CD Clock and AC Timing Control Register #1 */
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/* Base register value. These bits are always set by the driver. */
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#define I2CD_CACTC_BASE 0xfff00300
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#define I2CD_TCKHIGH_SHIFT 16
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#define I2CD_TCKLOW_SHIFT 12
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#define I2CD_THDDAT_SHIFT 10
|
||||
#define I2CD_TO_DIV_SHIFT 8
|
||||
#define I2CD_BASE_DIV_SHIFT 0
|
||||
|
||||
/* 0x08 : I2CD Clock and AC Timing Control Register #2 */
|
||||
#define I2CD_tTIMEOUT 1
|
||||
#define I2CD_NO_TIMEOUT_CTRL 0
|
||||
|
||||
/* 0x0c : I2CD Interrupt Control Register &
|
||||
* 0x10 : I2CD Interrupt Status Register
|
||||
*
|
||||
* These share bit definitions, so use the same values for the enable &
|
||||
* status bits.
|
||||
*/
|
||||
#define I2CD_INTR_SDA_DL_TIMEOUT (0x1 << 14)
|
||||
#define I2CD_INTR_BUS_RECOVER_DONE (0x1 << 13)
|
||||
#define I2CD_INTR_SMBUS_ALERT (0x1 << 12)
|
||||
#define I2CD_INTR_SMBUS_ARP_ADDR (0x1 << 11)
|
||||
#define I2CD_INTR_SMBUS_DEV_ALERT_ADDR (0x1 << 10)
|
||||
#define I2CD_INTR_SMBUS_DEF_ADDR (0x1 << 9)
|
||||
#define I2CD_INTR_GCALL_ADDR (0x1 << 8)
|
||||
#define I2CD_INTR_SLAVE_MATCH (0x1 << 7)
|
||||
#define I2CD_INTR_SCL_TIMEOUT (0x1 << 6)
|
||||
#define I2CD_INTR_ABNORMAL (0x1 << 5)
|
||||
#define I2CD_INTR_NORMAL_STOP (0x1 << 4)
|
||||
#define I2CD_INTR_ARBIT_LOSS (0x1 << 3)
|
||||
#define I2CD_INTR_RX_DONE (0x1 << 2)
|
||||
#define I2CD_INTR_TX_NAK (0x1 << 1)
|
||||
#define I2CD_INTR_TX_ACK (0x1 << 0)
|
||||
|
||||
/* 0x14 : I2CD Command/Status Register */
|
||||
#define I2CD_SDA_OE (0x1 << 28)
|
||||
#define I2CD_SDA_O (0x1 << 27)
|
||||
#define I2CD_SCL_OE (0x1 << 26)
|
||||
#define I2CD_SCL_O (0x1 << 25)
|
||||
#define I2CD_TX_TIMING (0x1 << 24)
|
||||
#define I2CD_TX_STATUS (0x1 << 23)
|
||||
|
||||
/* Tx State Machine */
|
||||
#define I2CD_IDLE 0x0
|
||||
#define I2CD_MACTIVE 0x8
|
||||
#define I2CD_MSTART 0x9
|
||||
#define I2CD_MSTARTR 0xa
|
||||
#define I2CD_MSTOP 0xb
|
||||
#define I2CD_MTXD 0xc
|
||||
#define I2CD_MRXACK 0xd
|
||||
#define I2CD_MRXD 0xe
|
||||
#define I2CD_MTXACK 0xf
|
||||
#define I2CD_SWAIT 0x1
|
||||
#define I2CD_SRXD 0x4
|
||||
#define I2CD_STXACK 0x5
|
||||
#define I2CD_STXD 0x6
|
||||
#define I2CD_SRXACK 0x7
|
||||
#define I2CD_RECOVER 0x3
|
||||
|
||||
#define I2CD_SCL_LINE_STS (0x1 << 18)
|
||||
#define I2CD_SDA_LINE_STS (0x1 << 17)
|
||||
#define I2CD_BUS_BUSY_STS (0x1 << 16)
|
||||
#define I2CD_SDA_OE_OUT_DIR (0x1 << 15)
|
||||
#define I2CD_SDA_O_OUT_DIR (0x1 << 14)
|
||||
#define I2CD_SCL_OE_OUT_DIR (0x1 << 13)
|
||||
#define I2CD_SCL_O_OUT_DIR (0x1 << 12)
|
||||
#define I2CD_BUS_RECOVER_CMD (0x1 << 11)
|
||||
#define I2CD_S_ALT_EN (0x1 << 10)
|
||||
#define I2CD_RX_DMA_ENABLE (0x1 << 9)
|
||||
#define I2CD_TX_DMA_ENABLE (0x1 << 8)
|
||||
|
||||
/* Command Bit */
|
||||
#define I2CD_RX_BUFF_ENABLE (0x1 << 7)
|
||||
#define I2CD_TX_BUFF_ENABLE (0x1 << 6)
|
||||
#define I2CD_M_STOP_CMD (0x1 << 5)
|
||||
#define I2CD_M_S_RX_CMD_LAST (0x1 << 4)
|
||||
#define I2CD_M_RX_CMD (0x1 << 3)
|
||||
#define I2CD_S_TX_CMD (0x1 << 2)
|
||||
#define I2CD_M_TX_CMD (0x1 << 1)
|
||||
#define I2CD_M_START_CMD 0x1
|
||||
|
||||
#define I2CD_RX_DATA_SHIFT 8
|
||||
#define I2CD_RX_DATA_MASK (0xff << I2CD_RX_DATA_SHIFT)
|
||||
|
||||
#define I2C_HIGHSPEED_RATE 400000
|
||||
|
||||
#endif /* __AST_I2C_H_ */
|
||||
Loading…
Add table
Reference in a new issue