mirror of
https://github.com/Fishwaldo/u-boot.git
synced 2025-03-19 05:31:32 +00:00
Make Freescale local bus registers available for both 83xx and 85xx.
- Rename lbus83xx_t to fsl_lbus_t and move it to asm/fsl_lbc.h so that it can be shared by both 83xx and 85xx - Remove lbus83xx_t and replace it with fsl_lbus_t in all 83xx boards files which use lbus83xx_t. - Move FMR, FIR, FCR, FPAR, LTESR from mpc83xx.h to asm/fsl_lbc.h so that 85xx can share them. Signed-off-by: Jason Jin <Jason.Jin@freescale.com> Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
This commit is contained in:
parent
695c130e4b
commit
4e190b03aa
12 changed files with 157 additions and 152 deletions
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@ -110,7 +110,7 @@ static long fixed_sdram(void)
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phys_size_t initdram(int board_type)
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phys_size_t initdram(int board_type)
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{
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{
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volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
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volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
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volatile lbus83xx_t *lbc = &im->lbus;
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volatile fsl_lbus_t *lbc = &im->lbus;
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u32 msize;
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u32 msize;
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if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
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if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
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@ -192,7 +192,7 @@ int checkboard (void)
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void sdram_init(void)
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void sdram_init(void)
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{
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{
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volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
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volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
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volatile lbus83xx_t *lbc= &immap->lbus;
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volatile fsl_lbus_t *lbc = &immap->lbus;
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uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
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uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
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/*
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/*
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@ -221,7 +221,7 @@ int misc_init_f(void)
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0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01
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0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01
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};
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};
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volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
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volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
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volatile lbus83xx_t *lbus = &immap->lbus;
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volatile fsl_lbus_t *lbus = &immap->lbus;
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lbus->bank[3].br = CONFIG_SYS_BR3_PRELIM;
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lbus->bank[3].br = CONFIG_SYS_BR3_PRELIM;
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lbus->bank[3].or = CONFIG_SYS_OR3_PRELIM;
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lbus->bank[3].or = CONFIG_SYS_OR3_PRELIM;
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@ -227,7 +227,7 @@ int checkboard(void)
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static int sdram_init(unsigned int base)
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static int sdram_init(unsigned int base)
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{
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{
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volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
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volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
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volatile lbus83xx_t *lbc = &immap->lbus;
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volatile fsl_lbus_t *lbc = &immap->lbus;
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const int sdram_size = CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024;
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const int sdram_size = CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024;
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int rem = base % sdram_size;
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int rem = base % sdram_size;
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uint *sdram_addr;
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uint *sdram_addr;
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@ -160,7 +160,7 @@ int checkboard (void)
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void sdram_init(void)
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void sdram_init(void)
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{
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{
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volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
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volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
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volatile lbus83xx_t *lbc= &immap->lbus;
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volatile fsl_lbus_t *lbc = &immap->lbus;
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uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
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uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
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puts("\n SDRAM on Local Bus: ");
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puts("\n SDRAM on Local Bus: ");
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@ -148,7 +148,7 @@ int checkcpu(void)
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void upmconfig (uint upm, uint *table, uint size)
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void upmconfig (uint upm, uint *table, uint size)
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{
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{
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volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
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volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
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volatile lbus83xx_t *lbus = &immap->lbus;
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volatile fsl_lbus_t *lbus = &immap->lbus;
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volatile uchar *dummy = NULL;
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volatile uchar *dummy = NULL;
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const u32 msel = (upm + 4) << BR_MSEL_SHIFT; /* What the MSEL field in BRn should be */
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const u32 msel = (upm + 4) << BR_MSEL_SHIFT; /* What the MSEL field in BRn should be */
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volatile u32 *mxmr = &lbus->mamr + upm; /* Pointer to mamr, mbmr, or mcmr */
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volatile u32 *mxmr = &lbus->mamr + upm; /* Pointer to mamr, mbmr, or mcmr */
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@ -75,7 +75,7 @@ struct fsl_elbc_ctrl {
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struct fsl_elbc_mtd *chips[MAX_BANKS];
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struct fsl_elbc_mtd *chips[MAX_BANKS];
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/* device info */
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/* device info */
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lbus83xx_t *regs;
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fsl_lbus_t *regs;
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u8 __iomem *addr; /* Address of assigned FCM buffer */
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u8 __iomem *addr; /* Address of assigned FCM buffer */
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unsigned int page; /* Last page written to / read from */
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unsigned int page; /* Last page written to / read from */
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unsigned int read_bytes; /* Number of bytes read during command */
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unsigned int read_bytes; /* Number of bytes read during command */
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@ -171,7 +171,7 @@ static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob)
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struct nand_chip *chip = mtd->priv;
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struct nand_chip *chip = mtd->priv;
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struct fsl_elbc_mtd *priv = chip->priv;
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struct fsl_elbc_mtd *priv = chip->priv;
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struct fsl_elbc_ctrl *ctrl = priv->ctrl;
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struct fsl_elbc_ctrl *ctrl = priv->ctrl;
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lbus83xx_t *lbc = ctrl->regs;
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fsl_lbus_t *lbc = ctrl->regs;
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int buf_num;
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int buf_num;
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ctrl->page = page_addr;
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ctrl->page = page_addr;
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@ -211,7 +211,7 @@ static int fsl_elbc_run_command(struct mtd_info *mtd)
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struct nand_chip *chip = mtd->priv;
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struct nand_chip *chip = mtd->priv;
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struct fsl_elbc_mtd *priv = chip->priv;
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struct fsl_elbc_mtd *priv = chip->priv;
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struct fsl_elbc_ctrl *ctrl = priv->ctrl;
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struct fsl_elbc_ctrl *ctrl = priv->ctrl;
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lbus83xx_t *lbc = ctrl->regs;
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fsl_lbus_t *lbc = ctrl->regs;
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long long end_tick;
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long long end_tick;
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u32 ltesr;
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u32 ltesr;
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@ -261,7 +261,7 @@ static void fsl_elbc_do_read(struct nand_chip *chip, int oob)
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{
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{
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struct fsl_elbc_mtd *priv = chip->priv;
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struct fsl_elbc_mtd *priv = chip->priv;
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struct fsl_elbc_ctrl *ctrl = priv->ctrl;
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struct fsl_elbc_ctrl *ctrl = priv->ctrl;
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lbus83xx_t *lbc = ctrl->regs;
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fsl_lbus_t *lbc = ctrl->regs;
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if (priv->page_size) {
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if (priv->page_size) {
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out_be32(&lbc->fir,
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out_be32(&lbc->fir,
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@ -295,7 +295,7 @@ static void fsl_elbc_cmdfunc(struct mtd_info *mtd, unsigned int command,
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struct nand_chip *chip = mtd->priv;
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struct nand_chip *chip = mtd->priv;
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struct fsl_elbc_mtd *priv = chip->priv;
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struct fsl_elbc_mtd *priv = chip->priv;
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struct fsl_elbc_ctrl *ctrl = priv->ctrl;
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struct fsl_elbc_ctrl *ctrl = priv->ctrl;
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lbus83xx_t *lbc = ctrl->regs;
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fsl_lbus_t *lbc = ctrl->regs;
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ctrl->use_mdr = 0;
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ctrl->use_mdr = 0;
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@ -633,7 +633,7 @@ static int fsl_elbc_wait(struct mtd_info *mtd, struct nand_chip *chip)
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{
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{
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struct fsl_elbc_mtd *priv = chip->priv;
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struct fsl_elbc_mtd *priv = chip->priv;
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struct fsl_elbc_ctrl *ctrl = priv->ctrl;
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struct fsl_elbc_ctrl *ctrl = priv->ctrl;
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lbus83xx_t *lbc = ctrl->regs;
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fsl_lbus_t *lbc = ctrl->regs;
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if (ctrl->status != LTESR_CC)
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if (ctrl->status != LTESR_CC)
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return NAND_STATUS_FAIL;
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return NAND_STATUS_FAIL;
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@ -693,13 +693,15 @@ static struct fsl_elbc_ctrl *elbc_ctrl;
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static void fsl_elbc_ctrl_init(void)
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static void fsl_elbc_ctrl_init(void)
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{
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{
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immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
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elbc_ctrl = kzalloc(sizeof(*elbc_ctrl), GFP_KERNEL);
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elbc_ctrl = kzalloc(sizeof(*elbc_ctrl), GFP_KERNEL);
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if (!elbc_ctrl)
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if (!elbc_ctrl)
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return;
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return;
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elbc_ctrl->regs = &im->lbus;
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#ifdef CONFIG_MPC85xx
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elbc_ctrl->regs = (void *)CONFIG_SYS_MPC85xx_LBC_ADDR;
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#else
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elbc_ctrl->regs = &((immap_t *)CONFIG_SYS_IMMR)->lbus;
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#endif
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/* clear event registers */
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/* clear event registers */
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out_be32(&elbc_ctrl->regs->ltesr, LTESR_NAND_MASK);
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out_be32(&elbc_ctrl->regs->ltesr, LTESR_NAND_MASK);
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@ -307,4 +307,134 @@
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#define LTEDR_RAWA 0x00400000 /* Read-after-write-atomic error checking disable */
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#define LTEDR_RAWA 0x00400000 /* Read-after-write-atomic error checking disable */
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#define LTEDR_CSD 0x00080000 /* Chip select error checking disable */
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#define LTEDR_CSD 0x00080000 /* Chip select error checking disable */
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/* FMR - Flash Mode Register
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*/
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#define FMR_CWTO 0x0000F000
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#define FMR_CWTO_SHIFT 12
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#define FMR_BOOT 0x00000800
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#define FMR_ECCM 0x00000100
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#define FMR_AL 0x00000030
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#define FMR_AL_SHIFT 4
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#define FMR_OP 0x00000003
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#define FMR_OP_SHIFT 0
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/* FIR - Flash Instruction Register
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*/
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#define FIR_OP0 0xF0000000
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#define FIR_OP0_SHIFT 28
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#define FIR_OP1 0x0F000000
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#define FIR_OP1_SHIFT 24
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#define FIR_OP2 0x00F00000
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#define FIR_OP2_SHIFT 20
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#define FIR_OP3 0x000F0000
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#define FIR_OP3_SHIFT 16
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#define FIR_OP4 0x0000F000
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#define FIR_OP4_SHIFT 12
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#define FIR_OP5 0x00000F00
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#define FIR_OP5_SHIFT 8
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#define FIR_OP6 0x000000F0
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#define FIR_OP6_SHIFT 4
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#define FIR_OP7 0x0000000F
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#define FIR_OP7_SHIFT 0
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#define FIR_OP_NOP 0x0 /* No operation and end of sequence */
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#define FIR_OP_CA 0x1 /* Issue current column address */
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#define FIR_OP_PA 0x2 /* Issue current block+page address */
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#define FIR_OP_UA 0x3 /* Issue user defined address */
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#define FIR_OP_CM0 0x4 /* Issue command from FCR[CMD0] */
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#define FIR_OP_CM1 0x5 /* Issue command from FCR[CMD1] */
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#define FIR_OP_CM2 0x6 /* Issue command from FCR[CMD2] */
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#define FIR_OP_CM3 0x7 /* Issue command from FCR[CMD3] */
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#define FIR_OP_WB 0x8 /* Write FBCR bytes from FCM buffer */
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#define FIR_OP_WS 0x9 /* Write 1 or 2 bytes from MDR[AS] */
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#define FIR_OP_RB 0xA /* Read FBCR bytes to FCM buffer */
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#define FIR_OP_RS 0xB /* Read 1 or 2 bytes to MDR[AS] */
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#define FIR_OP_CW0 0xC /* Wait then issue FCR[CMD0] */
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#define FIR_OP_CW1 0xD /* Wait then issue FCR[CMD1] */
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#define FIR_OP_RBW 0xE /* Wait then read FBCR bytes */
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#define FIR_OP_RSW 0xF /* Wait then read 1 or 2 bytes */
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/* FCR - Flash Command Register
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*/
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#define FCR_CMD0 0xFF000000
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#define FCR_CMD0_SHIFT 24
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#define FCR_CMD1 0x00FF0000
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#define FCR_CMD1_SHIFT 16
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#define FCR_CMD2 0x0000FF00
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#define FCR_CMD2_SHIFT 8
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#define FCR_CMD3 0x000000FF
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#define FCR_CMD3_SHIFT 0
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/* FBAR - Flash Block Address Register
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*/
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#define FBAR_BLK 0x00FFFFFF
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/* FPAR - Flash Page Address Register
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*/
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#define FPAR_SP_PI 0x00007C00
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#define FPAR_SP_PI_SHIFT 10
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#define FPAR_SP_MS 0x00000200
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#define FPAR_SP_CI 0x000001FF
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#define FPAR_SP_CI_SHIFT 0
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#define FPAR_LP_PI 0x0003F000
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#define FPAR_LP_PI_SHIFT 12
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#define FPAR_LP_MS 0x00000800
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#define FPAR_LP_CI 0x000007FF
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#define FPAR_LP_CI_SHIFT 0
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/* LTESR - Transfer Error Status Register
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*/
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#define LTESR_BM 0x80000000
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#define LTESR_FCT 0x40000000
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#define LTESR_PAR 0x20000000
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#define LTESR_WP 0x04000000
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#define LTESR_ATMW 0x00800000
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#define LTESR_ATMR 0x00400000
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#define LTESR_CS 0x00080000
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#define LTESR_CC 0x00000001
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#ifndef __ASSEMBLY__
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/*
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* Local Bus Controller Registers.
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*/
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typedef struct lbus_bank {
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u32 br; /* Base Register */
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u32 or; /* Option Register */
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} lbus_bank_t;
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typedef struct fsl_lbus {
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lbus_bank_t bank[8];
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u8 res0[0x28];
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u32 mar; /* UPM Address Register */
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u8 res1[0x4];
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u32 mamr; /* UPMA Mode Register */
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u32 mbmr; /* UPMB Mode Register */
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u32 mcmr; /* UPMC Mode Register */
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u8 res2[0x8];
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u32 mrtpr; /* Memory Refresh Timer Prescaler Register */
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u32 mdr; /* UPM Data Register */
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u8 res3[0x4];
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u32 lsor; /* Special Operation Initiation Register */
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u32 lsdmr; /* SDRAM Mode Register */
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u8 res4[0x8];
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u32 lurt; /* UPM Refresh Timer */
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u32 lsrt; /* SDRAM Refresh Timer */
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u8 res5[0x8];
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u32 ltesr; /* Transfer Error Status Register */
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u32 ltedr; /* Transfer Error Disable Register */
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u32 lteir; /* Transfer Error Interrupt Register */
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u32 lteatr; /* Transfer Error Attributes Register */
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u32 ltear; /* Transfer Error Address Register */
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u8 res6[0xC];
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u32 lbcr; /* Configuration Register */
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u32 lcrr; /* Clock Ratio Register */
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u8 res7[0x8];
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u32 fmr; /* Flash Mode Register */
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u32 fir; /* Flash Instruction Register */
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u32 fcr; /* Flash Command Register */
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u32 fbar; /* Flash Block Addr Register */
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u32 fpar; /* Flash Page Addr Register */
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u32 fbcr; /* Flash Byte Count Register */
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u8 res8[0xF08];
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} fsl_lbus_t;
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#endif /* __ASSEMBLY__ */
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#endif /* __ASM_PPC_FSL_LBC_H */
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#endif /* __ASM_PPC_FSL_LBC_H */
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#include <asm/types.h>
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#include <asm/types.h>
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#include <asm/fsl_i2c.h>
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#include <asm/fsl_i2c.h>
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#include <asm/mpc8xxx_spi.h>
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#include <asm/mpc8xxx_spi.h>
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#include <asm/fsl_lbc.h>
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/*
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/*
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* Local Access Window
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* Local Access Window
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@ -342,50 +343,6 @@ typedef struct duart83xx {
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u8 res2[0xEC];
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u8 res2[0xEC];
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} duart83xx_t;
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} duart83xx_t;
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/*
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* Local Bus Controller Registers
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*/
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typedef struct lbus_bank {
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u32 br; /* Base Register */
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u32 or; /* Option Register */
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} lbus_bank_t;
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typedef struct lbus83xx {
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|
||||||
lbus_bank_t bank[8];
|
|
||||||
u8 res0[0x28];
|
|
||||||
u32 mar; /* UPM Address Register */
|
|
||||||
u8 res1[0x4];
|
|
||||||
u32 mamr; /* UPMA Mode Register */
|
|
||||||
u32 mbmr; /* UPMB Mode Register */
|
|
||||||
u32 mcmr; /* UPMC Mode Register */
|
|
||||||
u8 res2[0x8];
|
|
||||||
u32 mrtpr; /* Memory Refresh Timer Prescaler Register */
|
|
||||||
u32 mdr; /* UPM Data Register */
|
|
||||||
u8 res3[0x4];
|
|
||||||
u32 lsor; /* Special Operation Initiation Register */
|
|
||||||
u32 lsdmr; /* SDRAM Mode Register */
|
|
||||||
u8 res4[0x8];
|
|
||||||
u32 lurt; /* UPM Refresh Timer */
|
|
||||||
u32 lsrt; /* SDRAM Refresh Timer */
|
|
||||||
u8 res5[0x8];
|
|
||||||
u32 ltesr; /* Transfer Error Status Register */
|
|
||||||
u32 ltedr; /* Transfer Error Disable Register */
|
|
||||||
u32 lteir; /* Transfer Error Interrupt Register */
|
|
||||||
u32 lteatr; /* Transfer Error Attributes Register */
|
|
||||||
u32 ltear; /* Transfer Error Address Register */
|
|
||||||
u8 res6[0xC];
|
|
||||||
u32 lbcr; /* Configuration Register */
|
|
||||||
u32 lcrr; /* Clock Ratio Register */
|
|
||||||
u8 res7[0x8];
|
|
||||||
u32 fmr; /* Flash Mode Register */
|
|
||||||
u32 fir; /* Flash Instruction Register */
|
|
||||||
u32 fcr; /* Flash Command Register */
|
|
||||||
u32 fbar; /* Flash Block Addr Register */
|
|
||||||
u32 fpar; /* Flash Page Addr Register */
|
|
||||||
u32 fbcr; /* Flash Byte Count Register */
|
|
||||||
u8 res8[0xF08];
|
|
||||||
} lbus83xx_t;
|
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* DMA/Messaging Unit
|
* DMA/Messaging Unit
|
||||||
*/
|
*/
|
||||||
|
@ -614,7 +571,7 @@ typedef struct immap {
|
||||||
u8 res2[0x1300];
|
u8 res2[0x1300];
|
||||||
duart83xx_t duart[2]; /* DUART */
|
duart83xx_t duart[2]; /* DUART */
|
||||||
u8 res3[0x900];
|
u8 res3[0x900];
|
||||||
lbus83xx_t lbus; /* Local Bus Controller Registers */
|
fsl_lbus_t lbus; /* Local Bus Controller Registers */
|
||||||
u8 res4[0x1000];
|
u8 res4[0x1000];
|
||||||
spi8xxx_t spi; /* Serial Peripheral Interface */
|
spi8xxx_t spi; /* Serial Peripheral Interface */
|
||||||
dma83xx_t dma; /* DMA */
|
dma83xx_t dma; /* DMA */
|
||||||
|
@ -648,7 +605,7 @@ typedef struct immap {
|
||||||
u8 res1[0x1300];
|
u8 res1[0x1300];
|
||||||
duart83xx_t duart[2]; /* DUART */
|
duart83xx_t duart[2]; /* DUART */
|
||||||
u8 res2[0x900];
|
u8 res2[0x900];
|
||||||
lbus83xx_t lbus; /* Local Bus Controller Registers */
|
fsl_lbus_t lbus; /* Local Bus Controller Registers */
|
||||||
u8 res3[0x1000];
|
u8 res3[0x1000];
|
||||||
spi8xxx_t spi; /* Serial Peripheral Interface */
|
spi8xxx_t spi; /* Serial Peripheral Interface */
|
||||||
dma83xx_t dma; /* DMA */
|
dma83xx_t dma; /* DMA */
|
||||||
|
@ -683,7 +640,7 @@ typedef struct immap {
|
||||||
u8 res1[0x1300];
|
u8 res1[0x1300];
|
||||||
duart83xx_t duart[2]; /* DUART */
|
duart83xx_t duart[2]; /* DUART */
|
||||||
u8 res2[0x900];
|
u8 res2[0x900];
|
||||||
lbus83xx_t lbus; /* Local Bus Controller Registers */
|
fsl_lbus_t lbus; /* Local Bus Controller Registers */
|
||||||
u8 res3[0x1000];
|
u8 res3[0x1000];
|
||||||
spi8xxx_t spi; /* Serial Peripheral Interface */
|
spi8xxx_t spi; /* Serial Peripheral Interface */
|
||||||
dma83xx_t dma; /* DMA */
|
dma83xx_t dma; /* DMA */
|
||||||
|
@ -728,7 +685,7 @@ typedef struct immap {
|
||||||
u8 res1[0x1300];
|
u8 res1[0x1300];
|
||||||
duart83xx_t duart[2]; /* DUART */
|
duart83xx_t duart[2]; /* DUART */
|
||||||
u8 res2[0x900];
|
u8 res2[0x900];
|
||||||
lbus83xx_t lbus; /* Local Bus Controller Registers */
|
fsl_lbus_t lbus; /* Local Bus Controller Registers */
|
||||||
u8 res3[0x1000];
|
u8 res3[0x1000];
|
||||||
spi8xxx_t spi; /* Serial Peripheral Interface */
|
spi8xxx_t spi; /* Serial Peripheral Interface */
|
||||||
dma83xx_t dma; /* DMA */
|
dma83xx_t dma; /* DMA */
|
||||||
|
@ -778,7 +735,7 @@ typedef struct immap {
|
||||||
u8 res4[0x1300];
|
u8 res4[0x1300];
|
||||||
duart83xx_t duart[2]; /* DUART */
|
duart83xx_t duart[2]; /* DUART */
|
||||||
u8 res5[0x900];
|
u8 res5[0x900];
|
||||||
lbus83xx_t lbus; /* Local Bus Controller Registers */
|
fsl_lbus_t lbus; /* Local Bus Controller Registers */
|
||||||
u8 res6[0x2000];
|
u8 res6[0x2000];
|
||||||
dma83xx_t dma; /* DMA */
|
dma83xx_t dma; /* DMA */
|
||||||
pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */
|
pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */
|
||||||
|
@ -817,7 +774,7 @@ typedef struct immap {
|
||||||
u8 res3[0x1300];
|
u8 res3[0x1300];
|
||||||
duart83xx_t duart[2]; /* DUART */
|
duart83xx_t duart[2]; /* DUART */
|
||||||
u8 res4[0x900];
|
u8 res4[0x900];
|
||||||
lbus83xx_t lbus; /* Local Bus Controller Registers */
|
fsl_lbus_t lbus; /* Local Bus Controller Registers */
|
||||||
u8 res5[0x2000];
|
u8 res5[0x2000];
|
||||||
dma83xx_t dma; /* DMA */
|
dma83xx_t dma; /* DMA */
|
||||||
pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */
|
pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */
|
||||||
|
|
|
@ -13,6 +13,7 @@
|
||||||
|
|
||||||
#include <asm/types.h>
|
#include <asm/types.h>
|
||||||
#include <asm/fsl_i2c.h>
|
#include <asm/fsl_i2c.h>
|
||||||
|
#include <asm/fsl_lbc.h>
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Local-Access Registers and ECM Registers(0x0000-0x2000)
|
* Local-Access Registers and ECM Registers(0x0000-0x2000)
|
||||||
|
|
|
@ -1147,91 +1147,6 @@
|
||||||
*/
|
*/
|
||||||
#define PMCCR1_POWER_OFF 0x00000020
|
#define PMCCR1_POWER_OFF 0x00000020
|
||||||
|
|
||||||
/* FMR - Flash Mode Register
|
|
||||||
*/
|
|
||||||
#define FMR_CWTO 0x0000F000
|
|
||||||
#define FMR_CWTO_SHIFT 12
|
|
||||||
#define FMR_BOOT 0x00000800
|
|
||||||
#define FMR_ECCM 0x00000100
|
|
||||||
#define FMR_AL 0x00000030
|
|
||||||
#define FMR_AL_SHIFT 4
|
|
||||||
#define FMR_OP 0x00000003
|
|
||||||
#define FMR_OP_SHIFT 0
|
|
||||||
|
|
||||||
/* FIR - Flash Instruction Register
|
|
||||||
*/
|
|
||||||
#define FIR_OP0 0xF0000000
|
|
||||||
#define FIR_OP0_SHIFT 28
|
|
||||||
#define FIR_OP1 0x0F000000
|
|
||||||
#define FIR_OP1_SHIFT 24
|
|
||||||
#define FIR_OP2 0x00F00000
|
|
||||||
#define FIR_OP2_SHIFT 20
|
|
||||||
#define FIR_OP3 0x000F0000
|
|
||||||
#define FIR_OP3_SHIFT 16
|
|
||||||
#define FIR_OP4 0x0000F000
|
|
||||||
#define FIR_OP4_SHIFT 12
|
|
||||||
#define FIR_OP5 0x00000F00
|
|
||||||
#define FIR_OP5_SHIFT 8
|
|
||||||
#define FIR_OP6 0x000000F0
|
|
||||||
#define FIR_OP6_SHIFT 4
|
|
||||||
#define FIR_OP7 0x0000000F
|
|
||||||
#define FIR_OP7_SHIFT 0
|
|
||||||
#define FIR_OP_NOP 0x0 /* No operation and end of sequence */
|
|
||||||
#define FIR_OP_CA 0x1 /* Issue current column address */
|
|
||||||
#define FIR_OP_PA 0x2 /* Issue current block+page address */
|
|
||||||
#define FIR_OP_UA 0x3 /* Issue user defined address */
|
|
||||||
#define FIR_OP_CM0 0x4 /* Issue command from FCR[CMD0] */
|
|
||||||
#define FIR_OP_CM1 0x5 /* Issue command from FCR[CMD1] */
|
|
||||||
#define FIR_OP_CM2 0x6 /* Issue command from FCR[CMD2] */
|
|
||||||
#define FIR_OP_CM3 0x7 /* Issue command from FCR[CMD3] */
|
|
||||||
#define FIR_OP_WB 0x8 /* Write FBCR bytes from FCM buffer */
|
|
||||||
#define FIR_OP_WS 0x9 /* Write 1 or 2 bytes from MDR[AS] */
|
|
||||||
#define FIR_OP_RB 0xA /* Read FBCR bytes to FCM buffer */
|
|
||||||
#define FIR_OP_RS 0xB /* Read 1 or 2 bytes to MDR[AS] */
|
|
||||||
#define FIR_OP_CW0 0xC /* Wait then issue FCR[CMD0] */
|
|
||||||
#define FIR_OP_CW1 0xD /* Wait then issue FCR[CMD1] */
|
|
||||||
#define FIR_OP_RBW 0xE /* Wait then read FBCR bytes */
|
|
||||||
#define FIR_OP_RSW 0xF /* Wait then read 1 or 2 bytes */
|
|
||||||
|
|
||||||
/* FCR - Flash Command Register
|
|
||||||
*/
|
|
||||||
#define FCR_CMD0 0xFF000000
|
|
||||||
#define FCR_CMD0_SHIFT 24
|
|
||||||
#define FCR_CMD1 0x00FF0000
|
|
||||||
#define FCR_CMD1_SHIFT 16
|
|
||||||
#define FCR_CMD2 0x0000FF00
|
|
||||||
#define FCR_CMD2_SHIFT 8
|
|
||||||
#define FCR_CMD3 0x000000FF
|
|
||||||
#define FCR_CMD3_SHIFT 0
|
|
||||||
|
|
||||||
/* FBAR - Flash Block Address Register
|
|
||||||
*/
|
|
||||||
#define FBAR_BLK 0x00FFFFFF
|
|
||||||
|
|
||||||
/* FPAR - Flash Page Address Register
|
|
||||||
*/
|
|
||||||
#define FPAR_SP_PI 0x00007C00
|
|
||||||
#define FPAR_SP_PI_SHIFT 10
|
|
||||||
#define FPAR_SP_MS 0x00000200
|
|
||||||
#define FPAR_SP_CI 0x000001FF
|
|
||||||
#define FPAR_SP_CI_SHIFT 0
|
|
||||||
#define FPAR_LP_PI 0x0003F000
|
|
||||||
#define FPAR_LP_PI_SHIFT 12
|
|
||||||
#define FPAR_LP_MS 0x00000800
|
|
||||||
#define FPAR_LP_CI 0x000007FF
|
|
||||||
#define FPAR_LP_CI_SHIFT 0
|
|
||||||
|
|
||||||
/* LTESR - Transfer Error Status Register
|
|
||||||
*/
|
|
||||||
#define LTESR_BM 0x80000000
|
|
||||||
#define LTESR_FCT 0x40000000
|
|
||||||
#define LTESR_PAR 0x20000000
|
|
||||||
#define LTESR_WP 0x04000000
|
|
||||||
#define LTESR_ATMW 0x00800000
|
|
||||||
#define LTESR_ATMR 0x00400000
|
|
||||||
#define LTESR_CS 0x00080000
|
|
||||||
#define LTESR_CC 0x00000001
|
|
||||||
|
|
||||||
/* DDRCDR - DDR Control Driver Register
|
/* DDRCDR - DDR Control Driver Register
|
||||||
*/
|
*/
|
||||||
#define DDRCDR_DHC_EN 0x80000000
|
#define DDRCDR_DHC_EN 0x80000000
|
||||||
|
|
|
@ -33,7 +33,7 @@
|
||||||
|
|
||||||
static void nand_wait(void)
|
static void nand_wait(void)
|
||||||
{
|
{
|
||||||
lbus83xx_t *regs = (lbus83xx_t *)(CONFIG_SYS_IMMR + 0x5000);
|
fsl_lbus_t *regs = (fsl_lbus_t *)(CONFIG_SYS_IMMR + 0x5000);
|
||||||
|
|
||||||
for (;;) {
|
for (;;) {
|
||||||
uint32_t status = in_be32(®s->ltesr);
|
uint32_t status = in_be32(®s->ltesr);
|
||||||
|
@ -50,7 +50,7 @@ static void nand_wait(void)
|
||||||
|
|
||||||
static void nand_load(unsigned int offs, int uboot_size, uchar *dst)
|
static void nand_load(unsigned int offs, int uboot_size, uchar *dst)
|
||||||
{
|
{
|
||||||
lbus83xx_t *regs = (lbus83xx_t *)(CONFIG_SYS_IMMR + 0x5000);
|
fsl_lbus_t *regs = (fsl_lbus_t *)(CONFIG_SYS_IMMR + 0x5000);
|
||||||
uchar *buf = (uchar *)CONFIG_SYS_NAND_BASE;
|
uchar *buf = (uchar *)CONFIG_SYS_NAND_BASE;
|
||||||
int large = in_be32(®s->bank[0].or) & OR_FCM_PGS;
|
int large = in_be32(®s->bank[0].or) & OR_FCM_PGS;
|
||||||
int block_shift = large ? 17 : 14;
|
int block_shift = large ? 17 : 14;
|
||||||
|
|
Loading…
Add table
Reference in a new issue