mirror of
https://github.com/Fishwaldo/u-boot.git
synced 2025-03-18 13:11:31 +00:00
ARM: uniphier: rename variable for DRAM controller base address
Rename the variable that contains the base address for consistency. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
This commit is contained in:
Masahiro Yamada
parent
a191e0dee0
commit
4e651003e5
4 changed files with 113 additions and 114 deletions
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@ -76,7 +76,7 @@ static void umc_start_ssif(void __iomem *ssif_base)
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writel(0x00000001, ssif_base + UMC_DMDRST);
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}
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static int umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base,
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static int umc_dramcont_init(void __iomem *dc_base, void __iomem *ca_base,
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int freq, unsigned long size, bool ddr3plus)
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{
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enum dram_freq freq_e;
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@ -113,29 +113,29 @@ static int umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base,
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return -EINVAL;
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}
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writel(umc_cmdctla_plus[freq_e], dramcont + UMC_CMDCTLA);
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writel(umc_cmdctlb_plus[freq_e], dramcont + UMC_CMDCTLB);
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writel(umc_spcctla[freq_e][size_e], dramcont + UMC_SPCCTLA);
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writel(umc_spcctlb[freq_e], dramcont + UMC_SPCCTLB);
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writel(umc_rdatactl[freq_e], dramcont + UMC_RDATACTL_D0);
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writel(0x04060806, dramcont + UMC_WDATACTL_D0);
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writel(0x04a02000, dramcont + UMC_DATASET);
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writel(umc_cmdctla_plus[freq_e], dc_base + UMC_CMDCTLA);
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writel(umc_cmdctlb_plus[freq_e], dc_base + UMC_CMDCTLB);
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writel(umc_spcctla[freq_e][size_e], dc_base + UMC_SPCCTLA);
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writel(umc_spcctlb[freq_e], dc_base + UMC_SPCCTLB);
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writel(umc_rdatactl[freq_e], dc_base + UMC_RDATACTL_D0);
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writel(0x04060806, dc_base + UMC_WDATACTL_D0);
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writel(0x04a02000, dc_base + UMC_DATASET);
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writel(0x00000000, ca_base + 0x2300);
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writel(0x00400020, dramcont + UMC_DCCGCTL);
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writel(0x00000003, dramcont + 0x7000);
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writel(0x0000000f, dramcont + 0x8000);
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writel(0x000000c3, dramcont + 0x8004);
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writel(0x00000071, dramcont + 0x8008);
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writel(0x0000003b, dramcont + UMC_DICGCTLA);
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writel(0x020a0808, dramcont + UMC_DICGCTLB);
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writel(0x00000004, dramcont + UMC_FLOWCTLG);
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writel(0x00400020, dc_base + UMC_DCCGCTL);
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writel(0x00000003, dc_base + 0x7000);
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writel(0x0000000f, dc_base + 0x8000);
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writel(0x000000c3, dc_base + 0x8004);
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writel(0x00000071, dc_base + 0x8008);
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writel(0x0000003b, dc_base + UMC_DICGCTLA);
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writel(0x020a0808, dc_base + UMC_DICGCTLB);
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writel(0x00000004, dc_base + UMC_FLOWCTLG);
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writel(0x80000201, ca_base + 0xc20);
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writel(0x0801e01e, dramcont + UMC_FLOWCTLA);
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writel(0x00200000, dramcont + UMC_FLOWCTLB);
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writel(0x00004444, dramcont + UMC_FLOWCTLC);
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writel(0x200a0a00, dramcont + UMC_SPCSETB);
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writel(0x00000000, dramcont + UMC_SPCSETD);
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writel(0x00000520, dramcont + UMC_DFICUPDCTLA);
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writel(0x0801e01e, dc_base + UMC_FLOWCTLA);
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writel(0x00200000, dc_base + UMC_FLOWCTLB);
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writel(0x00004444, dc_base + UMC_FLOWCTLC);
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writel(0x200a0a00, dc_base + UMC_SPCSETB);
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writel(0x00000000, dc_base + UMC_SPCSETD);
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writel(0x00000520, dc_base + UMC_DFICUPDCTLA);
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return 0;
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}
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@ -68,10 +68,10 @@ static void umc_start_ssif(void __iomem *ssif_base)
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writel(0x00000001, ssif_base + UMC_DMDRST);
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}
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static int umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base,
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static int umc_dramcont_init(void __iomem *dc_base, void __iomem *ca_base,
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int freq, unsigned long size, bool ddr3plus)
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{
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enum dram_size dram_size;
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enum dram_size size_e;
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if (freq != 1600) {
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pr_err("Unsupported DDR frequency %d MHz\n", freq);
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@ -85,43 +85,43 @@ static int umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base,
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switch (size) {
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case SZ_128M:
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dram_size = DRAM_SZ_128M;
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size_e = DRAM_SZ_128M;
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break;
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case SZ_256M:
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dram_size = DRAM_SZ_256M;
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size_e = DRAM_SZ_256M;
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break;
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case SZ_512M:
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dram_size = DRAM_SZ_512M;
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size_e = DRAM_SZ_512M;
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break;
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default:
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pr_err("unsupported DRAM size 0x%08lx (per 16bit)\n", size);
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return -EINVAL;
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}
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writel(0x66bb0f17, dramcont + UMC_CMDCTLA);
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writel(0x18c6aa44, dramcont + UMC_CMDCTLB);
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writel(umc_spcctla[dram_size], dramcont + UMC_SPCCTLA);
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writel(0x00ff0008, dramcont + UMC_SPCCTLB);
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writel(0x000c00ae, dramcont + UMC_RDATACTL_D0);
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writel(0x000c00ae, dramcont + UMC_RDATACTL_D1);
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writel(0x04060802, dramcont + UMC_WDATACTL_D0);
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writel(0x04060802, dramcont + UMC_WDATACTL_D1);
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writel(0x04a02000, dramcont + UMC_DATASET);
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writel(0x66bb0f17, dc_base + UMC_CMDCTLA);
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writel(0x18c6aa44, dc_base + UMC_CMDCTLB);
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writel(umc_spcctla[size_e], dc_base + UMC_SPCCTLA);
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writel(0x00ff0008, dc_base + UMC_SPCCTLB);
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writel(0x000c00ae, dc_base + UMC_RDATACTL_D0);
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writel(0x000c00ae, dc_base + UMC_RDATACTL_D1);
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writel(0x04060802, dc_base + UMC_WDATACTL_D0);
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writel(0x04060802, dc_base + UMC_WDATACTL_D1);
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writel(0x04a02000, dc_base + UMC_DATASET);
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writel(0x00000000, ca_base + 0x2300);
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writel(0x00400020, dramcont + UMC_DCCGCTL);
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writel(0x0000000f, dramcont + 0x7000);
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writel(0x0000000f, dramcont + 0x8000);
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writel(0x000000c3, dramcont + 0x8004);
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writel(0x00000071, dramcont + 0x8008);
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writel(0x00000004, dramcont + UMC_FLOWCTLG);
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writel(0x00000000, dramcont + 0x0060);
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writel(0x00400020, dc_base + UMC_DCCGCTL);
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writel(0x0000000f, dc_base + 0x7000);
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writel(0x0000000f, dc_base + 0x8000);
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writel(0x000000c3, dc_base + 0x8004);
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writel(0x00000071, dc_base + 0x8008);
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writel(0x00000004, dc_base + UMC_FLOWCTLG);
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writel(0x00000000, dc_base + 0x0060);
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writel(0x80000201, ca_base + 0xc20);
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writel(0x0801e01e, dramcont + UMC_FLOWCTLA);
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writel(0x00200000, dramcont + UMC_FLOWCTLB);
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writel(0x00004444, dramcont + UMC_FLOWCTLC);
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writel(0x200a0a00, dramcont + UMC_SPCSETB);
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writel(0x00010000, dramcont + UMC_SPCSETD);
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writel(0x80000020, dramcont + UMC_DFICUPDCTLA);
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writel(0x0801e01e, dc_base + UMC_FLOWCTLA);
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writel(0x00200000, dc_base + UMC_FLOWCTLB);
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writel(0x00004444, dc_base + UMC_FLOWCTLC);
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writel(0x200a0a00, dc_base + UMC_SPCSETB);
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writel(0x00010000, dc_base + UMC_SPCSETD);
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writel(0x80000020, dc_base + UMC_DFICUPDCTLA);
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return 0;
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}
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@ -79,7 +79,7 @@ static void umc_start_ssif(void __iomem *ssif_base)
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writel(0x00000001, ssif_base + UMC_DMDRST);
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}
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static int umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base,
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static int umc_dramcont_init(void __iomem *dc_base, void __iomem *ca_base,
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int freq, unsigned long size, bool ddr3plus)
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{
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enum dram_freq freq_e;
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@ -115,30 +115,30 @@ static int umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base,
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}
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writel((ddr3plus ? umc_cmdctla_plus : umc_cmdctla)[freq_e],
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dramcont + UMC_CMDCTLA);
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dc_base + UMC_CMDCTLA);
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writel((ddr3plus ? umc_cmdctlb_plus : umc_cmdctlb)[freq_e],
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dramcont + UMC_CMDCTLB);
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writel(umc_spcctla[freq_e][size_e], dramcont + UMC_SPCCTLA);
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writel(umc_spcctlb[freq_e], dramcont + UMC_SPCCTLB);
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writel(umc_rdatactl[freq_e], dramcont + UMC_RDATACTL_D0);
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writel(0x04060806, dramcont + UMC_WDATACTL_D0);
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writel(0x04a02000, dramcont + UMC_DATASET);
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dc_base + UMC_CMDCTLB);
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writel(umc_spcctla[freq_e][size_e], dc_base + UMC_SPCCTLA);
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writel(umc_spcctlb[freq_e], dc_base + UMC_SPCCTLB);
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writel(umc_rdatactl[freq_e], dc_base + UMC_RDATACTL_D0);
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writel(0x04060806, dc_base + UMC_WDATACTL_D0);
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writel(0x04a02000, dc_base + UMC_DATASET);
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writel(0x00000000, ca_base + 0x2300);
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writel(0x00400020, dramcont + UMC_DCCGCTL);
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writel(0x00000003, dramcont + 0x7000);
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writel(0x0000004f, dramcont + 0x8000);
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writel(0x000000c3, dramcont + 0x8004);
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writel(0x00000077, dramcont + 0x8008);
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writel(0x0000003b, dramcont + UMC_DICGCTLA);
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writel(0x020a0808, dramcont + UMC_DICGCTLB);
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writel(0x00000004, dramcont + UMC_FLOWCTLG);
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writel(0x00400020, dc_base + UMC_DCCGCTL);
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writel(0x00000003, dc_base + 0x7000);
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writel(0x0000004f, dc_base + 0x8000);
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writel(0x000000c3, dc_base + 0x8004);
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writel(0x00000077, dc_base + 0x8008);
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writel(0x0000003b, dc_base + UMC_DICGCTLA);
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writel(0x020a0808, dc_base + UMC_DICGCTLB);
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writel(0x00000004, dc_base + UMC_FLOWCTLG);
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writel(0x80000201, ca_base + 0xc20);
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writel(0x0801e01e, dramcont + UMC_FLOWCTLA);
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writel(0x00200000, dramcont + UMC_FLOWCTLB);
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writel(0x00004444, dramcont + UMC_FLOWCTLC);
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writel(0x200a0a00, dramcont + UMC_SPCSETB);
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writel(0x00000000, dramcont + UMC_SPCSETD);
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writel(0x00000520, dramcont + UMC_DFICUPDCTLA);
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writel(0x0801e01e, dc_base + UMC_FLOWCTLA);
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writel(0x00200000, dc_base + UMC_FLOWCTLB);
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writel(0x00004444, dc_base + UMC_FLOWCTLC);
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writel(0x200a0a00, dc_base + UMC_SPCSETB);
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writel(0x00000000, dc_base + UMC_SPCSETD);
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writel(0x00000520, dc_base + UMC_DFICUPDCTLA);
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return 0;
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}
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@ -404,12 +404,12 @@ static int ddrphy_training(void __iomem *phy_base)
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}
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/* UMC */
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static void umc_set_system_latency(void __iomem *umc_dc_base, int phy_latency)
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static void umc_set_system_latency(void __iomem *dc_base, int phy_latency)
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{
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u32 val;
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int latency;
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val = readl(umc_dc_base + UMC_RDATACTL_D0);
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val = readl(dc_base + UMC_RDATACTL_D0);
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latency = (val & UMC_RDATACTL_RADLTY_MASK) >> UMC_RDATACTL_RADLTY_SHIFT;
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latency += (val & UMC_RDATACTL_RAD2LTY_MASK) >>
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UMC_RDATACTL_RAD2LTY_SHIFT;
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@ -427,18 +427,18 @@ static void umc_set_system_latency(void __iomem *umc_dc_base, int phy_latency)
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val |= latency << UMC_RDATACTL_RADLTY_SHIFT;
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}
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writel(val, umc_dc_base + UMC_RDATACTL_D0);
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writel(val, umc_dc_base + UMC_RDATACTL_D1);
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writel(val, dc_base + UMC_RDATACTL_D0);
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writel(val, dc_base + UMC_RDATACTL_D1);
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readl(umc_dc_base + UMC_RDATACTL_D1); /* relax */
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readl(dc_base + UMC_RDATACTL_D1); /* relax */
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}
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/* enable/disable auto refresh */
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void umc_refresh_ctrl(void __iomem *umc_dc_base, int enable)
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void umc_refresh_ctrl(void __iomem *dc_base, int enable)
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{
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u32 tmp;
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tmp = readl(umc_dc_base + UMC_SPCSETB);
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tmp = readl(dc_base + UMC_SPCSETB);
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tmp &= ~UMC_SPCSETB_AREFMD_MASK;
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if (enable)
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@ -446,7 +446,7 @@ void umc_refresh_ctrl(void __iomem *umc_dc_base, int enable)
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else
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tmp |= UMC_SPCSETB_AREFMD_REG;
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writel(tmp, umc_dc_base + UMC_SPCSETB);
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writel(tmp, dc_base + UMC_SPCSETB);
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udelay(1);
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}
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@ -458,7 +458,7 @@ static void umc_ud_init(void __iomem *umc_base, int ch)
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writel(0x00000033, umc_base + UMC_PAIR1DOFF_D0);
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}
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static int umc_dc_init(void __iomem *umc_dc_base, enum dram_freq freq,
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static int umc_dc_init(void __iomem *dc_base, enum dram_freq freq,
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unsigned long size, int width, int ch)
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{
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enum dram_size size_e;
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@ -480,14 +480,13 @@ static int umc_dc_init(void __iomem *umc_dc_base, enum dram_freq freq,
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return -EINVAL;
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}
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writel(umc_cmdctla[freq], umc_dc_base + UMC_CMDCTLA);
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writel(umc_cmdctla[freq], dc_base + UMC_CMDCTLA);
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writel(ch == 2 ? umc_cmdctlb_ch2[freq] : umc_cmdctlb_ch01[freq],
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umc_dc_base + UMC_CMDCTLB);
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dc_base + UMC_CMDCTLB);
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writel(umc_spcctla[freq][size_e],
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umc_dc_base + UMC_SPCCTLA);
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writel(umc_spcctlb[freq], umc_dc_base + UMC_SPCCTLB);
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writel(umc_spcctla[freq][size_e], dc_base + UMC_SPCCTLA);
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writel(umc_spcctlb[freq], dc_base + UMC_SPCCTLB);
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val = 0x000e000e;
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latency = 12;
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@ -502,38 +501,38 @@ static int umc_dc_init(void __iomem *umc_dc_base, enum dram_freq freq,
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val |= latency << UMC_RDATACTL_RADLTY_SHIFT;
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}
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writel(val, umc_dc_base + UMC_RDATACTL_D0);
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writel(val, dc_base + UMC_RDATACTL_D0);
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if (width >= 32)
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writel(val, umc_dc_base + UMC_RDATACTL_D1);
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writel(val, dc_base + UMC_RDATACTL_D1);
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writel(0x04060A02, umc_dc_base + UMC_WDATACTL_D0);
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writel(0x04060A02, dc_base + UMC_WDATACTL_D0);
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if (width >= 32)
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writel(0x04060A02, umc_dc_base + UMC_WDATACTL_D1);
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writel(0x04000000, umc_dc_base + UMC_DATASET);
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writel(0x00400020, umc_dc_base + UMC_DCCGCTL);
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writel(0x00000084, umc_dc_base + UMC_FLOWCTLG);
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writel(0x00000000, umc_dc_base + UMC_ACSSETA);
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writel(0x04060A02, dc_base + UMC_WDATACTL_D1);
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writel(0x04000000, dc_base + UMC_DATASET);
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writel(0x00400020, dc_base + UMC_DCCGCTL);
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writel(0x00000084, dc_base + UMC_FLOWCTLG);
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writel(0x00000000, dc_base + UMC_ACSSETA);
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writel(ch == 2 ? umc_flowctla_ch2[freq] : umc_flowctla_ch01[freq],
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umc_dc_base + UMC_FLOWCTLA);
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dc_base + UMC_FLOWCTLA);
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writel(0x00004400, umc_dc_base + UMC_FLOWCTLC);
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writel(0x200A0A00, umc_dc_base + UMC_SPCSETB);
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writel(0x00000520, umc_dc_base + UMC_DFICUPDCTLA);
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writel(0x0000000D, umc_dc_base + UMC_RESPCTL);
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writel(0x00004400, dc_base + UMC_FLOWCTLC);
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writel(0x200A0A00, dc_base + UMC_SPCSETB);
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writel(0x00000520, dc_base + UMC_DFICUPDCTLA);
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writel(0x0000000D, dc_base + UMC_RESPCTL);
|
||||
|
||||
if (ch != 2) {
|
||||
writel(0x00202000, umc_dc_base + UMC_FLOWCTLB);
|
||||
writel(0xFDBFFFFF, umc_dc_base + UMC_FLOWCTLOB0);
|
||||
writel(0xFFFFFFFF, umc_dc_base + UMC_FLOWCTLOB1);
|
||||
writel(0x00080700, umc_dc_base + UMC_BSICMAPSET);
|
||||
writel(0x00202000, dc_base + UMC_FLOWCTLB);
|
||||
writel(0xFDBFFFFF, dc_base + UMC_FLOWCTLOB0);
|
||||
writel(0xFFFFFFFF, dc_base + UMC_FLOWCTLOB1);
|
||||
writel(0x00080700, dc_base + UMC_BSICMAPSET);
|
||||
} else {
|
||||
writel(0x00200000, umc_dc_base + UMC_FLOWCTLB);
|
||||
writel(0x00000000, umc_dc_base + UMC_BSICMAPSET);
|
||||
writel(0x00200000, dc_base + UMC_FLOWCTLB);
|
||||
writel(0x00000000, dc_base + UMC_BSICMAPSET);
|
||||
}
|
||||
|
||||
writel(0x00000000, umc_dc_base + UMC_ERRMASKA);
|
||||
writel(0x00000000, umc_dc_base + UMC_ERRMASKB);
|
||||
writel(0x00000000, dc_base + UMC_ERRMASKA);
|
||||
writel(0x00000000, dc_base + UMC_ERRMASKB);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -541,17 +540,17 @@ static int umc_dc_init(void __iomem *umc_dc_base, enum dram_freq freq,
|
|||
static int umc_ch_init(void __iomem *umc_ch_base, enum dram_freq freq,
|
||||
unsigned long size, unsigned int width, int ch)
|
||||
{
|
||||
void __iomem *umc_dc_base = umc_ch_base + 0x00011000;
|
||||
void __iomem *dc_base = umc_ch_base + 0x00011000;
|
||||
void __iomem *phy_base = umc_ch_base + 0x00030000;
|
||||
int ret;
|
||||
|
||||
writel(0x00000002, umc_dc_base + UMC_INITSET);
|
||||
while (readl(umc_dc_base + UMC_INITSTAT) & BIT(2))
|
||||
writel(0x00000002, dc_base + UMC_INITSET);
|
||||
while (readl(dc_base + UMC_INITSTAT) & BIT(2))
|
||||
cpu_relax();
|
||||
|
||||
/* deassert PHY reset signals */
|
||||
writel(UMC_DIOCTLA_CTL_NRST | UMC_DIOCTLA_CFG_NRST,
|
||||
umc_dc_base + UMC_DIOCTLA);
|
||||
dc_base + UMC_DIOCTLA);
|
||||
|
||||
ddrphy_init(phy_base, freq, width, ch);
|
||||
|
||||
|
|
@ -563,7 +562,7 @@ static int umc_ch_init(void __iomem *umc_ch_base, enum dram_freq freq,
|
|||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = umc_dc_init(umc_dc_base, freq, size, width, ch);
|
||||
ret = umc_dc_init(dc_base, freq, size, width, ch);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
|
|
@ -576,15 +575,15 @@ static int umc_ch_init(void __iomem *umc_ch_base, enum dram_freq freq,
|
|||
udelay(1);
|
||||
|
||||
/* match the system latency between UMC and PHY */
|
||||
umc_set_system_latency(umc_dc_base,
|
||||
umc_set_system_latency(dc_base,
|
||||
ddrphy_get_system_latency(phy_base, width));
|
||||
|
||||
udelay(1);
|
||||
|
||||
/* stop auto refresh before clearing FIFO in PHY */
|
||||
umc_refresh_ctrl(umc_dc_base, 0);
|
||||
umc_refresh_ctrl(dc_base, 0);
|
||||
ddrphy_fifo_reset(phy_base);
|
||||
umc_refresh_ctrl(umc_dc_base, 1);
|
||||
umc_refresh_ctrl(dc_base, 1);
|
||||
|
||||
udelay(10);
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue