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tegra2: Add more clock functions

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This adds most of the clock functions required by board and driver code:

-query and adjust peripheral clocks
-query and adjust PLLs
-reset and enable control

These functions are plumbed in as required.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Tom Warren <twarren@nvidia.com>
This commit is contained in:
Simon Glass 2011-09-21 12:40:04 +00:00 • committed by Albert ARIBAUD
parent 3e00dbdf24
commit 4ed59e70e4
7 changed files with 999 additions and 215 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

3
arch/arm/cpu/armv7/tegra2/ap20.c
View file

@ -189,7 +189,6 @@ static void reset_A9_cpu(int reset)
static void clock_enable_coresight(int enable)
{
struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
u32 rst, src;
clock_set_enable(PERIPH_ID_CORESIGHT, enable);
@ -203,7 +202,7 @@ static void clock_enable_coresight(int enable)
* (bits 7:0), so 00000001b == 1.5 (n+1 + .5)
*/
src = CLK_DIVIDER(NVBL_PLLP_KHZ, 144000);
writel(src, &clkrst->crc_clk_src_csite);
clock_ll_set_source_divisor(PERIPH_ID_CSI, 0, src);
/* Unlock the CPU CoreSight interfaces */
rst = 0xC5ACCE55;

821
arch/arm/cpu/armv7/tegra2/clock.c
View file

@ -27,6 +27,371 @@
#include <asm/arch/timer.h>
#include <asm/arch/tegra2.h>
#include <common.h>
#include <div64.h>
/*
* This is our record of the current clock rate of each clock. We don't
* fill all of these in since we are only really interested in clocks which
* we use as parents.
*/
static unsigned pll_rate[CLOCK_ID_COUNT];
/*
* The oscillator frequency is fixed to one of four set values. Based on this
* the other clocks are set up appropriately.
*/
static unsigned osc_freq[CLOCK_OSC_FREQ_COUNT] = {
13000000,
19200000,
12000000,
26000000,
};
/*
* Clock types that we can use as a source. The Tegra2 has muxes for the
* peripheral clocks, and in most cases there are four options for the clock
* source. This gives us a clock 'type' and exploits what commonality exists
* in the device.
*
* Letters are obvious, except for T which means CLK_M, and S which means the
* clock derived from 32KHz. Beware that CLK_M (also called OSC in the
* datasheet) and PLL_M are different things. The former is the basic
* clock supplied to the SOC from an external oscillator. The latter is the
* memory clock PLL.
*
* See definitions in clock_id in the header file.
*/
enum clock_type_id {
CLOCK_TYPE_AXPT, /* PLL_A, PLL_X, PLL_P, CLK_M */
CLOCK_TYPE_MCPA, /* and so on */
CLOCK_TYPE_MCPT,
CLOCK_TYPE_PCM,
CLOCK_TYPE_PCMT,
CLOCK_TYPE_PCXTS,
CLOCK_TYPE_PDCT,
CLOCK_TYPE_COUNT,
CLOCK_TYPE_NONE = -1, /* invalid clock type */
};
/* return 1 if a peripheral ID is in range */
#define clock_type_id_isvalid(id) ((id) >= 0 && \
(id) < CLOCK_TYPE_COUNT)
char pllp_valid = 1; /* PLLP is set up correctly */
enum {
CLOCK_MAX_MUX = 4 /* number of source options for each clock */
};
/*
* Clock source mux for each clock type. This just converts our enum into
* a list of mux sources for use by the code. Note that CLOCK_TYPE_PCXTS
* is special as it has 5 sources. Since it also has a different number of
* bits in its register for the source, we just handle it with a special
* case in the code.
*/
#define CLK(x) CLOCK_ID_ ## x
static enum clock_id clock_source[CLOCK_TYPE_COUNT][CLOCK_MAX_MUX] = {
{ CLK(AUDIO), CLK(XCPU), CLK(PERIPH), CLK(OSC) },
{ CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(AUDIO) },
{ CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(OSC) },
{ CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(NONE) },
{ CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC) },
{ CLK(PERIPH), CLK(CGENERAL), CLK(XCPU), CLK(OSC) },
{ CLK(PERIPH), CLK(DISPLAY), CLK(CGENERAL), CLK(OSC) },
};
/*
* Clock peripheral IDs which sadly don't match up with PERIPH_ID. This is
* not in the header file since it is for purely internal use - we want
* callers to use the PERIPH_ID for all access to peripheral clocks to avoid
* confusion bewteen PERIPH_ID_... and PERIPHC_...
*
* We don't call this CLOCK_PERIPH_ID or PERIPH_CLOCK_ID as it would just be
* confusing.
*
* Note to SOC vendors: perhaps define a unified numbering for peripherals and
* use it for reset, clock enable, clock source/divider and even pinmuxing
* if you can.
*/
enum periphc_internal_id {
/* 0x00 */
PERIPHC_I2S1,
PERIPHC_I2S2,
PERIPHC_SPDIF_OUT,
PERIPHC_SPDIF_IN,
PERIPHC_PWM,
PERIPHC_SPI1,
PERIPHC_SPI2,
PERIPHC_SPI3,
/* 0x08 */
PERIPHC_XIO,
PERIPHC_I2C1,
PERIPHC_DVC_I2C,
PERIPHC_TWC,
PERIPHC_0c,
PERIPHC_10, /* PERIPHC_SPI1, what is this really? */
PERIPHC_DISP1,
PERIPHC_DISP2,
/* 0x10 */
PERIPHC_CVE,
PERIPHC_IDE0,
PERIPHC_VI,
PERIPHC_1c,
PERIPHC_SDMMC1,
PERIPHC_SDMMC2,
PERIPHC_G3D,
PERIPHC_G2D,
/* 0x18 */
PERIPHC_NDFLASH,
PERIPHC_SDMMC4,
PERIPHC_VFIR,
PERIPHC_EPP,
PERIPHC_MPE,
PERIPHC_MIPI,
PERIPHC_UART1,
PERIPHC_UART2,
/* 0x20 */
PERIPHC_HOST1X,
PERIPHC_21,
PERIPHC_TVO,
PERIPHC_HDMI,
PERIPHC_24,
PERIPHC_TVDAC,
PERIPHC_I2C2,
PERIPHC_EMC,
/* 0x28 */
PERIPHC_UART3,
PERIPHC_29,
PERIPHC_VI_SENSOR,
PERIPHC_2b,
PERIPHC_2c,
PERIPHC_SPI4,
PERIPHC_I2C3,
PERIPHC_SDMMC3,
/* 0x30 */
PERIPHC_UART4,
PERIPHC_UART5,
PERIPHC_VDE,
PERIPHC_OWR,
PERIPHC_NOR,
PERIPHC_CSITE,
PERIPHC_COUNT,
PERIPHC_NONE = -1,
};
/* return 1 if a periphc_internal_id is in range */
#define periphc_internal_id_isvalid(id) ((id) >= 0 && \
(id) < PERIPHC_COUNT)
/*
* Clock type for each peripheral clock source. We put the name in each
* record just so it is easy to match things up
*/
#define TYPE(name, type) type
static enum clock_type_id clock_periph_type[PERIPHC_COUNT] = {
/* 0x00 */
TYPE(PERIPHC_I2S1, CLOCK_TYPE_AXPT),
TYPE(PERIPHC_I2S2, CLOCK_TYPE_AXPT),
TYPE(PERIPHC_SPDIF_OUT, CLOCK_TYPE_AXPT),
TYPE(PERIPHC_SPDIF_IN, CLOCK_TYPE_PCM),
TYPE(PERIPHC_PWM, CLOCK_TYPE_PCXTS),
TYPE(PERIPHC_SPI1, CLOCK_TYPE_PCMT),
TYPE(PERIPHC_SPI22, CLOCK_TYPE_PCMT),
TYPE(PERIPHC_SPI3, CLOCK_TYPE_PCMT),
/* 0x08 */
TYPE(PERIPHC_XIO, CLOCK_TYPE_PCMT),
TYPE(PERIPHC_I2C1, CLOCK_TYPE_PCMT),
TYPE(PERIPHC_DVC_I2C, CLOCK_TYPE_PCMT),
TYPE(PERIPHC_TWC, CLOCK_TYPE_PCMT),
TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
TYPE(PERIPHC_SPI1, CLOCK_TYPE_PCMT),
TYPE(PERIPHC_DISP1, CLOCK_TYPE_PDCT),
TYPE(PERIPHC_DISP2, CLOCK_TYPE_PDCT),
/* 0x10 */
TYPE(PERIPHC_CVE, CLOCK_TYPE_PDCT),
TYPE(PERIPHC_IDE0, CLOCK_TYPE_PCMT),
TYPE(PERIPHC_VI, CLOCK_TYPE_MCPA),
TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
TYPE(PERIPHC_SDMMC1, CLOCK_TYPE_PCMT),
TYPE(PERIPHC_SDMMC2, CLOCK_TYPE_PCMT),
TYPE(PERIPHC_G3D, CLOCK_TYPE_MCPA),
TYPE(PERIPHC_G2D, CLOCK_TYPE_MCPA),
/* 0x18 */
TYPE(PERIPHC_NDFLASH, CLOCK_TYPE_PCMT),
TYPE(PERIPHC_SDMMC4, CLOCK_TYPE_PCMT),
TYPE(PERIPHC_VFIR, CLOCK_TYPE_PCMT),
TYPE(PERIPHC_EPP, CLOCK_TYPE_MCPA),
TYPE(PERIPHC_MPE, CLOCK_TYPE_MCPA),
TYPE(PERIPHC_MIPI, CLOCK_TYPE_PCMT),
TYPE(PERIPHC_UART1, CLOCK_TYPE_PCMT),
TYPE(PERIPHC_UART2, CLOCK_TYPE_PCMT),
/* 0x20 */
TYPE(PERIPHC_HOST1X, CLOCK_TYPE_MCPA),
TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
TYPE(PERIPHC_TVO, CLOCK_TYPE_PDCT),
TYPE(PERIPHC_HDMI, CLOCK_TYPE_PDCT),
TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
TYPE(PERIPHC_TVDAC, CLOCK_TYPE_PDCT),
TYPE(PERIPHC_I2C2, CLOCK_TYPE_PCMT),
TYPE(PERIPHC_EMC, CLOCK_TYPE_MCPT),
/* 0x28 */
TYPE(PERIPHC_UART3, CLOCK_TYPE_PCMT),
TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
TYPE(PERIPHC_VI, CLOCK_TYPE_MCPA),
TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
TYPE(PERIPHC_SPI4, CLOCK_TYPE_PCMT),
TYPE(PERIPHC_I2C3, CLOCK_TYPE_PCMT),
TYPE(PERIPHC_SDMMC3, CLOCK_TYPE_PCMT),
/* 0x30 */
TYPE(PERIPHC_UART4, CLOCK_TYPE_PCMT),
TYPE(PERIPHC_UART5, CLOCK_TYPE_PCMT),
TYPE(PERIPHC_VDE, CLOCK_TYPE_PCMT),
TYPE(PERIPHC_OWR, CLOCK_TYPE_PCMT),
TYPE(PERIPHC_NOR, CLOCK_TYPE_PCMT),
TYPE(PERIPHC_CSITE, CLOCK_TYPE_PCMT),
};
/*
* This array translates a periph_id to a periphc_internal_id
*
* Not present/matched up:
* uint vi_sensor; _VI_SENSOR_0, 0x1A8
* SPDIF - which is both 0x08 and 0x0c
*
*/
#define NONE(name) (-1)
#define OFFSET(name, value) PERIPHC_ ## name
static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = {
/* Low word: 31:0 */
NONE(CPU),
NONE(RESERVED1),
NONE(RESERVED2),
NONE(AC97),
NONE(RTC),
NONE(TMR),
PERIPHC_UART1,
PERIPHC_UART2, /* and vfir 0x68 */
/* 0x08 */
NONE(GPIO),
PERIPHC_SDMMC2,
NONE(SPDIF), /* 0x08 and 0x0c, unclear which to use */
PERIPHC_I2S1,
PERIPHC_I2C1,
PERIPHC_NDFLASH,
PERIPHC_SDMMC1,
PERIPHC_SDMMC4,
/* 0x10 */
PERIPHC_TWC,
PERIPHC_PWM,
PERIPHC_I2S2,
PERIPHC_EPP,
PERIPHC_VI,
PERIPHC_G2D,
NONE(USBD),
NONE(ISP),
/* 0x18 */
PERIPHC_G3D,
PERIPHC_IDE0,
PERIPHC_DISP2,
PERIPHC_DISP1,
PERIPHC_HOST1X,
NONE(VCP),
NONE(RESERVED30),
NONE(CACHE2),
/* Middle word: 63:32 */
NONE(MEM),
NONE(AHBDMA),
NONE(APBDMA),
NONE(RESERVED35),
NONE(KBC),
NONE(STAT_MON),
NONE(PMC),
NONE(FUSE),
/* 0x28 */
NONE(KFUSE),
NONE(SBC1), /* SBC1, 0x34, is this SPI1? */
PERIPHC_NOR,
PERIPHC_SPI1,
PERIPHC_SPI2,
PERIPHC_XIO,
PERIPHC_SPI3,
PERIPHC_DVC_I2C,
/* 0x30 */
NONE(DSI),
PERIPHC_TVO, /* also CVE 0x40 */
PERIPHC_MIPI,
PERIPHC_HDMI,
PERIPHC_CSITE,
PERIPHC_TVDAC,
PERIPHC_I2C2,
PERIPHC_UART3,
/* 0x38 */
NONE(RESERVED56),
PERIPHC_EMC,
NONE(USB2),
NONE(USB3),
PERIPHC_MPE,
PERIPHC_VDE,
NONE(BSEA),
NONE(BSEV),
/* Upper word 95:64 */
NONE(SPEEDO),
PERIPHC_UART4,
PERIPHC_UART5,
PERIPHC_I2C3,
PERIPHC_SPI4,
PERIPHC_SDMMC3,
NONE(PCIE),
PERIPHC_OWR,
/* 0x48 */
NONE(AFI),
NONE(CORESIGHT),
NONE(RESERVED74),
NONE(AVPUCQ),
NONE(RESERVED76),
NONE(RESERVED77),
NONE(RESERVED78),
NONE(RESERVED79),
/* 0x50 */
NONE(RESERVED80),
NONE(RESERVED81),
NONE(RESERVED82),
NONE(RESERVED83),
NONE(IRAMA),
NONE(IRAMB),
NONE(IRAMC),
NONE(IRAMD),
/* 0x58 */
NONE(CRAM2),
};
/*
* Get the oscillator frequency, from the corresponding hardware configuration
@ -42,16 +407,21 @@ enum clock_osc_freq clock_get_osc_freq(void)
return (reg & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT;
}
unsigned long clock_start_pll(enum clock_id clkid, u32 divm, u32 divn,
u32 divp, u32 cpcon, u32 lfcon)
/* Returns a pointer to the registers of the given pll */
static struct clk_pll *get_pll(enum clock_id clkid)
{
struct clk_rst_ctlr *clkrst =
(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
u32 data;
struct clk_pll *pll;
assert(clock_id_isvalid(clkid));
pll = &clkrst->crc_pll[clkid];
return &clkrst->crc_pll[clkid];
}
unsigned long clock_start_pll(enum clock_id clkid, u32 divm, u32 divn,
u32 divp, u32 cpcon, u32 lfcon)
{
struct clk_pll *pll = get_pll(clkid);
u32 data;
/*
* We cheat by treating all PLL (except PLLU) in the same fashion.
@ -76,6 +446,294 @@ unsigned long clock_start_pll(enum clock_id clkid, u32 divm, u32 divn,
return timer_get_us() + CLOCK_PLL_STABLE_DELAY_US;
}
/* return 1 if a peripheral ID is in range and valid */
static int clock_periph_id_isvalid(enum periph_id id)
{
if (id < PERIPH_ID_FIRST || id >= PERIPH_ID_COUNT)
printf("Peripheral id %d out of range\n", id);
else {
switch (id) {
case PERIPH_ID_RESERVED1:
case PERIPH_ID_RESERVED2:
case PERIPH_ID_RESERVED30:
case PERIPH_ID_RESERVED35:
case PERIPH_ID_RESERVED56:
case PERIPH_ID_RESERVED74:
case PERIPH_ID_RESERVED76:
case PERIPH_ID_RESERVED77:
case PERIPH_ID_RESERVED78:
case PERIPH_ID_RESERVED79:
case PERIPH_ID_RESERVED80:
case PERIPH_ID_RESERVED81:
case PERIPH_ID_RESERVED82:
case PERIPH_ID_RESERVED83:
printf("Peripheral id %d is reserved\n", id);
break;
default:
return 1;
}
}
return 0;
}
/* Returns a pointer to the clock source register for a peripheral */
static u32 *get_periph_source_reg(enum periph_id periph_id)
{
struct clk_rst_ctlr *clkrst =
(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
enum periphc_internal_id internal_id;
assert(clock_periph_id_isvalid(periph_id));
internal_id = periph_id_to_internal_id[periph_id];
assert(internal_id != -1);
return &clkrst->crc_clk_src[internal_id];
}
void clock_ll_set_source_divisor(enum periph_id periph_id, unsigned source,
unsigned divisor)
{
u32 *reg = get_periph_source_reg(periph_id);
u32 value;
value = readl(reg);
value &= ~OUT_CLK_SOURCE_MASK;
value |= source << OUT_CLK_SOURCE_SHIFT;
value &= ~OUT_CLK_DIVISOR_MASK;
value |= divisor << OUT_CLK_DIVISOR_SHIFT;
writel(value, reg);
}
void clock_ll_set_source(enum periph_id periph_id, unsigned source)
{
u32 *reg = get_periph_source_reg(periph_id);
clrsetbits_le32(reg, OUT_CLK_SOURCE_MASK,
source << OUT_CLK_SOURCE_SHIFT);
}
/**
* Given the parent's rate and the required rate for the children, this works
* out the peripheral clock divider to use, in 7.1 binary format.
*
* @param parent_rate clock rate of parent clock in Hz
* @param rate required clock rate for this clock
* @return divider which should be used
*/
static int clk_div7_1_get_divider(unsigned long parent_rate,
unsigned long rate)
{
u64 divider = parent_rate * 2;
divider += rate - 1;
do_div(divider, rate);
if ((s64)divider - 2 < 0)
return 0;
if ((s64)divider - 2 > 255)
return -1;
return divider - 2;
}
/**
* Given the parent's rate and the divider in 7.1 format, this works out the
* resulting peripheral clock rate.
*
* @param parent_rate clock rate of parent clock in Hz
* @param divider which should be used in 7.1 format
* @return effective clock rate of peripheral
*/
static unsigned long get_rate_from_divider(unsigned long parent_rate,
int divider)
{
u64 rate;
rate = (u64)parent_rate * 2;
do_div(rate, divider + 2);
return rate;
}
unsigned long clock_get_periph_rate(enum periph_id periph_id,
enum clock_id parent)
{
u32 *reg = get_periph_source_reg(periph_id);
return get_rate_from_divider(pll_rate[parent],
(readl(reg) & OUT_CLK_DIVISOR_MASK) >> OUT_CLK_DIVISOR_SHIFT);
}
/**
* Find the best available 7.1 format divisor given a parent clock rate and
* required child clock rate. This function assumes that a second-stage
* divisor is available which can divide by powers of 2 from 1 to 256.
*
* @param parent_rate clock rate of parent clock in Hz
* @param rate required clock rate for this clock
* @param extra_div value for the second-stage divisor (not set if this
* function returns -1.
* @return divider which should be used, or -1 if nothing is valid
*
*/
static int find_best_divider(unsigned long parent_rate, unsigned long rate,
int *extra_div)
{
int shift;
int best_divider = -1;
int best_error = rate;
/* try dividers from 1 to 256 and find closest match */
for (shift = 0; shift <= 8 && best_error > 0; shift++) {
unsigned divided_parent = parent_rate >> shift;
int divider = clk_div7_1_get_divider(divided_parent, rate);
unsigned effective_rate = get_rate_from_divider(divided_parent,
divider);
int error = rate - effective_rate;
/* Given a valid divider, look for the lowest error */
if (divider != -1 && error < best_error) {
best_error = error;
*extra_div = 1 << shift;
best_divider = divider;
}
}
/* return what we found - *extra_div will already be set */
return best_divider;
}
/**
* Given a peripheral ID and the required source clock, this returns which
* value should be programmed into the source mux for that peripheral.
*
* There is special code here to handle the one source type with 5 sources.
*
* @param periph_id peripheral to start
* @param source PLL id of required parent clock
* @param mux_bits Set to number of bits in mux register: 2 or 4
* @return mux value (0-4, or -1 if not found)
*/
static int get_periph_clock_source(enum periph_id periph_id,
enum clock_id parent, int *mux_bits)
{
enum clock_type_id type;
enum periphc_internal_id internal_id;
int mux;
assert(clock_periph_id_isvalid(periph_id));
internal_id = periph_id_to_internal_id[periph_id];
assert(periphc_internal_id_isvalid(internal_id));
type = clock_periph_type[internal_id];
assert(clock_type_id_isvalid(type));
/* Special case here for the clock with a 4-bit source mux */
if (type == CLOCK_TYPE_PCXTS)
*mux_bits = 4;
else
*mux_bits = 2;
for (mux = 0; mux < CLOCK_MAX_MUX; mux++)
if (clock_source[type][mux] == parent)
return mux;
/*
* Not found: it might be looking for the 'S' in CLOCK_TYPE_PCXTS
* which is not in our table. If not, then they are asking for a
* source which this peripheral can't access through its mux.
*/
assert(type == CLOCK_TYPE_PCXTS);
assert(parent == CLOCK_ID_SFROM32KHZ);
if (type == CLOCK_TYPE_PCXTS && parent == CLOCK_ID_SFROM32KHZ)
return 4; /* mux value for this clock */
/* if we get here, either us or the caller has made a mistake */
printf("Caller requested bad clock: periph=%d, parent=%d\n", periph_id,
parent);
return -1;
}
/**
* Adjust peripheral PLL to use the given divider and source.
*
* @param periph_id peripheral to adjust
* @param parent Required parent clock (for source mux)
* @param divider Required divider in 7.1 format
* @return 0 if ok, -1 on error (requesting a parent clock which is not valid
* for this peripheral)
*/
static int adjust_periph_pll(enum periph_id periph_id,
enum clock_id parent, unsigned divider)
{
u32 *reg = get_periph_source_reg(periph_id);
unsigned source;
int mux_bits;
clrsetbits_le32(reg, OUT_CLK_DIVISOR_MASK,
divider << OUT_CLK_DIVISOR_SHIFT);
udelay(1);
/* work out the source clock and set it */
source = get_periph_clock_source(periph_id, parent, &mux_bits);
if (source < 0)
return -1;
if (mux_bits == 4) {
clrsetbits_le32(reg, OUT_CLK_SOURCE4_MASK,
source << OUT_CLK_SOURCE4_SHIFT);
} else {
clrsetbits_le32(reg, OUT_CLK_SOURCE_MASK,
source << OUT_CLK_SOURCE_SHIFT);
}
udelay(2);
return 0;
}
unsigned clock_adjust_periph_pll_div(enum periph_id periph_id,
enum clock_id parent, unsigned rate, int *extra_div)
{
unsigned effective_rate;
int divider;
if (extra_div)
divider = find_best_divider(pll_rate[parent], rate, extra_div);
else
divider = clk_div7_1_get_divider(pll_rate[parent], rate);
assert(divider >= 0);
if (adjust_periph_pll(periph_id, parent, divider))
return -1U;
debug("periph %d, rate=%d, reg=%p = %x\n", periph_id, rate,
get_periph_source_reg(periph_id),
readl(get_periph_source_reg(periph_id)));
/* Check what we ended up with. This shouldn't matter though */
effective_rate = clock_get_periph_rate(periph_id, parent);
if (extra_div)
effective_rate /= *extra_div;
if (rate != effective_rate)
debug("Requested clock rate %u not honored (got %u)\n",
rate, effective_rate);
return effective_rate;
}
unsigned clock_start_periph_pll(enum periph_id periph_id,
enum clock_id parent, unsigned rate)
{
unsigned effective_rate;
reset_set_enable(periph_id, 1);
clock_enable(periph_id);
effective_rate = clock_adjust_periph_pll_div(periph_id, parent, rate,
NULL);
reset_set_enable(periph_id, 0);
return effective_rate;
}
void clock_set_enable(enum periph_id periph_id, int enable)
{
struct clk_rst_ctlr *clkrst =
@ -148,3 +806,156 @@ void reset_cmplx_set_enable(int cpu, int which, int reset)
else
writel(mask, &clkrst->crc_cpu_cmplx_clr);
}
unsigned clock_get_rate(enum clock_id clkid)
{
struct clk_pll *pll;
u32 base;
u32 divm;
u64 parent_rate;
u64 rate;
parent_rate = osc_freq[clock_get_osc_freq()];
if (clkid == CLOCK_ID_OSC)
return parent_rate;
pll = get_pll(clkid);
base = readl(&pll->pll_base);
/* Oh for bf_unpack()... */
rate = parent_rate * ((base & PLL_DIVN_MASK) >> PLL_DIVN_SHIFT);
divm = (base & PLL_DIVM_MASK) >> PLL_DIVM_SHIFT;
if (clkid == CLOCK_ID_USB)
divm <<= (base & PLLU_VCO_FREQ_MASK) >> PLLU_VCO_FREQ_SHIFT;
else
divm <<= (base & PLL_DIVP_MASK) >> PLL_DIVP_SHIFT;
do_div(rate, divm);
return rate;
}
/**
* Set the output frequency you want for each PLL clock.
* PLL output frequencies are programmed by setting their N, M and P values.
* The governing equations are:
* VCO = (Fi / m) * n, Fo = VCO / (2^p)
* where Fo is the output frequency from the PLL.
* Example: Set the output frequency to 216Mhz(Fo) with 12Mhz OSC(Fi)
* 216Mhz = ((12Mhz / m) * n) / (2^p) so n=432,m=12,p=1
* Please see Tegra TRM section 5.3 to get the detail for PLL Programming
*
* @param n PLL feedback divider(DIVN)
* @param m PLL input divider(DIVN)
* @param p post divider(DIVP)
* @param cpcon base PLL charge pump(CPCON)
* @return 0 if ok, -1 on error (the requested PLL is incorrect and cannot
* be overriden), 1 if PLL is already correct
*/
static int clock_set_rate(enum clock_id clkid, u32 n, u32 m, u32 p, u32 cpcon)
{
u32 base_reg;
u32 misc_reg;
struct clk_pll *pll;
pll = get_pll(clkid);
base_reg = readl(&pll->pll_base);
/* Set BYPASS, m, n and p to PLL_BASE */
base_reg &= ~PLL_DIVM_MASK;
base_reg |= m << PLL_DIVM_SHIFT;
base_reg &= ~PLL_DIVN_MASK;
base_reg |= n << PLL_DIVN_SHIFT;
base_reg &= ~PLL_DIVP_MASK;
base_reg |= p << PLL_DIVP_SHIFT;
if (clkid == CLOCK_ID_PERIPH) {
/*
* If the PLL is already set up, check that it is correct
* and record this info for clock_verify() to check.
*/
if (base_reg & PLL_BASE_OVRRIDE_MASK) {
base_reg |= PLL_ENABLE_MASK;
if (base_reg != readl(&pll->pll_base))
pllp_valid = 0;
return pllp_valid ? 1 : -1;
}
base_reg |= PLL_BASE_OVRRIDE_MASK;
}
base_reg |= PLL_BYPASS_MASK;
writel(base_reg, &pll->pll_base);
/* Set cpcon to PLL_MISC */
misc_reg = readl(&pll->pll_misc);
misc_reg &= ~PLL_CPCON_MASK;
misc_reg |= cpcon << PLL_CPCON_SHIFT;
writel(misc_reg, &pll->pll_misc);
/* Enable PLL */
base_reg |= PLL_ENABLE_MASK;
writel(base_reg, &pll->pll_base);
/* Disable BYPASS */
base_reg &= ~PLL_BYPASS_MASK;
writel(base_reg, &pll->pll_base);
return 0;
}
int clock_verify(void)
{
struct clk_pll *pll = get_pll(CLOCK_ID_PERIPH);
u32 reg = readl(&pll->pll_base);
if (!pllp_valid) {
printf("Warning: PLLP %x is not correct\n", reg);
return -1;
}
debug("PLLX %x is correct\n", reg);
return 0;
}
void clock_early_init(void)
{
/*
* PLLP output frequency set to 216MHz
* PLLC output frequency set to 600Mhz
*
* TODO: Can we calculate these values instead of hard-coding?
*/
switch (clock_get_osc_freq()) {
case CLOCK_OSC_FREQ_12_0: /* OSC is 12Mhz */
clock_set_rate(CLOCK_ID_PERIPH, 432, 12, 1, 8);
clock_set_rate(CLOCK_ID_CGENERAL, 600, 12, 0, 8);
break;
case CLOCK_OSC_FREQ_26_0: /* OSC is 26Mhz */
clock_set_rate(CLOCK_ID_PERIPH, 432, 26, 1, 8);
clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8);
break;
case CLOCK_OSC_FREQ_13_0:
case CLOCK_OSC_FREQ_19_2:
default:
/*
* These are not supported. It is too early to print a
* message and the UART likely won't work anyway due to the
* oscillator being wrong.
*/
break;
}
}
void clock_init(void)
{
pll_rate[CLOCK_ID_MEMORY] = clock_get_rate(CLOCK_ID_MEMORY);
pll_rate[CLOCK_ID_PERIPH] = clock_get_rate(CLOCK_ID_PERIPH);
pll_rate[CLOCK_ID_CGENERAL] = clock_get_rate(CLOCK_ID_CGENERAL);
pll_rate[CLOCK_ID_OSC] = clock_get_rate(CLOCK_ID_OSC);
pll_rate[CLOCK_ID_SFROM32KHZ] = 32768;
debug("Osc = %d\n", pll_rate[CLOCK_ID_OSC]);
debug("PLLM = %d\n", pll_rate[CLOCK_ID_MEMORY]);
debug("PLLP = %d\n", pll_rate[CLOCK_ID_PERIPH]);
}

84
arch/arm/include/asm/arch-tegra2/clk_rst.h
View file

@ -43,9 +43,12 @@ struct clk_pll_simple {
* structure for which we use clk_pll_simple. The reason for this non-
* othogonal setup is not stated.
*/
#define TEGRA_CLK_PLLS 6
#define TEGRA_CLK_SIMPLE_PLLS 3 /* Number of simple PLLs */
#define TEGRA_CLK_REGS 3 /* Number of clock enable registers */
enum {
TEGRA_CLK_PLLS = 6, /* Number of normal PLLs */
TEGRA_CLK_SIMPLE_PLLS = 3, /* Number of simple PLLs */
TEGRA_CLK_REGS = 3, /* Number of clock enable registers */
TEGRA_CLK_SOURCES = 64, /* Number of peripheral clock sources */
};
/* Clock/Reset Controller (CLK_RST_CONTROLLER_) regs */
struct clk_rst_ctlr {
@ -79,65 +82,10 @@ struct clk_rst_ctlr {
uint crc_reserved10; /* _reserved_10, 0xF8 */
uint crc_reserved11; /* _reserved_11, 0xFC */
uint crc_clk_src_i2s1; /*_I2S1_0, 0x100 */
uint crc_clk_src_i2s2; /*_I2S2_0, 0x104 */
uint crc_clk_src_spdif_out; /*_SPDIF_OUT_0, 0x108 */
uint crc_clk_src_spdif_in; /*_SPDIF_IN_0, 0x10C */
uint crc_clk_src_pwm; /*_PWM_0, 0x110 */
uint crc_clk_src_spi1; /*_SPI1_0, 0x114 */
uint crc_clk_src_sbc2; /*_SBC2_0, 0x118 */
uint crc_clk_src_sbc3; /*_SBC3_0, 0x11C */
uint crc_clk_src_xio; /*_XIO_0, 0x120 */
uint crc_clk_src_i2c1; /*_I2C1_0, 0x124 */
uint crc_clk_src_dvc_i2c; /*_DVC_I2C_0, 0x128 */
uint crc_clk_src_twc; /*_TWC_0, 0x12C */
uint crc_reserved12; /* 0x130 */
uint crc_clk_src_sbc1; /*_SBC1_0, 0x134 */
uint crc_clk_src_disp1; /*_DISP1_0, 0x138 */
uint crc_clk_src_disp2; /*_DISP2_0, 0x13C */
uint crc_clk_src_cve; /*_CVE_0, 0x140 */
uint crc_clk_src_ide; /*_IDE_0, 0x144 */
uint crc_clk_src_vi; /*_VI_0, 0x148 */
uint crc_reserved13; /* 0x14C */
uint crc_clk_src_sdmmc1; /*_SDMMC1_0, 0x150 */
uint crc_clk_src_sdmmc2; /*_SDMMC2_0, 0x154 */
uint crc_clk_src_g3d; /*_G3D_0, 0x158 */
uint crc_clk_src_g2d; /*_G2D_0, 0x15C */
uint crc_clk_src_ndflash; /*_NDFLASH_0, 0x160 */
uint crc_clk_src_sdmmc4; /*_SDMMC4_0, 0x164 */
uint crc_clk_src_vfir; /*_VFIR_0, 0x168 */
uint crc_clk_src_epp; /*_EPP_0, 0x16C */
uint crc_clk_src_mp3; /*_MPE_0, 0x170 */
uint crc_clk_src_mipi; /*_MIPI_0, 0x174 */
uint crc_clk_src_uarta; /*_UARTA_0, 0x178 */
uint crc_clk_src_uartb; /*_UARTB_0, 0x17C */
uint crc_clk_src_host1x; /*_HOST1X_0, 0x180 */
uint crc_reserved14; /* 0x184 */
uint crc_clk_src_tvo; /*_TVO_0, 0x188 */
uint crc_clk_src_hdmi; /*_HDMI_0, 0x18C */
uint crc_reserved15; /* 0x190 */
uint crc_clk_src_tvdac; /*_TVDAC_0, 0x194 */
uint crc_clk_src_i2c2; /*_I2C2_0, 0x198 */
uint crc_clk_src_emc; /*_EMC_0, 0x19C */
uint crc_clk_src_uartc; /*_UARTC_0, 0x1A0 */
uint crc_reserved16; /* 0x1A4 */
uint crc_clk_src_vi_sensor; /*_VI_SENSOR_0, 0x1A8 */
uint crc_reserved17; /* 0x1AC */
uint crc_reserved18; /* 0x1B0 */
uint crc_clk_src_sbc4; /*_SBC4_0, 0x1B4 */
uint crc_clk_src_i2c3; /*_I2C3_0, 0x1B8 */
uint crc_clk_src_sdmmc3; /*_SDMMC3_0, 0x1BC */
uint crc_clk_src_uartd; /*_UARTD_0, 0x1C0 */
uint crc_clk_src_uarte; /*_UARTE_0, 0x1C4 */
uint crc_clk_src_vde; /*_VDE_0, 0x1C8 */
uint crc_clk_src_owr; /*_OWR_0, 0x1CC */
uint crc_clk_src_nor; /*_NOR_0, 0x1D0 */
uint crc_clk_src_csite; /*_CSITE_0, 0x1D4 */
uint crc_reserved19[9]; /* 0x1D8-1F8 */
uint crc_clk_src_osc; /*_OSC_0, 0x1FC */
uint crc_clk_src[TEGRA_CLK_SOURCES]; /*_I2S1_0... 0x100-1fc */
uint crc_reserved20[80]; /* 0x200-33C */
uint crc_cpu_cmplx_set; /* _CPU_CMPLX_SET_0, 0x340 */
uint crc_cpu_cmplx_clr; /* _CPU_CMPLX_CLR_0, 0x344 */
uint crc_cpu_cmplx_set; /* _CPU_CMPLX_SET_0, 0x340 */
uint crc_cpu_cmplx_clr; /* _CPU_CMPLX_CLR_0, 0x344 */
};
/* CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0 */
@ -156,10 +104,13 @@ struct clk_rst_ctlr {
#define PLL_BASE_OVRRIDE_MASK (1U << 28)
#define PLL_DIVP_SHIFT 20
#define PLL_DIVP_MASK (7U << PLL_DIVP_SHIFT)
#define PLL_DIVN_SHIFT 8
#define PLL_DIVN_MASK (0x3ffU << PLL_DIVN_SHIFT)
#define PLL_DIVM_SHIFT 0
#define PLL_DIVM_MASK (0x1f << PLL_DIVM_SHIFT)
/* CLK_RST_CONTROLLER_PLLx_MISC_0 */
#define PLL_CPCON_SHIFT 8
@ -168,9 +119,20 @@ struct clk_rst_ctlr {
#define PLL_LFCON_SHIFT 4
#define PLLU_VCO_FREQ_SHIFT 20
#define PLLU_VCO_FREQ_MASK (1U << PLLU_VCO_FREQ_SHIFT)
/* CLK_RST_CONTROLLER_OSC_CTRL_0 */
#define OSC_FREQ_SHIFT 30
#define OSC_FREQ_MASK (3U << OSC_FREQ_SHIFT)
/* CLK_RST_CONTROLLER_CLK_SOURCE_x_OUT_0 */
#define OUT_CLK_DIVISOR_SHIFT 0
#define OUT_CLK_DIVISOR_MASK (255 << OUT_CLK_DIVISOR_SHIFT)
#define OUT_CLK_SOURCE_SHIFT 30
#define OUT_CLK_SOURCE_MASK (3U << OUT_CLK_SOURCE_SHIFT)
#define OUT_CLK_SOURCE4_SHIFT 28
#define OUT_CLK_SOURCE4_MASK (15U << OUT_CLK_SOURCE4_SHIFT)
#endif /* CLK_RST_H */

108
arch/arm/include/asm/arch-tegra2/clock.h
View file

@ -51,7 +51,12 @@ enum clock_id {
CLOCK_ID_EPCI,
CLOCK_ID_SFROM32KHZ,
CLOCK_ID_COUNT,
/* These are the base clocks (inputs to the Tegra SOC) */
CLOCK_ID_32KHZ,
CLOCK_ID_OSC,
CLOCK_ID_COUNT, /* number of clocks */
CLOCK_ID_NONE = -1,
};
/* The clocks supported by the hardware */
@ -183,10 +188,6 @@ enum periph_id {
/* return 1 if a PLL ID is in range */
#define clock_id_isvalid(id) ((id) >= CLOCK_ID_FIRST && (id) < CLOCK_ID_COUNT)
/* return 1 if a peripheral ID is in range */
#define clock_periph_id_isvalid(id) ((id) >= PERIPH_ID_FIRST && \
(id) < PERIPH_ID_COUNT)
/* PLL stabilization delay in usec */
#define CLOCK_PLL_STABLE_DELAY_US 300
@ -215,6 +216,13 @@ unsigned long clock_start_pll(enum clock_id id, u32 divm, u32 divn,
*/
void clock_enable(enum periph_id clkid);
/*
* Disable a clock
*
* @param id clock id
*/
void clock_disable(enum periph_id clkid);
/*
* Set whether a clock is enabled or disabled.
*
@ -259,4 +267,94 @@ enum crc_reset_id {
*/
void reset_cmplx_set_enable(int cpu, int which, int reset);
/**
* Set the source for a peripheral clock. This plus the divisor sets the
* clock rate. You need to look up the datasheet to see the meaning of the
* source parameter as it changes for each peripheral.
*
* Warning: This function is only for use pre-relocation. Please use
* clock_start_periph_pll() instead.
*
* @param periph_id peripheral to adjust
* @param source source clock (0, 1, 2 or 3)
*/
void clock_ll_set_source(enum periph_id periph_id, unsigned source);
/**
* Set the source and divisor for a peripheral clock. This sets the
* clock rate. You need to look up the datasheet to see the meaning of the
* source parameter as it changes for each peripheral.
*
* Warning: This function is only for use pre-relocation. Please use
* clock_start_periph_pll() instead.
*
* @param periph_id peripheral to adjust
* @param source source clock (0, 1, 2 or 3)
* @param divisor divisor value to use
*/
void clock_ll_set_source_divisor(enum periph_id periph_id, unsigned source,
unsigned divisor);
/**
* Start a peripheral PLL clock at the given rate. This also resets the
* peripheral.
*
* @param periph_id peripheral to start
* @param parent PLL id of required parent clock
* @param rate Required clock rate in Hz
* @return rate selected in Hz, or -1U if something went wrong
*/
unsigned clock_start_periph_pll(enum periph_id periph_id,
enum clock_id parent, unsigned rate);
/**
* Returns the rate of a peripheral clock in Hz. Since the caller almost
* certainly knows the parent clock (having just set it) we require that
* this be passed in so we don't need to work it out.
*
* @param periph_id peripheral to start
* @param parent PLL id of parent clock (used to calculate rate, you
* must know this!)
* @return clock rate of peripheral in Hz
*/
unsigned long clock_get_periph_rate(enum periph_id periph_id,
enum clock_id parent);
/**
* Adjust peripheral PLL clock to the given rate. This does not reset the
* peripheral. If a second stage divisor is not available, pass NULL for
* extra_div. If it is available, then this parameter will return the
* divisor selected (which will be a power of 2 from 1 to 256).
*
* @param periph_id peripheral to start
* @param parent PLL id of required parent clock
* @param rate Required clock rate in Hz
* @param extra_div value for the second-stage divisor (NULL if one is
not available)
* @return rate selected in Hz, or -1U if something went wrong
*/
unsigned clock_adjust_periph_pll_div(enum periph_id periph_id,
enum clock_id parent, unsigned rate, int *extra_div);
/**
* Returns the clock rate of a specified clock, in Hz.
*
* @param parent PLL id of clock to check
* @return rate of clock in Hz
*/
unsigned clock_get_rate(enum clock_id clkid);
/*
* Checks that clocks are valid and prints a warning if not
*
* @return 0 if ok, -1 on error
*/
int clock_verify(void);
/* Initialize the clocks */
void clock_init(void);
/* Initialize the PLLs */
void clock_early_init(void);
#endif

105
board/nvidia/common/board.c
View file

@ -52,62 +52,31 @@ int timer_init(void)
return 0;
}
static void enable_uart(enum periph_id pid)
{
/* Assert UART reset and enable clock */
reset_set_enable(pid, 1);
clock_enable(pid);
clock_ll_set_source(pid, 0); /* UARTx_CLK_SRC = 00, PLLP_OUT0 */
/* wait for 2us */
udelay(2);
/* De-assert reset to UART */
reset_set_enable(pid, 0);
}
/*
* Routine: clock_init_uart
* Description: init the PLL and clock for the UART(s)
*/
static void clock_init_uart(void)
{
struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
struct clk_pll *pll = &clkrst->crc_pll[CLOCK_ID_PERIPH];
u32 reg;
reg = readl(&pll->pll_base);
if (!(reg & PLL_BASE_OVRRIDE_MASK)) {
/* Override pllp setup for 216MHz operation. */
reg = PLL_BYPASS_MASK | PLL_BASE_OVRRIDE_MASK |
(1 << PLL_DIVP_SHIFT) | (0xc << PLL_DIVM_SHIFT);
reg |= (NVRM_PLLP_FIXED_FREQ_KHZ / 500) << PLL_DIVN_SHIFT;
writel(reg, &pll->pll_base);
reg |= PLL_ENABLE_MASK;
writel(reg, &pll->pll_base);
reg &= ~PLL_BYPASS_MASK;
writel(reg, &pll->pll_base);
}
#if defined(CONFIG_TEGRA2_ENABLE_UARTA)
/* Assert UART reset and enable clock */
reset_set_enable(PERIPH_ID_UART1, 1);
clock_enable(PERIPH_ID_UART1);
/* Enable pllp_out0 to UART */
reg = readl(&clkrst->crc_clk_src_uarta);
reg &= 0x3FFFFFFF; /* UARTA_CLK_SRC = 00, PLLP_OUT0 */
writel(reg, &clkrst->crc_clk_src_uarta);
/* wait for 2us */
udelay(2);
/* De-assert reset to UART */
reset_set_enable(PERIPH_ID_UART1, 0);
enable_uart(PERIPH_ID_UART1);
#endif /* CONFIG_TEGRA2_ENABLE_UARTA */
#if defined(CONFIG_TEGRA2_ENABLE_UARTD)
/* Assert UART reset and enable clock */
reset_set_enable(PERIPH_ID_UART4, 1);
clock_enable(PERIPH_ID_UART4);
/* Enable pllp_out0 to UART */
reg = readl(&clkrst->crc_clk_src_uartd);
reg &= 0x3FFFFFFF; /* UARTD_CLK_SRC = 00, PLLP_OUT0 */
writel(reg, &clkrst->crc_clk_src_uartd);
/* wait for 2us */
udelay(2);
/* De-assert reset to UART */
reset_set_enable(PERIPH_ID_UART4, 0);
enable_uart(PERIPH_ID_UART4);
#endif /* CONFIG_TEGRA2_ENABLE_UARTD */
}
@ -144,40 +113,8 @@ static void pin_mux_uart(void)
*/
static void clock_init_mmc(void)
{
struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
u32 reg;
/* Do the SDMMC resets/clock enables */
reset_set_enable(PERIPH_ID_SDMMC4, 1);
clock_enable(PERIPH_ID_SDMMC4);
/* Enable pllp_out0 to SDMMC4 */
reg = readl(&clkrst->crc_clk_src_sdmmc4);
reg &= 0x3FFFFF00; /* SDMMC4_CLK_SRC = 00, PLLP_OUT0 */
reg |= (10 << 1); /* n-1, 11-1 shl 1 */
writel(reg, &clkrst->crc_clk_src_sdmmc4);
/*
* As per the Tegra2 TRM, section 5.3.4:
* 'Wait 2 us for the clock to flush through the pipe/logic'
*/
udelay(2);
reset_set_enable(PERIPH_ID_SDMMC4, 1);
reset_set_enable(PERIPH_ID_SDMMC3, 1);
clock_enable(PERIPH_ID_SDMMC3);
/* Enable pllp_out0 to SDMMC4, set divisor to 11 for 20MHz */
reg = readl(&clkrst->crc_clk_src_sdmmc3);
reg &= 0x3FFFFF00; /* SDMMC3_CLK_SRC = 00, PLLP_OUT0 */
reg |= (10 << 1); /* n-1, 11-1 shl 1 */
writel(reg, &clkrst->crc_clk_src_sdmmc3);
/* wait for 2us */
udelay(2);
reset_set_enable(PERIPH_ID_SDMMC3, 0);
clock_start_periph_pll(PERIPH_ID_SDMMC4, CLOCK_ID_PERIPH, 20000000);
clock_start_periph_pll(PERIPH_ID_SDMMC3, CLOCK_ID_PERIPH, 20000000);
}
/*
@ -226,6 +163,9 @@ static void pin_mux_mmc(void)
*/
int board_init(void)
{
clock_init();
clock_verify();
/* boot param addr */
gd->bd->bi_boot_params = (NV_PA_SDRAM_BASE + 0x100);
@ -268,6 +208,9 @@ int board_mmc_getcd(u8 *cd, struct mmc *mmc)
#ifdef CONFIG_BOARD_EARLY_INIT_F
int board_early_init_f(void)
{
/* Initialize essential common plls */
clock_early_init();
/* Initialize UART clocks */
clock_init_uart();

92
drivers/mmc/tegra2_mmc.c
View file

@ -23,36 +23,46 @@
#include <mmc.h>
#include <asm/io.h>
#include <asm/arch/clk_rst.h>
#include <asm/arch/clock.h>
#include "tegra2_mmc.h"
/* support 4 mmc hosts */
struct mmc mmc_dev[4];
struct mmc_host mmc_host[4];
static inline struct tegra2_mmc *tegra2_get_base_mmc(int dev_index)
/**
* Get the host address and peripheral ID for a device. Devices are numbered
* from 0 to 3.
*
* @param host Structure to fill in (base, reg, mmc_id)
* @param dev_index Device index (0-3)
*/
static void tegra2_get_setup(struct mmc_host *host, int dev_index)
{
unsigned long offset;
debug("tegra2_get_base_mmc: dev_index = %d\n", dev_index);
switch (dev_index) {
case 0:
offset = TEGRA2_SDMMC4_BASE;
break;
case 1:
offset = TEGRA2_SDMMC3_BASE;
host->base = TEGRA2_SDMMC3_BASE;
host->mmc_id = PERIPH_ID_SDMMC3;
break;
case 2:
offset = TEGRA2_SDMMC2_BASE;
host->base = TEGRA2_SDMMC2_BASE;
host->mmc_id = PERIPH_ID_SDMMC2;
break;
case 3:
offset = TEGRA2_SDMMC1_BASE;
host->base = TEGRA2_SDMMC1_BASE;
host->mmc_id = PERIPH_ID_SDMMC1;
break;
case 0:
default:
offset = TEGRA2_SDMMC4_BASE;
host->base = TEGRA2_SDMMC4_BASE;
host->mmc_id = PERIPH_ID_SDMMC4;
break;
}
return (struct tegra2_mmc *)(offset);
host->reg = (struct tegra2_mmc *)host->base;
}
static void mmc_prepare_data(struct mmc_host *host, struct mmc_data *data)
@ -274,62 +284,24 @@ static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
static void mmc_change_clock(struct mmc_host *host, uint clock)
{
int div, hw_div;
int div;
unsigned short clk;
unsigned long timeout;
unsigned int reg, hostbase;
struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
debug(" mmc_change_clock called\n");
/* Change Tegra2 SDMMCx clock divisor here */
/* Source is 216MHz, PLLP_OUT0 */
/*
* Change Tegra2 SDMMCx clock divisor here. Source is 216MHz,
* PLLP_OUT0
*/
if (clock == 0)
goto out;
div = 1;
if (clock <= 400000) {
hw_div = ((9-1)<<1); /* Best match is 375KHz */
div = 64;
} else if (clock <= 20000000)
hw_div = ((11-1)<<1); /* Best match is 19.6MHz */
else if (clock <= 26000000)
hw_div = ((9-1)<<1); /* Use 24MHz */
else
hw_div = ((4-1)<<1) + 1; /* 4.5 divisor for 48MHz */
debug("mmc_change_clock: hw_div = %d, card clock div = %d\n",
hw_div, div);
/* Change SDMMCx divisor */
hostbase = readl(&host->base);
debug("mmc_change_clock: hostbase = %08X\n", hostbase);
if (hostbase == TEGRA2_SDMMC1_BASE) {
reg = readl(&clkrst->crc_clk_src_sdmmc1);
reg &= 0xFFFFFF00; /* divisor (7.1) = 00 */
reg |= hw_div; /* n-1 */
writel(reg, &clkrst->crc_clk_src_sdmmc1);
} else if (hostbase == TEGRA2_SDMMC2_BASE) {
reg = readl(&clkrst->crc_clk_src_sdmmc2);
reg &= 0xFFFFFF00; /* divisor (7.1) = 00 */
reg |= hw_div; /* n-1 */
writel(reg, &clkrst->crc_clk_src_sdmmc2);
} else if (hostbase == TEGRA2_SDMMC3_BASE) {
reg = readl(&clkrst->crc_clk_src_sdmmc3);
reg &= 0xFFFFFF00; /* divisor (7.1) = 00 */
reg |= hw_div; /* n-1 */
writel(reg, &clkrst->crc_clk_src_sdmmc3);
} else {
reg = readl(&clkrst->crc_clk_src_sdmmc4);
reg &= 0xFFFFFF00; /* divisor (7.1) = 00 */
reg |= hw_div; /* n-1 */
writel(reg, &clkrst->crc_clk_src_sdmmc4);
}
clock_adjust_periph_pll_div(host->mmc_id, CLOCK_ID_PERIPH, clock,
&div);
debug("div = %d\n", div);
writew(0, &host->reg->clkcon);
div >>= 1;
/*
* CLKCON
* SELFREQ[15:8] : base clock divided by value
@ -337,6 +309,7 @@ static void mmc_change_clock(struct mmc_host *host, uint clock)
* STBLINTCLK[1] : Internal Clock Stable
* ENINTCLK[0] : Internal Clock Enable
*/
div >>= 1;
clk = (div << 8) | (1 << 0);
writew(clk, &host->reg->clkcon);
@ -355,7 +328,6 @@ static void mmc_change_clock(struct mmc_host *host, uint clock)
writew(clk, &host->reg->clkcon);
debug("mmc_change_clock: clkcon = %08X\n", clk);
debug("mmc_change_clock: CLK_SOURCE_SDMMCx = %08X\n", reg);
out:
host->clock = clock;
@ -370,7 +342,6 @@ static void mmc_set_ios(struct mmc *mmc)
debug("bus_width: %x, clock: %d\n", mmc->bus_width, mmc->clock);
/* Change clock first */
mmc_change_clock(host, mmc->clock);
ctrl = readb(&host->reg->hostctl);
@ -495,8 +466,7 @@ static int tegra2_mmc_initialize(int dev_index, int bus_width)
mmc->f_max = 48000000;
mmc_host[dev_index].clock = 0;
mmc_host[dev_index].reg = tegra2_get_base_mmc(dev_index);
mmc_host[dev_index].base = (unsigned int)mmc_host[dev_index].reg;
tegra2_get_setup(&mmc_host[dev_index], dev_index);
mmc_register(mmc);
return 0;

1
drivers/mmc/tegra2_mmc.h
View file

@ -73,6 +73,7 @@ struct mmc_host {
unsigned int version; /* SDHCI spec. version */
unsigned int clock; /* Current clock (MHz) */
unsigned int base; /* Base address, SDMMC1/2/3/4 */
enum periph_id mmc_id; /* Peripheral ID: PERIPH_ID_... */
};
int tegra2_mmc_init(int dev_index, int bus_width);