mirror of
https://github.com/Fishwaldo/u-boot.git
synced 2025-03-21 06:31:31 +00:00
Merge git://git.denx.de/u-boot-video
This commit is contained in:
commit
50905b55c7
11 changed files with 3465 additions and 46 deletions
|
@ -89,6 +89,37 @@
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||||||
compatible = "st,button1";
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compatible = "st,button1";
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||||||
button-gpio = <&gpioi 11 0>;
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button-gpio = <&gpioi 11 0>;
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||||||
};
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};
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||||||
|
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||||||
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backlight: backlight {
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||||||
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compatible = "gpio-backlight";
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||||||
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gpios = <&gpiok 3 0>;
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||||||
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status = "okay";
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||||||
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};
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||||||
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||||||
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panel-rgb@0 {
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compatible = "simple-panel";
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backlight = <&backlight>;
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enable-gpios = <&gpioi 12 0>;
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||||||
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status = "okay";
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||||||
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||||||
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display-timings {
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timing@0 {
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||||||
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clock-frequency = <9000000>;
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||||||
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hactive = <480>;
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||||||
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vactive = <272>;
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||||||
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hfront-porch = <2>;
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hback-porch = <2>;
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hsync-len = <41>;
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vfront-porch = <2>;
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||||||
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vback-porch = <2>;
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||||||
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vsync-len = <10>;
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||||||
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hsync-active = <0>;
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||||||
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vsync-active = <0>;
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||||||
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de-active = <0>;
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||||||
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pixelclk-active = <1>;
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||||||
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};
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||||||
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};
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||||||
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};
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||||||
};
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};
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||||||
|
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||||||
&clk_hse {
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&clk_hse {
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@ -183,6 +214,40 @@
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slew-rate = <2>;
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slew-rate = <2>;
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||||||
};
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};
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||||||
};
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};
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||||||
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||||||
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ltdc_pins: ltdc@0 {
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pins {
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pinmux = <STM32F746_PE4_FUNC_LCD_B0>,
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<STM32F746_PG12_FUNC_LCD_B4>,
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<STM32F746_PI9_FUNC_LCD_VSYNC>,
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<STM32F746_PI10_FUNC_LCD_HSYNC>,
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<STM32F746_PI14_FUNC_LCD_CLK>,
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<STM32F746_PI15_FUNC_LCD_R0>,
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<STM32F746_PJ0_FUNC_LCD_R1>,
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<STM32F746_PJ1_FUNC_LCD_R2>,
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||||||
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<STM32F746_PJ2_FUNC_LCD_R3>,
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||||||
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<STM32F746_PJ3_FUNC_LCD_R4>,
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<STM32F746_PJ4_FUNC_LCD_R5>,
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||||||
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<STM32F746_PJ5_FUNC_LCD_R6>,
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||||||
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<STM32F746_PJ6_FUNC_LCD_R7>,
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||||||
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<STM32F746_PJ7_FUNC_LCD_G0>,
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<STM32F746_PJ8_FUNC_LCD_G1>,
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||||||
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<STM32F746_PJ9_FUNC_LCD_G2>,
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<STM32F746_PJ10_FUNC_LCD_G3>,
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||||||
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<STM32F746_PJ11_FUNC_LCD_G4>,
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<STM32F746_PJ13_FUNC_LCD_B1>,
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<STM32F746_PJ14_FUNC_LCD_B2>,
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<STM32F746_PJ15_FUNC_LCD_B3>,
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<STM32F746_PK0_FUNC_LCD_G5>,
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<STM32F746_PK1_FUNC_LCD_G6>,
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<STM32F746_PK2_FUNC_LCD_G7>,
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||||||
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<STM32F746_PK4_FUNC_LCD_B5>,
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||||||
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<STM32F746_PK5_FUNC_LCD_B6>,
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||||||
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<STM32F746_PK6_FUNC_LCD_B7>,
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||||||
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<STM32F746_PK7_FUNC_LCD_DE>;
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||||||
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slew-rate = <2>;
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||||||
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};
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||||||
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};
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||||||
};
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};
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||||||
|
|
||||||
&usart1 {
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&usart1 {
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@ -250,3 +315,8 @@
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bus-width = <4>;
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bus-width = <4>;
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||||||
max-frequency = <25000000>;
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max-frequency = <25000000>;
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||||||
};
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};
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||||||
|
|
||||||
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<dc {
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||||||
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status = "okay";
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||||||
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pinctrl-0 = <<dc_pins>;
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||||||
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};
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|
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@ -330,6 +330,15 @@
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interrupts = <50>;
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interrupts = <50>;
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clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>;
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clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>;
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};
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};
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||||||
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ltdc: display-controller@40016800 {
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compatible = "st,stm32-ltdc";
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||||||
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reg = <0x40016800 0x200>;
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||||||
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resets = <&rcc STM32F7_APB2_RESET(LTDC)>;
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||||||
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clocks = <&rcc 0 STM32F7_APB2_CLOCK(LTDC)>;
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||||||
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u-boot,dm-pre-reloc;
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||||||
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status = "disabled";
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||||||
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};
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||||||
};
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};
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||||||
};
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};
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||||||
|
|
||||||
|
|
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@ -7,8 +7,12 @@
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||||||
|
|
||||||
#include <common.h>
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#include <common.h>
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#include <dm.h>
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#include <dm.h>
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#include <lcd.h>
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#include <ram.h>
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#include <ram.h>
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#include <spl.h>
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#include <spl.h>
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#include <splash.h>
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#include <st_logo_data.h>
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#include <video.h>
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#include <asm/io.h>
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#include <asm/io.h>
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#include <asm/armv7m.h>
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#include <asm/armv7m.h>
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#include <asm/arch/stm32.h>
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#include <asm/arch/stm32.h>
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||||||
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@ -153,5 +157,10 @@ int board_init(void)
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STM32_SYSCFG->pmc |= SYSCFG_PMC_MII_RMII_SEL;
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STM32_SYSCFG->pmc |= SYSCFG_PMC_MII_RMII_SEL;
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#endif
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#endif
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||||||
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|
||||||
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#if defined(CONFIG_CMD_BMP)
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bmp_display((ulong)stmicroelectronics_uboot_logo_8bit_rle,
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BMP_ALIGN_CENTER, BMP_ALIGN_CENTER);
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#endif /* CONFIG_CMD_BMP */
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||||||
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|
||||||
return 0;
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return 0;
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}
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}
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||||||
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|
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@ -29,6 +29,7 @@ CONFIG_CMD_PING=y
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CONFIG_CMD_SNTP=y
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CONFIG_CMD_SNTP=y
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CONFIG_CMD_DNS=y
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CONFIG_CMD_DNS=y
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CONFIG_CMD_LINK_LOCAL=y
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CONFIG_CMD_LINK_LOCAL=y
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CONFIG_CMD_BMP=y
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CONFIG_CMD_TIMER=y
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CONFIG_CMD_TIMER=y
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CONFIG_CMD_EXT2=y
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CONFIG_CMD_EXT2=y
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CONFIG_CMD_EXT4=y
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CONFIG_CMD_EXT4=y
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||||||
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@ -53,5 +54,10 @@ CONFIG_ETH_DESIGNWARE=y
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# CONFIG_PINCTRL_FULL is not set
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# CONFIG_PINCTRL_FULL is not set
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CONFIG_DM_SPI=y
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CONFIG_DM_SPI=y
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CONFIG_STM32_QSPI=y
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CONFIG_STM32_QSPI=y
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||||||
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CONFIG_DM_VIDEO=y
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||||||
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CONFIG_BACKLIGHT_GPIO=y
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||||||
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CONFIG_VIDEO_STM32=y
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||||||
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CONFIG_VIDEO_STM32_MAX_XRES=480
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||||||
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CONFIG_VIDEO_STM32_MAX_YRES=640
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||||||
CONFIG_OF_LIBFDT_OVERLAY=y
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CONFIG_OF_LIBFDT_OVERLAY=y
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||||||
# CONFIG_EFI_LOADER is not set
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# CONFIG_EFI_LOADER is not set
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||||||
|
|
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@ -768,7 +768,7 @@ static void parse_putc(const char c)
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break;
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break;
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||||||
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||||||
case '\n': /* next line */
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case '\n': /* next line */
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if (console_col || (!console_col && nl))
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if (console_col || nl)
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console_newline(1);
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console_newline(1);
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nl = 1;
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nl = 1;
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break;
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break;
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||||||
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|
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@ -853,9 +853,10 @@ static u32 wait_for_event(u32 event)
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||||||
do {
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do {
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ret = lcdc_irq_handler();
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ret = lcdc_irq_handler();
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udelay(1000);
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udelay(1000);
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||||||
} while (!(ret & event));
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--timeout;
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||||||
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} while (!(ret & event) && timeout);
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||||||
|
|
||||||
if (timeout <= 0) {
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if (!(ret & event)) {
|
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printf("%s: event %d not hit\n", __func__, event);
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printf("%s: event %d not hit\n", __func__, event);
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return -1;
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return -1;
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||||||
}
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}
|
||||||
|
|
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@ -321,7 +321,7 @@ static unsigned int exynos_dp_link_start(struct exynos_dp *regs,
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||||||
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static unsigned int exynos_dp_training_pattern_dis(struct exynos_dp *regs)
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static unsigned int exynos_dp_training_pattern_dis(struct exynos_dp *regs)
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{
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{
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unsigned int ret = EXYNOS_DP_SUCCESS;
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unsigned int ret;
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||||||
|
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exynos_dp_set_training_pattern(regs, DP_NONE);
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exynos_dp_set_training_pattern(regs, DP_NONE);
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||||||
|
|
||||||
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@ -339,7 +339,7 @@ static unsigned int exynos_dp_enable_rx_to_enhanced_mode(
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struct exynos_dp *regs, unsigned char enable)
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struct exynos_dp *regs, unsigned char enable)
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||||||
{
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{
|
||||||
unsigned char data;
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unsigned char data;
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unsigned int ret = EXYNOS_DP_SUCCESS;
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unsigned int ret;
|
||||||
|
|
||||||
ret = exynos_dp_read_byte_from_dpcd(regs, DPCD_LANE_COUNT_SET,
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ret = exynos_dp_read_byte_from_dpcd(regs, DPCD_LANE_COUNT_SET,
|
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&data);
|
&data);
|
||||||
|
@ -366,7 +366,7 @@ static unsigned int exynos_dp_enable_rx_to_enhanced_mode(
|
||||||
static unsigned int exynos_dp_set_enhanced_mode(struct exynos_dp *regs,
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static unsigned int exynos_dp_set_enhanced_mode(struct exynos_dp *regs,
|
||||||
unsigned char enhance_mode)
|
unsigned char enhance_mode)
|
||||||
{
|
{
|
||||||
unsigned int ret = EXYNOS_DP_SUCCESS;
|
unsigned int ret;
|
||||||
|
|
||||||
ret = exynos_dp_enable_rx_to_enhanced_mode(regs, enhance_mode);
|
ret = exynos_dp_enable_rx_to_enhanced_mode(regs, enhance_mode);
|
||||||
if (ret != EXYNOS_DP_SUCCESS) {
|
if (ret != EXYNOS_DP_SUCCESS) {
|
||||||
|
@ -416,7 +416,7 @@ static int exynos_dp_read_dpcd_lane_stat(struct exynos_dp *regs,
|
||||||
static unsigned int exynos_dp_read_dpcd_adj_req(struct exynos_dp *regs,
|
static unsigned int exynos_dp_read_dpcd_adj_req(struct exynos_dp *regs,
|
||||||
unsigned char lane_num, unsigned char *sw, unsigned char *em)
|
unsigned char lane_num, unsigned char *sw, unsigned char *em)
|
||||||
{
|
{
|
||||||
unsigned int ret = EXYNOS_DP_SUCCESS;
|
unsigned int ret;
|
||||||
unsigned char buf;
|
unsigned char buf;
|
||||||
unsigned int dpcd_addr;
|
unsigned int dpcd_addr;
|
||||||
unsigned char shift_val[DP_LANE_CNT_4] = {0, 4, 0, 4};
|
unsigned char shift_val[DP_LANE_CNT_4] = {0, 4, 0, 4};
|
||||||
|
@ -484,7 +484,7 @@ static int exynos_dp_reduce_link_rate(struct exynos_dp *regs,
|
||||||
static unsigned int exynos_dp_process_clock_recovery(struct exynos_dp *regs,
|
static unsigned int exynos_dp_process_clock_recovery(struct exynos_dp *regs,
|
||||||
struct exynos_dp_priv *priv)
|
struct exynos_dp_priv *priv)
|
||||||
{
|
{
|
||||||
unsigned int ret = EXYNOS_DP_SUCCESS;
|
unsigned int ret;
|
||||||
unsigned char lane_stat;
|
unsigned char lane_stat;
|
||||||
unsigned char lt_ctl_val[DP_LANE_CNT_4] = {0, };
|
unsigned char lt_ctl_val[DP_LANE_CNT_4] = {0, };
|
||||||
unsigned int i;
|
unsigned int i;
|
||||||
|
@ -594,7 +594,7 @@ static unsigned int exynos_dp_process_clock_recovery(struct exynos_dp *regs,
|
||||||
static unsigned int exynos_dp_process_equalizer_training(
|
static unsigned int exynos_dp_process_equalizer_training(
|
||||||
struct exynos_dp *regs, struct exynos_dp_priv *priv)
|
struct exynos_dp *regs, struct exynos_dp_priv *priv)
|
||||||
{
|
{
|
||||||
unsigned int ret = EXYNOS_DP_SUCCESS;
|
unsigned int ret;
|
||||||
unsigned char lane_stat, adj_req_sw, adj_req_em, i;
|
unsigned char lane_stat, adj_req_sw, adj_req_em, i;
|
||||||
unsigned char lt_ctl_val[DP_LANE_CNT_4] = {0,};
|
unsigned char lt_ctl_val[DP_LANE_CNT_4] = {0,};
|
||||||
unsigned char interlane_aligned = 0;
|
unsigned char interlane_aligned = 0;
|
||||||
|
|
|
@ -1993,7 +1993,7 @@ static void stbtt__fill_active_edges_new(float *scanline, float *scanline_fill,
|
||||||
|
|
||||||
STBTT_assert(fabs(area) <= 1.01f);
|
STBTT_assert(fabs(area) <= 1.01f);
|
||||||
|
|
||||||
scanline[x2] += area + sign * (1-((x2-x2)+(x_bottom-x2))/2) * (sy1-y_crossing);
|
scanline[x2] += area + sign * (1-(x_bottom-x2)/2) * (sy1-y_crossing);
|
||||||
|
|
||||||
scanline_fill[x2] += sign * (sy1-sy0);
|
scanline_fill[x2] += sign * (sy1-sy0);
|
||||||
}
|
}
|
||||||
|
|
|
@ -1,8 +1,7 @@
|
||||||
/*
|
/*
|
||||||
* Copyright (C) STMicroelectronics SA 2017
|
* Copyright (C) 2017-2018 STMicroelectronics - All Rights Reserved
|
||||||
*
|
* Author(s): Philippe Cornu <philippe.cornu@st.com> for STMicroelectronics.
|
||||||
* Authors: Philippe Cornu <philippe.cornu@st.com>
|
* Yannick Fertre <yannick.fertre@st.com> for STMicroelectronics.
|
||||||
* Yannick Fertre <yannick.fertre@st.com>
|
|
||||||
*
|
*
|
||||||
* SPDX-License-Identifier: GPL-2.0+
|
* SPDX-License-Identifier: GPL-2.0+
|
||||||
*/
|
*/
|
||||||
|
@ -11,6 +10,7 @@
|
||||||
#include <clk.h>
|
#include <clk.h>
|
||||||
#include <dm.h>
|
#include <dm.h>
|
||||||
#include <panel.h>
|
#include <panel.h>
|
||||||
|
#include <reset.h>
|
||||||
#include <video.h>
|
#include <video.h>
|
||||||
#include <asm/io.h>
|
#include <asm/io.h>
|
||||||
#include <asm/arch/gpio.h>
|
#include <asm/arch/gpio.h>
|
||||||
|
@ -138,7 +138,9 @@ struct stm32_ltdc_priv {
|
||||||
#define LXCFBLNR_CFBLN GENMASK(10, 0) /* Color Frame Buffer Line Number */
|
#define LXCFBLNR_CFBLN GENMASK(10, 0) /* Color Frame Buffer Line Number */
|
||||||
|
|
||||||
#define BF1_PAXCA 0x600 /* Pixel Alpha x Constant Alpha */
|
#define BF1_PAXCA 0x600 /* Pixel Alpha x Constant Alpha */
|
||||||
|
#define BF1_CA 0x400 /* Constant Alpha */
|
||||||
#define BF2_1PAXCA 0x007 /* 1 - (Pixel Alpha x Constant Alpha) */
|
#define BF2_1PAXCA 0x007 /* 1 - (Pixel Alpha x Constant Alpha) */
|
||||||
|
#define BF2_1CA 0x005 /* 1 - Constant Alpha */
|
||||||
|
|
||||||
enum stm32_ltdc_pix_fmt {
|
enum stm32_ltdc_pix_fmt {
|
||||||
PF_ARGB8888 = 0,
|
PF_ARGB8888 = 0,
|
||||||
|
@ -161,11 +163,17 @@ static u32 stm32_ltdc_get_pixel_format(enum video_log2_bpp l2bpp)
|
||||||
pf = PF_RGB565;
|
pf = PF_RGB565;
|
||||||
break;
|
break;
|
||||||
|
|
||||||
|
case VIDEO_BPP32:
|
||||||
|
pf = PF_ARGB8888;
|
||||||
|
break;
|
||||||
|
|
||||||
|
case VIDEO_BPP8:
|
||||||
|
pf = PF_L8;
|
||||||
|
break;
|
||||||
|
|
||||||
case VIDEO_BPP1:
|
case VIDEO_BPP1:
|
||||||
case VIDEO_BPP2:
|
case VIDEO_BPP2:
|
||||||
case VIDEO_BPP4:
|
case VIDEO_BPP4:
|
||||||
case VIDEO_BPP8:
|
|
||||||
case VIDEO_BPP32:
|
|
||||||
default:
|
default:
|
||||||
debug("%s: warning %dbpp not supported yet, %dbpp instead\n",
|
debug("%s: warning %dbpp not supported yet, %dbpp instead\n",
|
||||||
__func__, VNBITS(l2bpp), VNBITS(VIDEO_BPP16));
|
__func__, VNBITS(l2bpp), VNBITS(VIDEO_BPP16));
|
||||||
|
@ -178,6 +186,23 @@ static u32 stm32_ltdc_get_pixel_format(enum video_log2_bpp l2bpp)
|
||||||
return (u32)pf;
|
return (u32)pf;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
static bool has_alpha(u32 fmt)
|
||||||
|
{
|
||||||
|
switch (fmt) {
|
||||||
|
case PF_ARGB8888:
|
||||||
|
case PF_ARGB1555:
|
||||||
|
case PF_ARGB4444:
|
||||||
|
case PF_AL44:
|
||||||
|
case PF_AL88:
|
||||||
|
return true;
|
||||||
|
case PF_RGB888:
|
||||||
|
case PF_RGB565:
|
||||||
|
case PF_L8:
|
||||||
|
default:
|
||||||
|
return false;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
static void stm32_ltdc_enable(struct stm32_ltdc_priv *priv)
|
static void stm32_ltdc_enable(struct stm32_ltdc_priv *priv)
|
||||||
{
|
{
|
||||||
/* Reload configuration immediately & enable LTDC */
|
/* Reload configuration immediately & enable LTDC */
|
||||||
|
@ -219,6 +244,8 @@ static void stm32_ltdc_set_mode(struct stm32_ltdc_priv *priv)
|
||||||
val = (total_w << 16) | total_h;
|
val = (total_w << 16) | total_h;
|
||||||
clrsetbits_le32(regs + LTDC_TWCR, TWCR_TOTALH | TWCR_TOTALW, val);
|
clrsetbits_le32(regs + LTDC_TWCR, TWCR_TOTALH | TWCR_TOTALW, val);
|
||||||
|
|
||||||
|
setbits_le32(regs + LTDC_LIPCR, acc_act_h + 1);
|
||||||
|
|
||||||
/* Signal polarities */
|
/* Signal polarities */
|
||||||
val = 0;
|
val = 0;
|
||||||
debug("%s: timing->flags 0x%08x\n", __func__, timing->flags);
|
debug("%s: timing->flags 0x%08x\n", __func__, timing->flags);
|
||||||
|
@ -245,6 +272,7 @@ static void stm32_ltdc_set_layer1(struct stm32_ltdc_priv *priv, ulong fb_addr)
|
||||||
u32 line_length;
|
u32 line_length;
|
||||||
u32 bus_width;
|
u32 bus_width;
|
||||||
u32 val, tmp, bpp;
|
u32 val, tmp, bpp;
|
||||||
|
u32 format;
|
||||||
|
|
||||||
x0 = priv->crop_x;
|
x0 = priv->crop_x;
|
||||||
x1 = priv->crop_x + priv->crop_w - 1;
|
x1 = priv->crop_x + priv->crop_w - 1;
|
||||||
|
@ -275,15 +303,18 @@ static void stm32_ltdc_set_layer1(struct stm32_ltdc_priv *priv, ulong fb_addr)
|
||||||
clrsetbits_le32(regs + LTDC_L1CFBLR, LXCFBLR_CFBLL | LXCFBLR_CFBP, val);
|
clrsetbits_le32(regs + LTDC_L1CFBLR, LXCFBLR_CFBLL | LXCFBLR_CFBP, val);
|
||||||
|
|
||||||
/* Pixel format */
|
/* Pixel format */
|
||||||
val = stm32_ltdc_get_pixel_format(priv->l2bpp);
|
format = stm32_ltdc_get_pixel_format(priv->l2bpp);
|
||||||
clrsetbits_le32(regs + LTDC_L1PFCR, LXPFCR_PF, val);
|
clrsetbits_le32(regs + LTDC_L1PFCR, LXPFCR_PF, format);
|
||||||
|
|
||||||
/* Constant alpha value */
|
/* Constant alpha value */
|
||||||
clrsetbits_le32(regs + LTDC_L1CACR, LXCACR_CONSTA, priv->alpha);
|
clrsetbits_le32(regs + LTDC_L1CACR, LXCACR_CONSTA, priv->alpha);
|
||||||
|
|
||||||
|
/* Specifies the blending factors : with or without pixel alpha */
|
||||||
|
/* Manage hw-specific capabilities */
|
||||||
|
val = has_alpha(format) ? BF1_PAXCA | BF2_1PAXCA : BF1_CA | BF2_1CA;
|
||||||
|
|
||||||
/* Blending factors */
|
/* Blending factors */
|
||||||
clrsetbits_le32(regs + LTDC_L1BFCR, LXBFCR_BF2 | LXBFCR_BF1,
|
clrsetbits_le32(regs + LTDC_L1BFCR, LXBFCR_BF2 | LXBFCR_BF1, val);
|
||||||
BF1_PAXCA | BF2_1PAXCA);
|
|
||||||
|
|
||||||
/* Frame buffer line number */
|
/* Frame buffer line number */
|
||||||
clrsetbits_le32(regs + LTDC_L1CFBLNR, LXCFBLNR_CFBLN, priv->crop_h);
|
clrsetbits_le32(regs + LTDC_L1CFBLNR, LXCFBLNR_CFBLN, priv->crop_h);
|
||||||
|
@ -301,8 +332,9 @@ static int stm32_ltdc_probe(struct udevice *dev)
|
||||||
struct video_priv *uc_priv = dev_get_uclass_priv(dev);
|
struct video_priv *uc_priv = dev_get_uclass_priv(dev);
|
||||||
struct stm32_ltdc_priv *priv = dev_get_priv(dev);
|
struct stm32_ltdc_priv *priv = dev_get_priv(dev);
|
||||||
struct udevice *panel;
|
struct udevice *panel;
|
||||||
struct clk pclk, pxclk;
|
struct clk pclk;
|
||||||
int ret;
|
struct reset_ctl rst;
|
||||||
|
int rate, ret;
|
||||||
|
|
||||||
priv->regs = (void *)dev_read_addr(dev);
|
priv->regs = (void *)dev_read_addr(dev);
|
||||||
if ((fdt_addr_t)priv->regs == FDT_ADDR_T_NONE) {
|
if ((fdt_addr_t)priv->regs == FDT_ADDR_T_NONE) {
|
||||||
|
@ -310,6 +342,28 @@ static int stm32_ltdc_probe(struct udevice *dev)
|
||||||
return -EINVAL;
|
return -EINVAL;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
ret = clk_get_by_index(dev, 0, &pclk);
|
||||||
|
if (ret) {
|
||||||
|
debug("%s: peripheral clock get error %d\n", __func__, ret);
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
ret = clk_enable(&pclk);
|
||||||
|
if (ret) {
|
||||||
|
debug("%s: peripheral clock enable error %d\n",
|
||||||
|
__func__, ret);
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
ret = reset_get_by_index(dev, 0, &rst);
|
||||||
|
if (ret) {
|
||||||
|
debug("%s: missing ltdc hardware reset\n", __func__);
|
||||||
|
return -ENODEV;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Reset */
|
||||||
|
reset_deassert(&rst);
|
||||||
|
|
||||||
ret = uclass_first_device(UCLASS_PANEL, &panel);
|
ret = uclass_first_device(UCLASS_PANEL, &panel);
|
||||||
if (ret) {
|
if (ret) {
|
||||||
debug("%s: panel device error %d\n", __func__, ret);
|
debug("%s: panel device error %d\n", __func__, ret);
|
||||||
|
@ -323,31 +377,24 @@ static int stm32_ltdc_probe(struct udevice *dev)
|
||||||
return ret;
|
return ret;
|
||||||
}
|
}
|
||||||
|
|
||||||
ret = fdtdec_decode_display_timing(gd->fdt_blob, dev_of_offset(dev),
|
ret = fdtdec_decode_display_timing(gd->fdt_blob,
|
||||||
0, &priv->timing);
|
dev_of_offset(dev), 0,
|
||||||
|
&priv->timing);
|
||||||
if (ret) {
|
if (ret) {
|
||||||
debug("%s: decode display timing error %d\n", __func__, ret);
|
debug("%s: decode display timing error %d\n",
|
||||||
|
__func__, ret);
|
||||||
return -EINVAL;
|
return -EINVAL;
|
||||||
}
|
}
|
||||||
|
|
||||||
ret = clk_get_by_name(dev, "pclk", &pclk);
|
rate = clk_set_rate(&pclk, priv->timing.pixelclock.typ);
|
||||||
if (ret) {
|
if (rate < 0) {
|
||||||
debug("%s: peripheral clock get error %d\n", __func__, ret);
|
debug("%s: fail to set pixel clock %d hz %d hz\n",
|
||||||
return ret;
|
__func__, priv->timing.pixelclock.typ, rate);
|
||||||
|
return rate;
|
||||||
}
|
}
|
||||||
|
|
||||||
ret = clk_enable(&pclk);
|
debug("%s: Set pixel clock req %d hz get %d hz\n", __func__,
|
||||||
if (ret) {
|
priv->timing.pixelclock.typ, rate);
|
||||||
debug("%s: peripheral clock enable error %d\n", __func__, ret);
|
|
||||||
return ret;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Verify pixel clock value if any & inform user accordingly */
|
|
||||||
ret = clk_get_by_name(dev, "pxclk", &pxclk);
|
|
||||||
if (!ret) {
|
|
||||||
if (clk_get_rate(&pxclk) != priv->timing.pixelclock.typ)
|
|
||||||
printf("Warning: please adjust ltdc pixel clock\n");
|
|
||||||
}
|
|
||||||
|
|
||||||
/* TODO Below parameters are hard-coded for the moment... */
|
/* TODO Below parameters are hard-coded for the moment... */
|
||||||
priv->l2bpp = VIDEO_BPP16;
|
priv->l2bpp = VIDEO_BPP16;
|
||||||
|
@ -397,10 +444,10 @@ static const struct udevice_id stm32_ltdc_ids[] = {
|
||||||
};
|
};
|
||||||
|
|
||||||
U_BOOT_DRIVER(stm32_ltdc) = {
|
U_BOOT_DRIVER(stm32_ltdc) = {
|
||||||
.name = "stm32_ltdc",
|
.name = "stm32_display",
|
||||||
.id = UCLASS_VIDEO,
|
.id = UCLASS_VIDEO,
|
||||||
.of_match = stm32_ltdc_ids,
|
.of_match = stm32_ltdc_ids,
|
||||||
.probe = stm32_ltdc_probe,
|
.probe = stm32_ltdc_probe,
|
||||||
.bind = stm32_ltdc_bind,
|
.bind = stm32_ltdc_bind,
|
||||||
.priv_auto_alloc_size = sizeof(struct stm32_ltdc_priv),
|
.priv_auto_alloc_size = sizeof(struct stm32_ltdc_priv),
|
||||||
};
|
};
|
||||||
|
|
|
@ -79,4 +79,14 @@
|
||||||
#endif
|
#endif
|
||||||
/* For SPL ends */
|
/* For SPL ends */
|
||||||
|
|
||||||
|
/* For splashcreen */
|
||||||
|
#ifdef CONFIG_DM_VIDEO
|
||||||
|
#define CONFIG_VIDEO_BMP_RLE8
|
||||||
|
#define CONFIG_BMP_16BPP
|
||||||
|
#define CONFIG_BMP_24BPP
|
||||||
|
#define CONFIG_BMP_32BPP
|
||||||
|
#define CONFIG_SPLASH_SCREEN
|
||||||
|
#define CONFIG_SPLASH_SCREEN_ALIGN
|
||||||
|
#endif
|
||||||
|
|
||||||
#endif /* __CONFIG_H */
|
#endif /* __CONFIG_H */
|
||||||
|
|
3267
include/st_logo_data.h
Normal file
3267
include/st_logo_data.h
Normal file
File diff suppressed because it is too large
Load diff
Loading…
Add table
Reference in a new issue