mirror of
https://github.com/Fishwaldo/u-boot.git
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ARM: uniphier: refactor cmd_ddrmphy
Make it look like cmd_ddrphy. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
This commit is contained in:
parent
fada9eafe1
commit
513cfaccc8
1 changed files with 109 additions and 80 deletions
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@ -1,13 +1,15 @@
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/*
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/*
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* Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
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* Copyright (C) 2015-2017 Socionext Inc.
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* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
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*
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*
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* SPDX-License-Identifier: GPL-2.0+
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* SPDX-License-Identifier: GPL-2.0+
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*/
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*/
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#include <common.h>
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#include <common.h>
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#include <linux/io.h>
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#include <linux/io.h>
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#include <linux/sizes.h>
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#include "../init.h"
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#include "../soc-info.h"
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#include "ddrmphy-regs.h"
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#include "ddrmphy-regs.h"
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/* Select either decimal or hexadecimal */
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/* Select either decimal or hexadecimal */
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@ -19,24 +21,41 @@
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/* field separator */
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/* field separator */
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#define FS " "
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#define FS " "
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static void __iomem *get_phy_base(int ch)
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#define ptr_to_uint(p) ((unsigned int)(unsigned long)(p))
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{
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return (void __iomem *)(0x5b830000 + ch * 0x00200000);
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}
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static int get_nr_ch(void)
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#define UNIPHIER_MAX_NR_DDRMPHY 3
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{
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const struct uniphier_board_data *bd = uniphier_get_board_param();
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return bd->dram_ch[2].size ? 3 : 2;
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struct uniphier_ddrmphy_param {
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}
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unsigned int soc_id;
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unsigned int nr_phy;
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struct {
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resource_size_t base;
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unsigned int nr_zq;
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unsigned int nr_dx;
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} phy[UNIPHIER_MAX_NR_DDRMPHY];
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};
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static int get_nr_datx8(int ch)
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static const struct uniphier_ddrmphy_param uniphier_ddrmphy_param[] = {
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{
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{
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const struct uniphier_board_data *bd = uniphier_get_board_param();
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.soc_id = UNIPHIER_PXS2_ID,
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.nr_phy = 3,
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return bd->dram_ch[ch].width / 8;
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.phy = {
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}
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{ .base = 0x5b830000, .nr_zq = 3, .nr_dx = 4, },
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{ .base = 0x5ba30000, .nr_zq = 3, .nr_dx = 4, },
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{ .base = 0x5bc30000, .nr_zq = 2, .nr_dx = 2, },
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},
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},
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{
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.soc_id = UNIPHIER_LD6B_ID,
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.nr_phy = 3,
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.phy = {
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{ .base = 0x5b830000, .nr_zq = 3, .nr_dx = 4, },
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{ .base = 0x5ba30000, .nr_zq = 3, .nr_dx = 4, },
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{ .base = 0x5bc30000, .nr_zq = 2, .nr_dx = 2, },
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},
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},
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};
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UNIPHIER_DEFINE_SOCDATA_FUNC(uniphier_get_ddrmphy_param, uniphier_ddrmphy_param)
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static void print_bdl(void __iomem *reg, int n)
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static void print_bdl(void __iomem *reg, int n)
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{
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{
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@ -47,59 +66,60 @@ static void print_bdl(void __iomem *reg, int n)
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printf(FS PRINTF_FORMAT, (val >> i * 8) & 0x1f);
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printf(FS PRINTF_FORMAT, (val >> i * 8) & 0x1f);
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}
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}
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static void dump_loop(void (*callback)(void __iomem *))
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static void dump_loop(const struct uniphier_ddrmphy_param *param,
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void (*callback)(void __iomem *))
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{
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{
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int ch, dx, nr_ch, nr_dx;
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void __iomem *phy_base, *dx_base;
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void __iomem *dx_base;
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int phy, dx;
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nr_ch = get_nr_ch();
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for (phy = 0; phy < param->nr_phy; phy++) {
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phy_base = ioremap(param->phy[phy].base, SZ_4K);
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dx_base = phy_base + MPHY_DX_BASE;
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for (ch = 0; ch < nr_ch; ch++) {
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for (dx = 0; dx < param->phy[phy].nr_dx; dx++) {
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dx_base = get_phy_base(ch) + MPHY_DX_BASE;
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printf("PHY%dDX%d:", phy, dx);
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nr_dx = get_nr_datx8(ch);
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for (dx = 0; dx < nr_dx; dx++) {
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printf("CH%dDX%d:", ch, dx);
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(*callback)(dx_base);
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(*callback)(dx_base);
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dx_base += MPHY_DX_STRIDE;
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dx_base += MPHY_DX_STRIDE;
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printf("\n");
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printf("\n");
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}
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}
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iounmap(phy_base);
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}
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}
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}
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}
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static void zq_dump(void)
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static void zq_dump(const struct uniphier_ddrmphy_param *param)
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{
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{
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int ch, zq, nr_ch, nr_zq, i;
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void __iomem *phy_base, *zq_base;
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void __iomem *zq_base;
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u32 val;
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u32 dr, pr;
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int phy, zq, i;
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printf("\n--- Impedance Data ---\n");
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printf("\n--- Impedance Data ---\n");
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printf(" ZPD ZPU OPD OPU ZDV ODV\n");
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printf(" ZPD ZPU OPD OPU ZDV ODV\n");
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nr_ch = get_nr_ch();
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for (phy = 0; phy < param->nr_phy; phy++) {
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phy_base = ioremap(param->phy[phy].base, SZ_4K);
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zq_base = phy_base + MPHY_ZQ_BASE;
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for (ch = 0; ch < nr_ch; ch++) {
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for (zq = 0; zq < param->phy[phy].nr_zq; zq++) {
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zq_base = get_phy_base(ch) + MPHY_ZQ_BASE;
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printf("PHY%dZQ%d:", phy, zq);
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nr_zq = 3;
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for (zq = 0; zq < nr_zq; zq++) {
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val = readl(zq_base + MPHY_ZQ_DR);
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printf("CH%dZQ%d:", ch, zq);
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dr = readl(zq_base + MPHY_ZQ_DR);
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for (i = 0; i < 4; i++) {
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for (i = 0; i < 4; i++) {
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printf(FS PRINTF_FORMAT, dr & 0x7f);
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printf(FS PRINTF_FORMAT, val & 0x7f);
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dr >>= 7;
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val >>= 7;
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}
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}
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pr = readl(zq_base + MPHY_ZQ_PR);
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val = readl(zq_base + MPHY_ZQ_PR);
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for (i = 0; i < 2; i++) {
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for (i = 0; i < 2; i++) {
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printf(FS PRINTF_FORMAT, pr & 0xf);
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printf(FS PRINTF_FORMAT, val & 0xf);
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pr >>= 4;
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val >>= 4;
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}
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}
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zq_base += MPHY_ZQ_STRIDE;
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zq_base += MPHY_ZQ_STRIDE;
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printf("\n");
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printf("\n");
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}
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}
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iounmap(phy_base);
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}
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}
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}
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}
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@ -113,12 +133,12 @@ static void __wbdl_dump(void __iomem *dx_base)
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readl(dx_base + MPHY_DX_LCDLR1) & 0xff);
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readl(dx_base + MPHY_DX_LCDLR1) & 0xff);
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}
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}
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static void wbdl_dump(void)
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static void wbdl_dump(const struct uniphier_ddrmphy_param *param)
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{
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{
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printf("\n--- Write Bit Delay Line ---\n");
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printf("\n--- Write Bit Delay Line ---\n");
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printf(" DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM DQS (WDQD)\n");
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printf(" DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM DQS (WDQD)\n");
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dump_loop(&__wbdl_dump);
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dump_loop(param, &__wbdl_dump);
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}
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}
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static void __rbdl_dump(void __iomem *dx_base)
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static void __rbdl_dump(void __iomem *dx_base)
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@ -134,12 +154,12 @@ static void __rbdl_dump(void __iomem *dx_base)
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(readl(dx_base + MPHY_DX_LCDLR1) >> 16) & 0xff);
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(readl(dx_base + MPHY_DX_LCDLR1) >> 16) & 0xff);
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}
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}
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static void rbdl_dump(void)
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static void rbdl_dump(const struct uniphier_ddrmphy_param *param)
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{
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{
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printf("\n--- Read Bit Delay Line ---\n");
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printf("\n--- Read Bit Delay Line ---\n");
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printf(" DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM (RDQSD) (RDQSND)\n");
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printf(" DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM (RDQSD) (RDQSND)\n");
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dump_loop(&__rbdl_dump);
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dump_loop(param, &__rbdl_dump);
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}
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}
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static void __wld_dump(void __iomem *dx_base)
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static void __wld_dump(void __iomem *dx_base)
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@ -157,12 +177,12 @@ static void __wld_dump(void __iomem *dx_base)
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}
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}
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}
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}
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static void wld_dump(void)
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static void wld_dump(const struct uniphier_ddrmphy_param *param)
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{
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{
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printf("\n--- Write Leveling Delay ---\n");
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printf("\n--- Write Leveling Delay ---\n");
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printf(" Rank0 Rank1 Rank2 Rank3\n");
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printf(" Rank0 Rank1 Rank2 Rank3\n");
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dump_loop(&__wld_dump);
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dump_loop(param, &__wld_dump);
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}
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}
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static void __dqsgd_dump(void __iomem *dx_base)
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static void __dqsgd_dump(void __iomem *dx_base)
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}
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}
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}
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}
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static void dqsgd_dump(void)
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static void dqsgd_dump(const struct uniphier_ddrmphy_param *param)
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{
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{
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printf("\n--- DQS Gating Delay ---\n");
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printf("\n--- DQS Gating Delay ---\n");
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printf(" Rank0 Rank1 Rank2 Rank3\n");
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printf(" Rank0 Rank1 Rank2 Rank3\n");
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dump_loop(&__dqsgd_dump);
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dump_loop(param, &__dqsgd_dump);
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}
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}
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static void __mdl_dump(void __iomem *dx_base)
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static void __mdl_dump(void __iomem *dx_base)
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printf(FS PRINTF_FORMAT, (mdl >> (8 * i)) & 0xff);
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printf(FS PRINTF_FORMAT, (mdl >> (8 * i)) & 0xff);
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}
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}
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static void mdl_dump(void)
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static void mdl_dump(const struct uniphier_ddrmphy_param *param)
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{
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{
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printf("\n--- Master Delay Line ---\n");
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printf("\n--- Master Delay Line ---\n");
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printf(" IPRD TPRD MDLD\n");
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printf(" IPRD TPRD MDLD\n");
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dump_loop(&__mdl_dump);
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dump_loop(param, &__mdl_dump);
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}
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}
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#define REG_DUMP(x) \
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#define REG_DUMP(x) \
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printf("%3d: DX%d%-7s: %p : %08x\n", \
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printf("%3d: DX%d%-7s: %p : %08x\n", \
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ofst >> MPHY_SHIFT, (dx), #x, reg, readl(reg)); }
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ofst >> MPHY_SHIFT, (dx), #x, reg, readl(reg)); }
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static void reg_dump(void)
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static void reg_dump(const struct uniphier_ddrmphy_param *param)
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{
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{
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int ch, dx, nr_ch, nr_dx;
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void __iomem *phy_base;
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void __iomem *phy_base;
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int phy, dx;
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printf("\n--- DDR PHY registers ---\n");
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printf("\n--- DDR Multi PHY registers ---\n");
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nr_ch = get_nr_ch();
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for (phy = 0; phy < param->nr_phy; phy++) {
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phy_base = ioremap(param->phy[phy].base, SZ_4K);
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for (ch = 0; ch < nr_ch; ch++) {
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printf("== PHY%d (base: %08x) ==\n", phy,
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phy_base = get_phy_base(ch);
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ptr_to_uint(phy_base));
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nr_dx = get_nr_datx8(ch);
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printf("== Ch%d ==\n", ch);
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printf(" No: Name : Address : Data\n");
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printf(" No: Name : Address : Data\n");
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REG_DUMP(RIDR);
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REG_DUMP(RIDR);
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REG_DUMP(MR2);
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REG_DUMP(MR2);
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REG_DUMP(MR3);
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REG_DUMP(MR3);
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for (dx = 0; dx < nr_dx; dx++) {
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for (dx = 0; dx < param->phy[phy].nr_dx; dx++) {
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DX_REG_DUMP(dx, GCR0);
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DX_REG_DUMP(dx, GCR0);
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DX_REG_DUMP(dx, GCR1);
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DX_REG_DUMP(dx, GCR1);
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DX_REG_DUMP(dx, GCR2);
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DX_REG_DUMP(dx, GCR2);
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DX_REG_DUMP(dx, GCR3);
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DX_REG_DUMP(dx, GCR3);
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DX_REG_DUMP(dx, GTR);
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DX_REG_DUMP(dx, GTR);
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}
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}
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iounmap(phy_base);
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}
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}
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}
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}
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static int do_ddrm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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static int do_ddrm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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{
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char *cmd = argv[1];
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const struct uniphier_ddrmphy_param *param;
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char *cmd;
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param = uniphier_get_ddrmphy_param();
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if (!param) {
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printf("unsupported SoC\n");
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return CMD_RET_FAILURE;
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}
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if (argc == 1)
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if (argc == 1)
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cmd = "all";
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cmd = "all";
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else
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cmd = argv[1];
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if (!strcmp(cmd, "zq") || !strcmp(cmd, "all"))
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if (!strcmp(cmd, "zq") || !strcmp(cmd, "all"))
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zq_dump();
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zq_dump(param);
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if (!strcmp(cmd, "wbdl") || !strcmp(cmd, "all"))
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if (!strcmp(cmd, "wbdl") || !strcmp(cmd, "all"))
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wbdl_dump();
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wbdl_dump(param);
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if (!strcmp(cmd, "rbdl") || !strcmp(cmd, "all"))
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if (!strcmp(cmd, "rbdl") || !strcmp(cmd, "all"))
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rbdl_dump();
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rbdl_dump(param);
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if (!strcmp(cmd, "wld") || !strcmp(cmd, "all"))
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if (!strcmp(cmd, "wld") || !strcmp(cmd, "all"))
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wld_dump();
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wld_dump(param);
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if (!strcmp(cmd, "dqsgd") || !strcmp(cmd, "all"))
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if (!strcmp(cmd, "dqsgd") || !strcmp(cmd, "all"))
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dqsgd_dump();
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dqsgd_dump(param);
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if (!strcmp(cmd, "mdl") || !strcmp(cmd, "all"))
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if (!strcmp(cmd, "mdl") || !strcmp(cmd, "all"))
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mdl_dump();
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mdl_dump(param);
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if (!strcmp(cmd, "reg") || !strcmp(cmd, "all"))
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if (!strcmp(cmd, "reg") || !strcmp(cmd, "all"))
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reg_dump();
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reg_dump(param);
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return 0;
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return CMD_RET_SUCCESS;
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}
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}
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U_BOOT_CMD(
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U_BOOT_CMD(
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ddrm, 2, 1, do_ddrm,
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ddrm, 2, 1, do_ddrm,
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"UniPhier DDR PHY parameters dumper",
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"UniPhier DDR Multi PHY parameters dumper",
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"- dump all of the following\n"
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"- dump all of the following\n"
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"ddrm zq - dump Impedance Data\n"
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"ddrm zq - dump Impedance Data\n"
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"ddrm wbdl - dump Write Bit Delay\n"
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"ddrm wbdl - dump Write Bit Delay\n"
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