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powerpc/85xx:Fix MSR[DE] bit in MSR to support debugger

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Debugging of e500 and e500v1 processer requires MSR[DE] bit to be set always.
Where MSR = Machine State register

Make sure of MSR[DE] bit is set uniformaly across the different execution
address space i.e. AS0 and AS1.

Signed-off-by: Radu Lazarescu <radu.lazarescu@freescale.com>
Signed-off-by: Catalin Udma <catalin.udma@freescale.com>
Signed-off-by: Marius Grigoras <marius.grigoras@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
This commit is contained in:
Prabhakar Kushwaha 2012-04-29 23:56:30 +00:00 • committed by Andy Fleming
parent afa6b551fd
commit 5344f7a258
2 changed files with 6 additions and 3 deletions
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2
arch/powerpc/cpu/mpc85xx/cpu_init.c
View file

@ -537,7 +537,7 @@ void arch_preboot_os(void)
* disabled by the time we get called.
*/
msr = mfmsr();
msr &= ~(MSR_ME|MSR_CE|MSR_DE);
msr &= ~(MSR_ME|MSR_CE);
mtmsr(msr);
setup_ivors();

7
arch/powerpc/cpu/mpc85xx/start.S
View file

@ -82,6 +82,9 @@
.globl _start_e500
_start_e500:
/* Enable debug exception */
li r1,MSR_DE
mtmsr r1
#if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_E500MC)
/* ISBC uses L2 as stack.
@ -733,8 +736,8 @@ create_init_ram_area:
msync
tlbwe
lis r6,MSR_IS|MSR_DS@h
ori r6,r6,MSR_IS|MSR_DS@l
lis r6,MSR_IS|MSR_DS|MSR_DE@h
ori r6,r6,MSR_IS|MSR_DS|MSR_DE@l
lis r7,switch_as@h
ori r7,r7,switch_as@l