From 6978db36aa6daa31f3ac12e699f5c6a540ff2cd0 Mon Sep 17 00:00:00 2001 From: John Robertson Date: Tue, 1 Sep 2020 02:55:14 +0000 Subject: [PATCH 1/8] mmc: pic32: Refresh PIC32 MMC driver The existing driver is not compatible with the Driver Model. This patch makes the necessary changes while also removing obsolescent calls/properties as follows: - fdtdec_* calls replaced with dev_read_* equivalents; - 'clock-freq-min-max' property replaced by querying the frequency of the source clock 'base_clk'; - The card detect erratum workaround is applied during probe rather than overriding get_cd. The card detect workaround (Microchip ref. DS80000736E, erratum #15) is not always needed and can be disabled using a vendor specific DT property. Signed-off-by: John Robertson --- drivers/mmc/pic32_sdhci.c | 98 ++++++++++++++++++++++----------------- 1 file changed, 56 insertions(+), 42 deletions(-) diff --git a/drivers/mmc/pic32_sdhci.c b/drivers/mmc/pic32_sdhci.c index 029e0fbc2b..e201bdb8f4 100644 --- a/drivers/mmc/pic32_sdhci.c +++ b/drivers/mmc/pic32_sdhci.c @@ -6,65 +6,76 @@ * Andrei Pistirica */ -#include #include #include -#include -#include +#include -DECLARE_GLOBAL_DATA_PTR; - -static int pic32_sdhci_get_cd(struct sdhci_host *host) -{ - /* PIC32 SDHCI CD errata: - * - set CD_TEST and clear CD_TEST_INS bit - */ - sdhci_writeb(host, SDHCI_CTRL_CD_TEST, SDHCI_HOST_CONTROL); - - return 0; -} - -static const struct sdhci_ops pic32_sdhci_ops = { - .get_cd = pic32_sdhci_get_cd, +struct pic32_sdhci_plat { + struct mmc_config cfg; + struct mmc mmc; }; static int pic32_sdhci_probe(struct udevice *dev) { + struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); + struct pic32_sdhci_plat *plat = dev_get_platdata(dev); struct sdhci_host *host = dev_get_priv(dev); - const void *fdt = gd->fdt_blob; - u32 f_min_max[2]; - fdt_addr_t addr; - fdt_size_t size; + + struct clk clk; + ulong clk_rate; int ret; - addr = fdtdec_get_addr_size(fdt, dev_of_offset(dev), "reg", &size); - if (addr == FDT_ADDR_T_NONE) - return -EINVAL; - - host->ioaddr = ioremap(addr, size); - host->name = dev->name; - host->quirks = SDHCI_QUIRK_NO_HISPD_BIT; - host->bus_width = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), - "bus-width", 4); - host->ops = &pic32_sdhci_ops; - - ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(dev), - "clock-freq-min-max", f_min_max, 2); - if (ret) { - printf("sdhci: clock-freq-min-max not found\n"); - return ret; - } - - host->max_clk = f_min_max[1]; - - ret = add_sdhci(host, 0, f_min_max[0]); + ret = clk_get_by_name(dev, "base_clk", &clk); if (ret) return ret; + + clk_rate = clk_get_rate(&clk); + clk_free(&clk); + + if (IS_ERR_VALUE(clk_rate)) + return clk_rate; + + host->ioaddr = dev_remap_addr(dev); + + if (!host->ioaddr) + return -EINVAL; + + host->name = dev->name; + host->quirks = SDHCI_QUIRK_NO_HISPD_BIT; + host->bus_width = dev_read_u32_default(dev, "bus-width", 4); + host->max_clk = clk_rate; + + host->mmc = &plat->mmc; host->mmc->dev = dev; + ret = sdhci_setup_cfg(&plat->cfg, host, 0, 0); + if (ret) + return ret; + + host->mmc->priv = host; + upriv->mmc = host->mmc; + + ret = sdhci_probe(dev); + if (ret) + return ret; + + if (!dev_read_bool(dev, "microchip,use-sdcd")) { + // Use workaround 1 for erratum #15 by default + u8 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); + ctrl = (ctrl & ~SDHCI_CTRL_CD_TEST_INS) | SDHCI_CTRL_CD_TEST; + sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); + } + return 0; } +static int pic32_sdhci_bind(struct udevice *dev) +{ + struct pic32_sdhci_plat *plat = dev_get_platdata(dev); + + return sdhci_bind(dev, &plat->mmc, &plat->cfg); +} + static const struct udevice_id pic32_sdhci_ids[] = { { .compatible = "microchip,pic32mzda-sdhci" }, { } @@ -74,6 +85,9 @@ U_BOOT_DRIVER(pic32_sdhci_drv) = { .name = "pic32_sdhci", .id = UCLASS_MMC, .of_match = pic32_sdhci_ids, + .ops = &sdhci_ops, + .bind = pic32_sdhci_bind, .probe = pic32_sdhci_probe, .priv_auto_alloc_size = sizeof(struct sdhci_host), + .platdata_auto_alloc_size = sizeof(struct pic32_sdhci_plat) }; From 10d65bf00beb8609c8d6639c3e60a89b148899e6 Mon Sep 17 00:00:00 2001 From: John Robertson Date: Tue, 1 Sep 2020 02:55:26 +0000 Subject: [PATCH 2/8] pinmux: pic32: add SDHCI pin config The GPIO pins used by the SDHCI controller need to be configured to allow the interface to work. Signed-off-by: John Robertson --- drivers/pinctrl/pinctrl_pic32.c | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/drivers/pinctrl/pinctrl_pic32.c b/drivers/pinctrl/pinctrl_pic32.c index 911af1297b..899c279975 100644 --- a/drivers/pinctrl/pinctrl_pic32.c +++ b/drivers/pinctrl/pinctrl_pic32.c @@ -222,6 +222,31 @@ static void pic32_eth_pin_config(struct udevice *dev) pic32_pinconfig_set(priv, configs, ARRAY_SIZE(configs)); } +static void pic32_sdhci_pin_config(struct udevice *dev) +{ + struct pic32_pinctrl_priv *priv = dev_get_priv(dev); + const struct pic32_pin_config configs[] = { + /* SDWP - H2 */ + PIN_CONFIG(PIC32_PORT_H, 2, PIN_CONFIG_PIC32_DIGITAL), + /* SDCD - A0 */ + PIN_CONFIG(PIC32_PORT_A, 0, PIN_CONFIG_PIC32_DIGITAL), + /* SDCMD - D4 */ + PIN_CONFIG(PIC32_PORT_D, 4, PIN_CONFIG_PIC32_DIGITAL), + /* SDCK - A6 */ + PIN_CONFIG(PIC32_PORT_A, 6, PIN_CONFIG_PIC32_DIGITAL), + /* SDDATA0 - G13 */ + PIN_CONFIG(PIC32_PORT_G, 13, PIN_CONFIG_PIC32_DIGITAL), + /* SDDATA1 - G12 */ + PIN_CONFIG(PIC32_PORT_G, 12, PIN_CONFIG_PIC32_DIGITAL), + /* SDDATA2 - G14 */ + PIN_CONFIG(PIC32_PORT_G, 14, PIN_CONFIG_PIC32_DIGITAL), + /* SDDATA3 - A7 */ + PIN_CONFIG(PIC32_PORT_A, 7, PIN_CONFIG_PIC32_DIGITAL), + }; + + pic32_pinconfig_set(priv, configs, ARRAY_SIZE(configs)); +} + static int pic32_pinctrl_request(struct udevice *dev, int func, int flags) { struct pic32_pinctrl_priv *priv = dev_get_priv(dev); @@ -240,6 +265,9 @@ static int pic32_pinctrl_request(struct udevice *dev, int func, int flags) case PERIPH_ID_ETH: pic32_eth_pin_config(dev); break; + case PERIPH_ID_SDHCI: + pic32_sdhci_pin_config(dev); + break; default: debug("%s: unknown-unhandled case\n", __func__); break; From 69af033fb9ee25201483ed48c52c546779c75c9b Mon Sep 17 00:00:00 2001 From: John Robertson Date: Tue, 1 Sep 2020 02:55:42 +0000 Subject: [PATCH 3/8] mips: pic32mzdask: disable SDHCI SDCD signal workaround The PIC32MZ DA Starter Kit does not need the card detect workaround because the SDCD signal line is connected properly. Disable the workaround in this case. Signed-off-by: John Robertson --- arch/mips/dts/pic32mzda_sk.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/mips/dts/pic32mzda_sk.dts b/arch/mips/dts/pic32mzda_sk.dts index b3c916a6db..fc86154e0a 100644 --- a/arch/mips/dts/pic32mzda_sk.dts +++ b/arch/mips/dts/pic32mzda_sk.dts @@ -40,6 +40,7 @@ }; &sdhci { + microchip,use-sdcd; status = "okay"; }; From 95e714129434d8718500ad5d9faffc6507ffb0ce Mon Sep 17 00:00:00 2001 From: John Robertson Date: Tue, 1 Sep 2020 02:55:56 +0000 Subject: [PATCH 4/8] mips: pic32mzdask: enable CONFIG_BLK CONFIG_BLK needs to be enabled by default to allow U-Boot to compile after a 'make pic32mzdask_defconfig'. Signed-off-by: John Robertson --- configs/pic32mzdask_defconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/configs/pic32mzdask_defconfig b/configs/pic32mzdask_defconfig index 7bf61e2d8d..6ff1ee3489 100644 --- a/configs/pic32mzdask_defconfig +++ b/configs/pic32mzdask_defconfig @@ -27,7 +27,6 @@ CONFIG_CMD_EXT4_WRITE=y # CONFIG_EFI_PARTITION is not set CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y -# CONFIG_BLK is not set CONFIG_CLK=y CONFIG_MMC=y CONFIG_DM_MMC=y From 0723c2ddeb8a5446a4b32e7583461efe50d0fe6c Mon Sep 17 00:00:00 2001 From: John Robertson Date: Tue, 1 Sep 2020 04:14:56 +0000 Subject: [PATCH 5/8] mips: dts: Fix device tree warnings for PIC32MZDA Signed-off-by: John Robertson --- arch/mips/dts/pic32mzda.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/mips/dts/pic32mzda.dtsi b/arch/mips/dts/pic32mzda.dtsi index 4c8b7a9a0b..8aff9eb812 100644 --- a/arch/mips/dts/pic32mzda.dtsi +++ b/arch/mips/dts/pic32mzda.dtsi @@ -26,8 +26,13 @@ }; cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu@0 { compatible = "mips,mips14kc"; + device-type = "cpu"; + reg = <0>; }; }; @@ -40,6 +45,7 @@ uart1: serial@1f822000 { compatible = "microchip,pic32mzda-uart"; reg = <0x1f822000 0x50>; + interrupt-parent = <&evic>; interrupts = <112 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; clocks = <&clock PB2CLK>; @@ -48,6 +54,7 @@ uart2: serial@1f822200 { compatible = "microchip,pic32mzda-uart"; reg = <0x1f822200 0x50>; + interrupt-parent = <&evic>; interrupts = <145 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock PB2CLK>; status = "disabled"; @@ -56,6 +63,7 @@ uart6: serial@1f822a00 { compatible = "microchip,pic32mzda-uart"; reg = <0x1f822a00 0x50>; + interrupt-parent = <&evic>; interrupts = <188 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock PB2CLK>; status = "disabled"; @@ -153,6 +161,7 @@ sdhci: sdhci@1f8ec000 { compatible = "microchip,pic32mzda-sdhci"; reg = <0x1f8ec000 0x100>; + interrupt-parent = <&evic>; interrupts = <191 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock REF4CLK>, <&clock PB5CLK>; clock-names = "base_clk", "sys_clk"; @@ -164,6 +173,7 @@ ethernet: ethernet@1f882000 { compatible = "microchip,pic32mzda-eth"; reg = <0x1f882000 0x1000>; + interrupt-parent = <&evic>; interrupts = <153 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock PB5CLK>; status = "disabled"; @@ -176,6 +186,7 @@ reg = <0x1f8e3000 0x1000>, <0x1f884000 0x1000>; reg-names = "mc", "control"; + interrupt-parent = <&evic>; interrupts = <132 IRQ_TYPE_EDGE_RISING>, <133 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock PB5CLK>; From 81b543a4e61013fb87f5bdb526d815f1e014d0a4 Mon Sep 17 00:00:00 2001 From: John Robertson Date: Tue, 1 Sep 2020 18:02:13 +0000 Subject: [PATCH 6/8] mips: dts: Fix PIC32MZDA GPIO register definitions GPIO state cannot be changed via the device tree (e.g. with gpio-hog) or using the 'gpio' command from the console. The root cause is a discrepancy between the driver and the device tree: the driver code expects an absolute I/O address in the property, while the device tree defines the address relative to a declaration in the parent pinctrl node. Changing the device tree to fix a driver issue would normally be wrong, however: - I have run the first version of U-Boot in which this driver appears (v2016.03) and the same problem exists, so this is not a regression; - There is no code that references a parent device tree node that might suggest the intent of the author was to parse the DT as it exists now; - The equivalent Linux PIC32 GPIO driver also uses absolute addresses for the GPIO property. This change brings the U-Boot DT more into line with Linux. Additionally, the data sheet (Microchip ref. 60001361H) shows that the register set to control a GPIO bank spans 0xE0 bytes, but the device tree specified size is only 0x48 bytes. Signed-off-by: John Robertson --- arch/mips/dts/pic32mzda.dtsi | 45 ++++++++++++++++++------------------ 1 file changed, 22 insertions(+), 23 deletions(-) diff --git a/arch/mips/dts/pic32mzda.dtsi b/arch/mips/dts/pic32mzda.dtsi index 8aff9eb812..cd156de848 100644 --- a/arch/mips/dts/pic32mzda.dtsi +++ b/arch/mips/dts/pic32mzda.dtsi @@ -77,6 +77,8 @@ }; pinctrl: pinctrl@1f801400 { + #address-cells = <1>; + #size-cells = <1>; compatible = "microchip,pic32mzda-pinctrl"; reg = <0x1f801400 0x100>, /* in */ <0x1f801500 0x200>, /* out */ @@ -84,75 +86,72 @@ reg-names = "ppsin","ppsout","port"; status = "disabled"; - ranges = <0 0x1f860000 0xa00>; - #address-cells = <1>; - #size-cells = <1>; - gpioA: gpio0@0 { + gpioA: gpio0@1f860000 { compatible = "microchip,pic32mzda-gpio"; - reg = <0x000 0x48>; + reg = <0x1f860000 0xe0>; gpio-controller; #gpio-cells = <2>; }; - gpioB: gpio1@100 { + gpioB: gpio1@1f860100 { compatible = "microchip,pic32mzda-gpio"; - reg = <0x100 0x48>; + reg = <0x1f860100 0xe0>; gpio-controller; #gpio-cells = <2>; }; - gpioC: gpio2@200 { + gpioC: gpio2@1f860200 { compatible = "microchip,pic32mzda-gpio"; - reg = <0x200 0x48>; + reg = <0x1f860200 0xe0>; gpio-controller; #gpio-cells = <2>; }; - gpioD: gpio3@300 { + gpioD: gpio3@1f860300 { compatible = "microchip,pic32mzda-gpio"; - reg = <0x300 0x48>; + reg = <0x1f860300 0xe0>; gpio-controller; #gpio-cells = <2>; }; - gpioE: gpio4@400 { + gpioE: gpio4@1f860400 { compatible = "microchip,pic32mzda-gpio"; - reg = <0x400 0x48>; + reg = <0x1f860400 0xe0>; gpio-controller; #gpio-cells = <2>; }; - gpioF: gpio5@500 { + gpioF: gpio5@1f860500 { compatible = "microchip,pic32mzda-gpio"; - reg = <0x500 0x48>; + reg = <0x1f860500 0xe0>; gpio-controller; #gpio-cells = <2>; }; - gpioG: gpio6@600 { + gpioG: gpio6@1f860600 { compatible = "microchip,pic32mzda-gpio"; - reg = <0x600 0x48>; + reg = <0x1f860600 0xe0>; gpio-controller; #gpio-cells = <2>; }; - gpioH: gpio7@700 { + gpioH: gpio7@1f860700 { compatible = "microchip,pic32mzda-gpio"; - reg = <0x700 0x48>; + reg = <0x1f860700 0xe0>; gpio-controller; #gpio-cells = <2>; }; - gpioJ: gpio8@800 { + gpioJ: gpio8@1f860800 { compatible = "microchip,pic32mzda-gpio"; - reg = <0x800 0x48>; + reg = <0x1f860800 0xe0>; gpio-controller; #gpio-cells = <2>; }; - gpioK: gpio9@900 { + gpioK: gpio9@1f860900 { compatible = "microchip,pic32mzda-gpio"; - reg = <0x900 0x48>; + reg = <0x1f860900 0xe0>; gpio-controller; #gpio-cells = <2>; }; From bd25f9a69fa5accde66cf914154bdd64604d8f64 Mon Sep 17 00:00:00 2001 From: John Robertson Date: Tue, 1 Sep 2020 18:02:20 +0000 Subject: [PATCH 7/8] mips: dts: Fix PIC32MZDA GPIO register definitions The GPIO bank name for banks J and K are not correct when using the 'gpio' command from the console. The driver derives the bank name from the device tree instance string by using the instance value and adding 'A': gpio0@xxaddrxx is Bank A, gpio1@yyaddryy is Bank B and so on. On the PIC32, there is no Bank I so instances 8 and 9 need to be incremented as a minimum change. An alternative (less opaque) implementation would be to use a bank-name property instead but this would require modifying the driver code too. Signed-off-by: John Robertson --- arch/mips/dts/pic32mzda.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/mips/dts/pic32mzda.dtsi b/arch/mips/dts/pic32mzda.dtsi index cd156de848..43cd7cf304 100644 --- a/arch/mips/dts/pic32mzda.dtsi +++ b/arch/mips/dts/pic32mzda.dtsi @@ -142,14 +142,14 @@ #gpio-cells = <2>; }; - gpioJ: gpio8@1f860800 { + gpioJ: gpio9@1f860800 { compatible = "microchip,pic32mzda-gpio"; reg = <0x1f860800 0xe0>; gpio-controller; #gpio-cells = <2>; }; - gpioK: gpio9@1f860900 { + gpioK: gpio10@1f860900 { compatible = "microchip,pic32mzda-gpio"; reg = <0x1f860900 0xe0>; gpio-controller; From 7d1538cc9bb87d12dcd8c9f9b07c17bb510042ef Mon Sep 17 00:00:00 2001 From: Mauro Condarelli Date: Sun, 20 Sep 2020 18:28:59 +0200 Subject: [PATCH 8/8] mips: vocore2: fix various issues - fix SPL image generation - fix incorrect console output - increase malloc_f and malloc_r space to fix LZMA decompression errors - increase SPI flash clock Signed-off-by: Mauro Condarelli [squashed to one patch, fix commit subject and description] Signed-off-by: Daniel Schwierzeck --- arch/mips/dts/vocore_vocore2.dts | 2 +- configs/vocore2_defconfig | 2 +- include/configs/vocore2.h | 4 +++- 3 files changed, 5 insertions(+), 3 deletions(-) diff --git a/arch/mips/dts/vocore_vocore2.dts b/arch/mips/dts/vocore_vocore2.dts index 3502e4b8b7..9adf39652f 100644 --- a/arch/mips/dts/vocore_vocore2.dts +++ b/arch/mips/dts/vocore_vocore2.dts @@ -59,7 +59,7 @@ #address-cells = <1>; #size-cells = <1>; compatible = "jedec,spi-nor"; - spi-max-frequency = <25000000>; + spi-max-frequency = <40000000>; reg = <0>; }; }; diff --git a/configs/vocore2_defconfig b/configs/vocore2_defconfig index 99a1143e6e..5776aada15 100644 --- a/configs/vocore2_defconfig +++ b/configs/vocore2_defconfig @@ -6,7 +6,7 @@ CONFIG_ENV_SIZE=0x1000 CONFIG_ENV_OFFSET=0x04e000 CONFIG_ENV_SECT_SIZE=0x1000 CONFIG_SYS_BOOTCOUNT_ADDR=0xb000006c -CONFIG_SPL_SYS_MALLOC_F_LEN=0x20000 +CONFIG_SPL_SYS_MALLOC_F_LEN=0x40000 CONFIG_SPL=y CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y CONFIG_ARCH_MTMIPS=y diff --git a/include/configs/vocore2.h b/include/configs/vocore2.h index 40467b737c..dfdb8fcc04 100644 --- a/include/configs/vocore2.h +++ b/include/configs/vocore2.h @@ -25,6 +25,7 @@ #define CONFIG_SPL_BSS_START_ADDR 0x80010000 #define CONFIG_SPL_BSS_MAX_SIZE 0x10000 #define CONFIG_SPL_MAX_SIZE 0x10000 +#define CONFIG_SPL_PAD_TO 0 /* Dummy value */ #define CONFIG_SYS_UBOOT_BASE 0 @@ -34,12 +35,13 @@ #define CONFIG_SYS_NS16550_CLK 40000000 #define CONFIG_SYS_NS16550_REG_SIZE -4 #define CONFIG_SYS_NS16550_COM3 0xb0000e00 +#define CONFIG_CONS_INDEX 3 /* RAM */ /* Memory usage */ #define CONFIG_SYS_MAXARGS 64 -#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) +#define CONFIG_SYS_MALLOC_LEN (16 * 1024 * 1024) #define CONFIG_SYS_BOOTPARAMS_LEN (128 * 1024) #define CONFIG_SYS_CBSIZE 512