mirror of
https://github.com/Fishwaldo/u-boot.git
synced 2025-03-18 13:11:31 +00:00
Merge branch 'master' of git://git.denx.de/u-boot-sh
This commit is contained in:
commit
55aea84b1d
27 changed files with 67 additions and 12 deletions
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@ -91,7 +91,7 @@ int cache_control(unsigned int cmd)
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return 0;
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}
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void dcache_wback_range(u32 start, u32 end)
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void flush_dcache_range(unsigned long start, unsigned long end)
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{
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u32 v;
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@ -102,7 +102,7 @@ void dcache_wback_range(u32 start, u32 end)
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}
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}
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void dcache_invalid_range(u32 start, u32 end)
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void invalidate_dcache_range(unsigned long start, unsigned long end)
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{
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u32 v;
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@ -41,7 +41,7 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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void flush_cache (unsigned long addr, unsigned long size)
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{
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dcache_invalid_range( addr , addr + size );
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invalidate_dcache_range(addr , addr + size);
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}
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void icache_enable (void)
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@ -10,9 +10,6 @@ int cache_control(unsigned int cmd);
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struct __large_struct { unsigned long buf[100]; };
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#define __m(x) (*(struct __large_struct *)(x))
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void dcache_wback_range(u32 start, u32 end);
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void dcache_invalid_range(u32 start, u32 end);
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#else
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/*
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@ -17,15 +17,17 @@
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#include <asm/io.h>
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#include <sh_tmu.h>
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#define TCR_TPSC 0x07
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static struct tmu_regs *tmu = (struct tmu_regs *)TMU_BASE;
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static u16 bit;
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static unsigned long last_tcnt;
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static unsigned long long overflow_ticks;
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unsigned long get_tbclk(void)
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{
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return get_tmu0_clk_rate() >> ((bit + 1) * 2);
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u16 tmu_bit = (ffs(CONFIG_SYS_TMU_CLK_DIV) >> 1) - 1;
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return get_tmu0_clk_rate() >> ((tmu_bit + 1) * 2);
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}
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static inline unsigned long long tick_to_time(unsigned long long tick)
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@ -60,8 +62,8 @@ static void tmu_timer_stop(unsigned int timer)
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int timer_init(void)
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{
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bit = (ffs(CONFIG_SYS_TMU_CLK_DIV) >> 1) - 1;
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writew(readw(&tmu->tcr0) | bit, &tmu->tcr0);
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u16 tmu_bit = (ffs(CONFIG_SYS_TMU_CLK_DIV) >> 1) - 1;
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writew((readw(&tmu->tcr0) & ~TCR_TPSC) | tmu_bit, &tmu->tcr0);
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tmu_timer_stop(0);
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tmu_timer_start(0);
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@ -1,5 +1,6 @@
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/*
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* SuperH SCIF device driver.
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* Copyright (C) 2013 Renesas Electronics Corporation
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* Copyright (C) 2007,2008,2010 Nobuhiro Iwamatsu
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* Copyright (C) 2002 - 2008 Paul Mundt
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*
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@ -48,7 +49,9 @@ static struct uart_port sh_sci = {
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static void sh_serial_setbrg(void)
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{
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DECLARE_GLOBAL_DATA_PTR;
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sci_out(&sh_sci, SCBRR, SCBRR_VALUE(gd->baudrate, CONFIG_SYS_CLK_FREQ));
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sci_out(&sh_sci, SCBRR,
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SCBRR_VALUE(gd->baudrate, CONFIG_SH_SCIF_CLK_FREQ));
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}
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static int sh_serial_init(void)
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@ -224,6 +224,9 @@ struct uart_port {
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# define SCSPTR3 0xffc60020 /* 16 bit SCIF */
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# define SCIF_ORER 0x0001 /* Overrun error bit */
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# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
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#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791)
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# define SCIF_ORER 0x0001
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# define SCSCR_INIT(port) 0x32 /* TIE=0,RIE=0,TE=1,RE=1,REIE=0, */
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#else
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# error CPU subtype not defined
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#endif
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@ -298,6 +301,9 @@ struct uart_port {
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/* SH7763 SCIF2 support */
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# define SCIF2_RFDC_MASK 0x001f
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# define SCIF2_TXROOM_MAX 16
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#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791)
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# define SCIF_ERRORS (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK)
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# define SCIF_RFDC_MASK 0x003f
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#else
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# define SCIF_ERRORS (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK)
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# define SCIF_RFDC_MASK 0x001f
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@ -579,6 +585,10 @@ SCIF_FNS(SCSPTR, 0, 0, 0, 0)
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#else
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SCIF_FNS(SCSPTR, 0, 0, 0x20, 16)
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#endif
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#if defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791)
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SCIF_FNS(DL, 0, 0, 0x30, 16)
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SCIF_FNS(CKS, 0, 0, 0x34, 16)
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#endif
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SCIF_FNS(SCLSR, 0, 0, 0x24, 16)
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#endif
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#endif
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@ -720,6 +730,9 @@ static inline int scbrr_calc(struct uart_port port, int bps, int clk)
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#define SCBRR_VALUE(bps, clk) scbrr_calc(sh_sci, bps, clk)
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#elif defined(__H8300H__) || defined(__H8300S__)
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#define SCBRR_VALUE(bps, clk) (((clk*1000/32)/bps)-1)
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#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791)
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#define SCBRR DL
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#define SCBRR_VALUE(bps, clk) (clk / bps / 16)
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#else /* Generic SH */
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#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1)
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#endif
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@ -123,6 +123,8 @@
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/* Board Clock */
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#define CONFIG_SYS_CLK_FREQ 33333333
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#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
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#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
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#define CONFIG_SYS_TMU_CLK_DIV (4) /* 4 (default), 16, 64, 256 or 1024 */
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#define CONFIG_SYS_HZ 1000
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@ -155,6 +155,8 @@
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/* Board Clock */
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#define CONFIG_SYS_CLK_FREQ 33333333
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#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
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#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
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#define CONFIG_SYS_TMU_CLK_DIV (4) /* 4 (default), 16, 64, 256 or 1024 */
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#define CONFIG_SYS_HZ 1000
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@ -158,6 +158,8 @@
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#else
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#define CONFIG_SYS_CLK_FREQ 44444444
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#endif
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#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
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#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
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#define CONFIG_SYS_TMU_CLK_DIV 4
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#define CONFIG_SYS_HZ 1000
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@ -179,6 +179,8 @@
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/* Board Clock */
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#define CONFIG_SYS_CLK_FREQ 41666666
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#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
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#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
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#define CONFIG_SYS_TMU_CLK_DIV 4
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#define CONFIG_SYS_HZ 1000
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@ -98,6 +98,8 @@
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/* Clock */
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#define CONFIG_SYS_CLK_FREQ 66666666
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#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
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#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
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#define CONFIG_SYS_TMU_CLK_DIV 4
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#define CONFIG_SYS_HZ 1000
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@ -67,6 +67,8 @@
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/* Clocks */
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#define CONFIG_SYS_CLK_FREQ 24000000
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#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
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#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
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#define CONFIG_SYS_TMU_CLK_DIV 4 /* 4 (default), 16, 64, 256 or 1024 */
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#define CONFIG_SYS_HZ 1000
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@ -85,6 +85,8 @@
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/* Board Clock */
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#define CONFIG_SYS_CLK_FREQ 33333333
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#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
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#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
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#define CONFIG_SYS_TMU_CLK_DIV 4 /* 4 (default), 16, 64, 256 or 1024 */
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#define CONFIG_SYS_HZ 1000
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@ -111,6 +111,8 @@
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/* Board Clock */
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#define CONFIG_SYS_CLK_FREQ 33333333
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#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
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#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
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#define CONFIG_SYS_TMU_CLK_DIV (4) /* 4 (default), 16, 64, 256 or 1024 */
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#define CONFIG_SYS_HZ 1000
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@ -82,6 +82,8 @@
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/* Board Clock */
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#define CONFIG_SYS_CLK_FREQ 33333333
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#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
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#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
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#define CONFIG_SYS_TMU_CLK_DIV 4
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#define CONFIG_SYS_HZ 1000
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@ -164,6 +164,8 @@
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#else
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#define CONFIG_SYS_CLK_FREQ 44444444
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#endif
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#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
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#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
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#define CONFIG_SYS_TMU_CLK_DIV 4
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#define CONFIG_SYS_HZ 1000
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@ -77,6 +77,8 @@
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* SuperH Clock setting
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*/
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#define CONFIG_SYS_CLK_FREQ 60000000
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#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
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#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
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#define CONFIG_SYS_TMU_CLK_DIV 4
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#define CONFIG_SYS_HZ 1000
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#define CONFIG_SYS_PLL_SETTLING_TIME 100/* in us */
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@ -102,6 +102,8 @@
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/* Board Clock */
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#define CONFIG_SYS_CLK_FREQ 33333333
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#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
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#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
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#define CONFIG_SYS_TMU_CLK_DIV 4
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#define CONFIG_SYS_HZ 1000
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@ -85,6 +85,8 @@
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/* Board Clock */
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#define CONFIG_SYS_CLK_FREQ 33333333
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#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
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#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
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#define CMT_CLK_DIVIDER 32 /* 8 (default), 32, 128 or 512 */
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#define CONFIG_SYS_HZ (CONFIG_SYS_CLK_FREQ / CMT_CLK_DIVIDER)
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@ -65,6 +65,8 @@
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/* Board Clock */
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#define CONFIG_SYS_CLK_FREQ 36000000
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#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
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#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
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#define CMT_CLK_DIVIDER 32 /* 8 (default), 32, 128 or 512 */
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#define CONFIG_SYS_HZ (CONFIG_SYS_CLK_FREQ / CMT_CLK_DIVIDER)
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@ -64,6 +64,8 @@
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/* Board Clock */
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#define CONFIG_SYS_CLK_FREQ 66125000
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#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
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#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
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#define CMT_CLK_DIVIDER 32 /* 8 (default), 32, 128 or 512 */
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#define CONFIG_SYS_HZ (CONFIG_SYS_CLK_FREQ / CMT_CLK_DIVIDER)
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@ -132,6 +132,8 @@
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/* Board Clock */
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#define CONFIG_SYS_CLK_FREQ 48000000
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#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
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#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
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#define CONFIG_SYS_TMU_CLK_DIV 4
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#define CONFIG_SYS_HZ 1000
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#endif /* __SH7752EVB_H */
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@ -140,6 +140,8 @@
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/* Board Clock */
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#define CONFIG_SYS_CLK_FREQ 48000000
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#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
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#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
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#define CONFIG_SYS_TMU_CLK_DIV 4
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#define CONFIG_SYS_HZ 1000
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#endif /* __SH7757LCR_H */
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@ -98,6 +98,8 @@
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/* Clock */
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#define CONFIG_SYS_CLK_FREQ 66666666
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#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
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#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
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#define CONFIG_SYS_TMU_CLK_DIV (4) /* 4 (default), 16, 64, 256 or 1024 */
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#define CONFIG_SYS_HZ 1000
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@ -172,6 +172,8 @@
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/* Board Clock */
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/* The SCIF used external clock. system clock only used timer. */
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#define CONFIG_SYS_CLK_FREQ 50000000
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#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
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#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
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#define CONFIG_SYS_TMU_CLK_DIV 4
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#define CONFIG_SYS_HZ 1000
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@ -103,6 +103,8 @@
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#else
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#define CONFIG_SYS_CLK_FREQ 33333333
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#endif /* CONFIG_T_SH7706LSR */
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#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
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#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
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#define CONFIG_SYS_TMU_CLK_DIV 4
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#define CONFIG_SYS_HZ 1000
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@ -69,7 +69,7 @@ struct tmu_regs {
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static inline unsigned long get_tmu0_clk_rate(void)
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{
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return CONFIG_SYS_CLK_FREQ;
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return CONFIG_SH_TMU_CLK_FREQ;
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}
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#endif /* __SH_TMU_H */
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