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x86: Add queensbay and crownbay Kconfig files
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
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@ -32,6 +32,15 @@ config TARGET_CHROMEBOOK_LINK
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and it provides a 2560x1700 high resolution touch-enabled LCD
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and it provides a 2560x1700 high resolution touch-enabled LCD
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display.
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display.
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config TARGET_CROWNBAY
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bool "Support Intel Crown Bay CRB"
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help
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This is the Intel Crown Bay Customer Reference Board. It contains
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the Intel Atom Processor E6xx populated on the COM Express module
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with 1GB DDR2 soldered down memory and a carrier board with the
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Intel Platform Controller Hub EG20T, other system components and
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peripheral connectors for PCIe/SATA/USB/LAN/SD/UART/Audio/LVDS.
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endchoice
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endchoice
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config RAMBASE
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config RAMBASE
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@ -310,8 +319,12 @@ endmenu
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source "arch/x86/cpu/ivybridge/Kconfig"
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source "arch/x86/cpu/ivybridge/Kconfig"
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source "arch/x86/cpu/queensbay/Kconfig"
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source "board/coreboot/coreboot/Kconfig"
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source "board/coreboot/coreboot/Kconfig"
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source "board/google/chromebook_link/Kconfig"
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source "board/google/chromebook_link/Kconfig"
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source "board/intel/crownbay/Kconfig"
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endmenu
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endmenu
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79
arch/x86/cpu/queensbay/Kconfig
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79
arch/x86/cpu/queensbay/Kconfig
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@ -0,0 +1,79 @@
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#
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# Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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config INTEL_QUEENSBAY
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bool
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select HAVE_FSP
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select HAVE_CMC
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if INTEL_QUEENSBAY
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config HAVE_FSP
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bool "Add an Firmware Support Package binary"
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help
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Select this option to add an Firmware Support Package binary to
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the resulting U-Boot image. It is a binary blob which U-Boot uses
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to set up SDRAM and other chipset specific initialization.
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Note: Without this binary U-Boot will not be able to set up its
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SDRAM so will not boot.
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config FSP_FILE
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string "Firmware Support Package binary filename"
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depends on HAVE_FSP
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default "fsp.bin"
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help
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The filename of the file to use as Firmware Support Package binary
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in the board directory.
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config FSP_LOCATION
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hex "Firmware Support Package binary location"
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depends on HAVE_FSP
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default 0xfffc0000
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help
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FSP is not Position Independent Code (PIC) and the whole FSP has to
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be rebased if it is placed at a location which is different from the
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perferred base address specified during the FSP build. Use Intel's
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Binary Configuration Tool (BCT) to do the rebase.
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The default base address of 0xfffc0000 indicates that the binary must
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be located at offset 0xc0000 from the beginning of a 1MB flash device.
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config FSP_TEMP_RAM_ADDR
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hex
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default 0x2000000
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help
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Stack top address which is used in FspInit after DRAM is ready and
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CAR is disabled.
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config HAVE_CMC
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bool "Add a Chipset Micro Code state machine binary"
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help
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Select this option to add a Chipset Micro Code state machine binary
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to the resulting U-Boot image. It is a 64K data block of machine
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specific code which must be put in the flash for the processor to
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access when powered up before system BIOS is executed.
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config CMC_FILE
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string "Chipset Micro Code state machine filename"
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depends on HAVE_CMC
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default "cmc.bin"
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help
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The filename of the file to use as Chipset Micro Code state machine
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binary in the board directory.
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config CMC_LOCATION
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hex "Chipset Micro Code state machine binary location"
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depends on HAVE_CMC
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default 0xfffb0000
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help
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The location of the CMC binary is determined by a strap. It must be
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put in flash at a location matching the strap-determined base address.
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The default base address of 0xfffb0000 indicates that the binary must
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be located at offset 0xb0000 from the beginning of a 1MB flash device.
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endif
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20
board/intel/crownbay/Kconfig
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20
board/intel/crownbay/Kconfig
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@ -0,0 +1,20 @@
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if TARGET_CROWNBAY
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config SYS_BOARD
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default "crownbay"
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config SYS_VENDOR
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default "intel"
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config SYS_SOC
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default "queensbay"
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config SYS_CONFIG_NAME
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default "crownbay"
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config BOARD_SPECIFIC_OPTIONS # dummy
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def_bool y
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select INTEL_QUEENSBAY
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select BOARD_ROMSIZE_KB_1024
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endif
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