mirror of
https://github.com/Fishwaldo/u-boot.git
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arm: dts: sunxi: h5: Update DT files
Update the H5 DT files from the Linux 5.12 release. The changes don't affect U-Boot at all, but fix Gigabit Ethernet when this DT is passed on to the Linux kernel. It also introduces DVFS. This also updates the shared sunxi-h3-h5.dtsi, but that only adds nodes that are of no concern to U-Boot. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
This commit is contained in:
parent
127e57c671
commit
58f68611df
13 changed files with 296 additions and 24 deletions
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@ -3,6 +3,7 @@
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/dts-v1/;
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#include "sun50i-h5.dtsi"
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#include "sun50i-h5-cpu-opp.dtsi"
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#include <arm/sunxi-bananapi-m2-plus-v1.2.dtsi>
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/ {
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79
arch/arm/dts/sun50i-h5-cpu-opp.dtsi
Normal file
79
arch/arm/dts/sun50i-h5-cpu-opp.dtsi
Normal file
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@ -0,0 +1,79 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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// Copyright (C) 2020 Chen-Yu Tsai <wens@csie.org>
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/ {
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cpu_opp_table: cpu-opp-table {
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compatible = "operating-points-v2";
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opp-shared;
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opp-408000000 {
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opp-hz = /bits/ 64 <408000000>;
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opp-microvolt = <1000000 1000000 1310000>;
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clock-latency-ns = <244144>; /* 8 32k periods */
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};
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opp-648000000 {
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opp-hz = /bits/ 64 <648000000>;
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opp-microvolt = <1040000 1040000 1310000>;
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clock-latency-ns = <244144>; /* 8 32k periods */
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};
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opp-816000000 {
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opp-hz = /bits/ 64 <816000000>;
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opp-microvolt = <1080000 1080000 1310000>;
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clock-latency-ns = <244144>; /* 8 32k periods */
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};
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opp-912000000 {
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opp-hz = /bits/ 64 <912000000>;
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opp-microvolt = <1120000 1120000 1310000>;
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clock-latency-ns = <244144>; /* 8 32k periods */
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};
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opp-960000000 {
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opp-hz = /bits/ 64 <960000000>;
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opp-microvolt = <1160000 1160000 1310000>;
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clock-latency-ns = <244144>; /* 8 32k periods */
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};
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opp-1008000000 {
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opp-hz = /bits/ 64 <1008000000>;
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opp-microvolt = <1200000 1200000 1310000>;
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clock-latency-ns = <244144>; /* 8 32k periods */
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};
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opp-1056000000 {
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opp-hz = /bits/ 64 <1056000000>;
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opp-microvolt = <1240000 1240000 1310000>;
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clock-latency-ns = <244144>; /* 8 32k periods */
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};
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opp-1104000000 {
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opp-hz = /bits/ 64 <1104000000>;
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opp-microvolt = <1260000 1260000 1310000>;
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clock-latency-ns = <244144>; /* 8 32k periods */
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};
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opp-1152000000 {
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opp-hz = /bits/ 64 <1152000000>;
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opp-microvolt = <1300000 1300000 1310000>;
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clock-latency-ns = <244144>; /* 8 32k periods */
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};
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};
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};
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&cpu0 {
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operating-points-v2 = <&cpu_opp_table>;
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};
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&cpu1 {
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operating-points-v2 = <&cpu_opp_table>;
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};
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&cpu2 {
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operating-points-v2 = <&cpu_opp_table>;
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};
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&cpu3 {
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operating-points-v2 = <&cpu_opp_table>;
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};
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@ -4,6 +4,7 @@
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/dts-v1/;
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#include "sun50i-h5.dtsi"
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#include "sun50i-h5-cpu-opp.dtsi"
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#include <sunxi-libretech-all-h3-cc.dtsi>
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/ {
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@ -36,7 +36,7 @@
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pinctrl-0 = <&emac_rgmii_pins>;
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phy-supply = <®_gmac_3v3>;
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phy-handle = <&ext_rgmii_phy>;
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phy-mode = "rgmii";
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phy-mode = "rgmii-id";
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/delete-property/ allwinner,leds-active-low;
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status = "okay";
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};
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@ -25,13 +25,13 @@
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leds {
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compatible = "gpio-leds";
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pwr {
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led-0 {
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label = "nanopi:green:pwr";
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gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>;
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default-state = "on";
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};
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status {
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led-1 {
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label = "nanopi:red:status";
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gpios = <&pio 0 20 GPIO_ACTIVE_HIGH>;
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};
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@ -96,7 +96,7 @@
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pinctrl-0 = <&emac_rgmii_pins>;
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phy-supply = <®_gmac_3v3>;
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phy-handle = <&ext_rgmii_phy>;
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phy-mode = "rgmii";
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phy-mode = "rgmii-id";
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status = "okay";
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};
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@ -22,13 +22,13 @@
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leds {
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compatible = "gpio-leds";
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pwr {
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led-0 {
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label = "nanopi:green:pwr";
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gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>;
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default-state = "on";
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};
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status {
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led-1 {
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label = "nanopi:blue:status";
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gpios = <&pio 0 10 GPIO_ACTIVE_HIGH>;
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};
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@ -42,13 +42,13 @@
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leds {
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compatible = "gpio-leds";
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pwr {
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led-0 {
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label = "orangepi:green:pwr";
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gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>;
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default-state = "on";
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};
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status {
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led-1 {
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label = "orangepi:red:status";
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gpios = <&pio 0 20 GPIO_ACTIVE_HIGH>;
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};
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label = "sw4";
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linux,code = <BTN_0>;
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gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;
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wakeup-source;
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};
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};
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status = "okay";
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};
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&cpu0 {
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cpu-supply = <®_vdd_cpux>;
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};
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&de {
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status = "okay";
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};
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pinctrl-0 = <&emac_rgmii_pins>;
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phy-supply = <®_gmac_3v3>;
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phy-handle = <&ext_rgmii_phy>;
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phy-mode = "rgmii";
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phy-mode = "rgmii-id";
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status = "okay";
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};
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status = "okay";
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};
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&r_i2c {
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status = "okay";
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reg_vdd_cpux: regulator@65 {
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compatible = "silergy,sy8106a";
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reg = <0x65>;
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regulator-name = "vdd-cpux";
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silergy,fixed-microvolt = <1100000>;
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regulator-min-microvolt = <1000000>;
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regulator-max-microvolt = <1400000>;
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regulator-ramp-delay = <200>;
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regulator-boot-on;
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regulator-always-on;
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};
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};
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&spi0 {
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status = "okay";
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leds {
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compatible = "gpio-leds";
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pwr {
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led-0 {
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label = "orangepi:green:pwr";
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gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>;
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default-state = "on";
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};
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status {
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led-1 {
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label = "orangepi:red:status";
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gpios = <&pio 0 20 GPIO_ACTIVE_HIGH>;
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};
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pinctrl-0 = <&emac_rgmii_pins>;
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phy-supply = <®_gmac_3v3>;
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phy-handle = <&ext_rgmii_phy>;
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phy-mode = "rgmii";
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phy-mode = "rgmii-id";
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status = "okay";
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};
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leds {
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compatible = "gpio-leds";
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pwr {
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led-0 {
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label = "orangepi:green:pwr";
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gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; /* PA10 */
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default-state = "on";
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};
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status {
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led-1 {
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label = "orangepi:red:status";
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gpios = <&pio 0 17 GPIO_ACTIVE_HIGH>; /* PA17 */
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};
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};
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};
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leds {
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compatible = "gpio-leds";
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led-0 {
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label = "orangepi:green:pwr";
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gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>;
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default-state = "on";
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};
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led-1 {
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label = "orangepi:red:status";
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gpios = <&pio 0 17 GPIO_ACTIVE_HIGH>;
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};
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};
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reg_vcc3v3: vcc3v3 {
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compatible = "regulator-fixed";
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regulator-name = "vcc3v3";
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status = "okay";
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};
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&ehci0 {
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status = "okay";
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};
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&hdmi {
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status = "okay";
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};
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status = "okay";
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};
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&ohci0 {
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status = "okay";
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};
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&uart0 {
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pinctrl-names = "default";
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pinctrl-0 = <&uart0_pa_pins>;
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pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>;
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status = "okay";
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};
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&usb_otg {
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/*
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* According to schematics CN1 MicroUSB port can be used to take
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* external 5V to power up the board VBUS. On the contrary CN1 MicroUSB
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* port cannot provide power externally even if the board is powered
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* via GPIO pins. It thus makes sense to force peripheral mode.
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*/
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dr_mode = "peripheral";
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status = "okay";
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};
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&usbphy {
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status = "okay";
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};
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#include <sunxi-h3-h5.dtsi>
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#include <dt-bindings/thermal/thermal.h>
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/ {
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cpus {
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#address-cells = <1>;
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device_type = "cpu";
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reg = <0>;
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enable-method = "psci";
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clocks = <&ccu CLK_CPUX>;
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clock-latency-ns = <244144>; /* 8 32k periods */
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#cooling-cells = <2>;
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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reg = <1>;
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enable-method = "psci";
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clocks = <&ccu CLK_CPUX>;
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clock-latency-ns = <244144>; /* 8 32k periods */
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#cooling-cells = <2>;
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};
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cpu2: cpu@2 {
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device_type = "cpu";
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reg = <2>;
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enable-method = "psci";
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clocks = <&ccu CLK_CPUX>;
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clock-latency-ns = <244144>; /* 8 32k periods */
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#cooling-cells = <2>;
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};
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cpu3: cpu@3 {
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device_type = "cpu";
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reg = <3>;
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enable-method = "psci";
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clocks = <&ccu CLK_CPUX>;
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clock-latency-ns = <244144>; /* 8 32k periods */
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#cooling-cells = <2>;
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};
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};
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pmu {
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compatible = "arm,cortex-a53-pmu",
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"arm,armv8-pmuv3";
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compatible = "arm,cortex-a53-pmu";
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interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
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timer {
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compatible = "arm,armv8-timer";
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arm,no-tick-in-suspend;
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interrupts = <GIC_PPI 13
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14
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resets = <&ccu RST_BUS_CE>;
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};
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deinterlace: deinterlace@1e00000 {
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compatible = "allwinner,sun8i-h3-deinterlace";
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reg = <0x01e00000 0x20000>;
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clocks = <&ccu CLK_BUS_DEINTERLACE>,
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<&ccu CLK_DEINTERLACE>,
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<&ccu CLK_DRAM_DEINTERLACE>;
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clock-names = "bus", "mod", "ram";
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resets = <&ccu RST_BUS_DEINTERLACE>;
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interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
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interconnects = <&mbus 9>;
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interconnect-names = "dma-mem";
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};
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mali: gpu@1e80000 {
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compatible = "allwinner,sun50i-h5-mali", "arm,mali-450";
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reg = <0x01e80000 0x30000>;
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@ -126,8 +153,7 @@
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<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
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<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "gp",
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"gpmmu",
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"pp",
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@ -138,8 +164,7 @@
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"pp2",
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"ppmmu2",
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"pp3",
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"ppmmu3",
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"pmu";
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"ppmmu3";
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clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>;
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clock-names = "bus", "core";
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resets = <&ccu RST_BUS_GPU>;
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@ -166,6 +191,30 @@
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polling-delay-passive = <0>;
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polling-delay = <0>;
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thermal-sensors = <&ths 0>;
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trips {
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cpu_hot_trip: cpu-hot {
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temperature = <80000>;
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hysteresis = <2000>;
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type = "passive";
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};
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cpu_very_hot_trip: cpu-very-hot {
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temperature = <100000>;
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hysteresis = <0>;
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type = "critical";
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};
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};
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cooling-maps {
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cpu-hot-limit {
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trip = <&cpu_hot_trip>;
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cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
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};
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};
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};
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gpu_thermal {
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@ -41,6 +41,7 @@
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*/
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#include "sunxi-h3-h5.dtsi"
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#include <dt-bindings/thermal/thermal.h>
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/ {
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cpu0_opp_table: opp_table0 {
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|
@ -111,6 +112,26 @@
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};
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};
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gpu_opp_table: gpu-opp-table {
|
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compatible = "operating-points-v2";
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opp-120000000 {
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opp-hz = /bits/ 64 <120000000>;
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};
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opp-312000000 {
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opp-hz = /bits/ 64 <312000000>;
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};
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opp-432000000 {
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opp-hz = /bits/ 64 <432000000>;
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};
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opp-576000000 {
|
||||
opp-hz = /bits/ 64 <576000000>;
|
||||
};
|
||||
};
|
||||
|
||||
pmu {
|
||||
compatible = "arm,cortex-a7-pmu";
|
||||
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
|
||||
|
@ -204,9 +225,7 @@
|
|||
clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>;
|
||||
clock-names = "bus", "core";
|
||||
resets = <&ccu RST_BUS_GPU>;
|
||||
|
||||
assigned-clocks = <&ccu CLK_GPU>;
|
||||
assigned-clock-rates = <384000000>;
|
||||
operating-points-v2 = <&gpu_opp_table>;
|
||||
};
|
||||
|
||||
ths: thermal-sensor@1c25000 {
|
||||
|
@ -227,6 +246,30 @@
|
|||
polling-delay-passive = <0>;
|
||||
polling-delay = <0>;
|
||||
thermal-sensors = <&ths 0>;
|
||||
|
||||
trips {
|
||||
cpu_hot_trip: cpu-hot {
|
||||
temperature = <80000>;
|
||||
hysteresis = <2000>;
|
||||
type = "passive";
|
||||
};
|
||||
|
||||
cpu_very_hot_trip: cpu-very-hot {
|
||||
temperature = <100000>;
|
||||
hysteresis = <0>;
|
||||
type = "critical";
|
||||
};
|
||||
};
|
||||
|
||||
cooling-maps {
|
||||
cpu-hot-limit {
|
||||
trip = <&cpu_hot_trip>;
|
||||
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
@ -114,7 +114,7 @@
|
|||
|
||||
display_clocks: clock@1000000 {
|
||||
/* compatible is in per SoC .dtsi file */
|
||||
reg = <0x01000000 0x100000>;
|
||||
reg = <0x01000000 0x10000>;
|
||||
clocks = <&ccu CLK_BUS_DE>,
|
||||
<&ccu CLK_DE>;
|
||||
clock-names = "bus",
|
||||
|
@ -239,6 +239,16 @@
|
|||
};
|
||||
};
|
||||
|
||||
msgbox: mailbox@1c17000 {
|
||||
compatible = "allwinner,sun8i-h3-msgbox",
|
||||
"allwinner,sun6i-a31-msgbox";
|
||||
reg = <0x01c17000 0x1000>;
|
||||
clocks = <&ccu CLK_BUS_MSGBOX>;
|
||||
resets = <&ccu RST_BUS_MSGBOX>;
|
||||
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#mbox-cells = <1>;
|
||||
};
|
||||
|
||||
usb_otg: usb@1c19000 {
|
||||
compatible = "allwinner,sun8i-h3-musb";
|
||||
reg = <0x01c19000 0x400>;
|
||||
|
@ -560,6 +570,8 @@
|
|||
compatible = "allwinner,sun8i-h3-mbus";
|
||||
reg = <0x01c62000 0x1000>;
|
||||
clocks = <&ccu CLK_MBUS>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
dma-ranges = <0x00000000 0x40000000 0xc0000000>;
|
||||
#interconnect-cells = <1>;
|
||||
};
|
||||
|
@ -650,6 +662,19 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
i2s2: i2s@1c22800 {
|
||||
#sound-dai-cells = <0>;
|
||||
compatible = "allwinner,sun8i-h3-i2s";
|
||||
reg = <0x01c22800 0x400>;
|
||||
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&ccu CLK_BUS_I2S2>, <&ccu CLK_I2S2>;
|
||||
clock-names = "apb", "mod";
|
||||
dmas = <&dma 27>;
|
||||
resets = <&ccu RST_BUS_I2S2>;
|
||||
dma-names = "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
codec: codec@1c22c00 {
|
||||
#sound-dai-cells = <0>;
|
||||
compatible = "allwinner,sun8i-h3-codec";
|
||||
|
@ -892,6 +917,21 @@
|
|||
pins = "PL0", "PL1";
|
||||
function = "s_i2c";
|
||||
};
|
||||
|
||||
r_pwm_pin: r-pwm-pin {
|
||||
pins = "PL10";
|
||||
function = "s_pwm";
|
||||
};
|
||||
};
|
||||
|
||||
r_pwm: pwm@1f03800 {
|
||||
compatible = "allwinner,sun8i-h3-pwm";
|
||||
reg = <0x01f03800 0x8>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&r_pwm_pin>;
|
||||
clocks = <&osc24M>;
|
||||
#pwm-cells = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
Loading…
Add table
Reference in a new issue