mirror of
https://github.com/Fishwaldo/u-boot.git
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pci: powerpc: Drop old code
Drop the old pre-driver model code from these drivers. Signed-off-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Simon Glass
Tom Rini
parent
ae09983886
commit
595232ad1f
3 changed files with 0 additions and 352 deletions
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@ -27,166 +27,6 @@ DECLARE_GLOBAL_DATA_PTR;
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static struct pci_controller pci_hose[MAX_BUSES];
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static int pci_num_buses;
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#if !defined(CONFIG_DM_PCI)
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static void pci_init_bus(int bus, struct pci_region *reg)
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{
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volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
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volatile pot83xx_t *pot = immr->ios.pot;
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volatile pcictrl83xx_t *pci_ctrl = &immr->pci_ctrl[bus];
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struct pci_controller *hose = &pci_hose[bus];
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u32 dev;
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u16 reg16;
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int i;
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if (bus == 1)
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pot += 3;
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/* Setup outbound translation windows */
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for (i = 0; i < 3; i++, reg++, pot++) {
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if (reg->size == 0)
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break;
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hose->regions[i] = *reg;
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hose->region_count++;
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pot->potar = reg->bus_start >> 12;
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pot->pobar = reg->phys_start >> 12;
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pot->pocmr = ~(reg->size - 1) >> 12;
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if (reg->flags & PCI_REGION_IO)
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pot->pocmr |= POCMR_IO;
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#ifdef CONFIG_83XX_PCI_STREAMING
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else if (reg->flags & PCI_REGION_PREFETCH)
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pot->pocmr |= POCMR_SE;
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#endif
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if (bus == 1)
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pot->pocmr |= POCMR_DST;
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pot->pocmr |= POCMR_EN;
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}
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/* Point inbound translation at RAM */
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pci_ctrl->pitar1 = 0;
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pci_ctrl->pibar1 = 0;
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pci_ctrl->piebar1 = 0;
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pci_ctrl->piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP |
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PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size - 1));
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i = hose->region_count++;
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hose->regions[i].bus_start = 0;
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hose->regions[i].phys_start = 0;
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hose->regions[i].size = gd->ram_size;
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hose->regions[i].flags = PCI_REGION_MEM | PCI_REGION_SYS_MEMORY;
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hose->first_busno = pci_last_busno() + 1;
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hose->last_busno = 0xff;
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pci_setup_indirect(hose, CONFIG_SYS_IMMR + 0x8300 + bus * 0x80,
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CONFIG_SYS_IMMR + 0x8304 + bus * 0x80);
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pci_register_hose(hose);
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/*
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* Write to Command register
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*/
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reg16 = 0xff;
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dev = PCI_BDF(hose->first_busno, 0, 0);
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pci_hose_read_config_word(hose, dev, PCI_COMMAND, ®16);
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reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
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pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16);
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/*
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* Clear non-reserved bits in status register.
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*/
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pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
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pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
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pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
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#ifdef CONFIG_PCI_SCAN_SHOW
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printf("PCI: Bus Dev VenId DevId Class Int\n");
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#endif
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#ifndef CONFIG_PCISLAVE
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/*
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* Hose scan.
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*/
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hose->last_busno = pci_hose_scan(hose);
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#endif
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}
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/*
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* The caller must have already set OCCR, and the PCI_LAW BARs
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* must have been set to cover all of the requested regions.
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*
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* If fewer than three regions are requested, then the region
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* list is terminated with a region of size 0.
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*/
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void mpc83xx_pci_init(int num_buses, struct pci_region **reg)
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{
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volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
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int i;
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if (num_buses > MAX_BUSES) {
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printf("%d PCI buses requested, %d supported\n",
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num_buses, MAX_BUSES);
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num_buses = MAX_BUSES;
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}
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pci_num_buses = num_buses;
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/*
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* Release PCI RST Output signal.
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* Power on to RST high must be at least 100 ms as per PCI spec.
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* On warm boots only 1 ms is required, but we play it safe.
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*/
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udelay(100000);
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for (i = 0; i < num_buses; i++)
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immr->pci_ctrl[i].gcr = 1;
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/*
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* RST high to first config access must be at least 2^25 cycles
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* as per PCI spec. This could be cut in half if we know we're
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* running at 66MHz. This could be insufficiently long if we're
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* running the PCI bus at significantly less than 33MHz.
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*/
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udelay(1020000);
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for (i = 0; i < num_buses; i++)
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pci_init_bus(i, reg[i]);
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}
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#ifdef CONFIG_PCISLAVE
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#define PCI_FUNCTION_CONFIG 0x44
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#define PCI_FUNCTION_CFG_LOCK 0x20
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/*
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* Unlock the configuration bit so that the host system can begin booting
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*
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* This should be used after you have:
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* 1) Called mpc83xx_pci_init()
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* 2) Set up your inbound translation windows to the appropriate size
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*/
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void mpc83xx_pcislave_unlock(int bus)
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{
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struct pci_controller *hose = &pci_hose[bus];
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u32 dev;
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u16 reg16;
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/* Unlock configuration lock in PCI function configuration register */
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dev = PCI_BDF(hose->first_busno, 0, 0);
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pci_hose_read_config_word (hose, dev, PCI_FUNCTION_CONFIG, ®16);
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reg16 &= ~(PCI_FUNCTION_CFG_LOCK);
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pci_hose_write_config_word (hose, dev, PCI_FUNCTION_CONFIG, reg16);
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/* The configuration bit is now unlocked, so we can scan the bus */
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hose->last_busno = pci_hose_scan(hose);
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}
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#endif
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#endif /* CONFIG_DM_PCI */
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#if defined(CONFIG_OF_LIBFDT)
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void ft_pci_setup(void *blob, struct bd_info *bd)
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{
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@ -33,7 +33,6 @@ obj-$(CONFIG_CPM2) += ether_fcc.o
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obj-$(CONFIG_OF_LIBFDT) += fdt.o
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obj-$(CONFIG_FSL_CORENET) += liodn.o
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obj-$(CONFIG_MP) += mp.o
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obj-$(CONFIG_PCI) += pci.o
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obj-$(CONFIG_SYS_DPAA_QBMAN) += portals.o
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# various SoC specific assignments
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@ -1,191 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2004 Freescale Semiconductor.
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* Copyright (C) 2003 Motorola Inc.
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* Xianghua Xiao (x.xiao@motorola.com)
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*/
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/*
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* PCI Configuration space access support for MPC85xx PCI Bridge
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*/
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#include <common.h>
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#include <asm/bitops.h>
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#include <asm/cpm_85xx.h>
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#include <pci.h>
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#if !defined(CONFIG_FSL_PCI_INIT) && !defined(CONFIG_DM_PCI)
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#ifndef CONFIG_SYS_PCI1_MEM_BUS
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#define CONFIG_SYS_PCI1_MEM_BUS CONFIG_SYS_PCI1_MEM_BASE
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#endif
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#ifndef CONFIG_SYS_PCI1_IO_BUS
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#define CONFIG_SYS_PCI1_IO_BUS CONFIG_SYS_PCI1_IO_BASE
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#endif
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#ifndef CONFIG_SYS_PCI2_MEM_BUS
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#define CONFIG_SYS_PCI2_MEM_BUS CONFIG_SYS_PCI2_MEM_BASE
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#endif
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#ifndef CONFIG_SYS_PCI2_IO_BUS
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#define CONFIG_SYS_PCI2_IO_BUS CONFIG_SYS_PCI2_IO_BASE
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#endif
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static struct pci_controller *pci_hose;
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void
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pci_mpc85xx_init(struct pci_controller *board_hose)
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{
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u16 reg16;
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u32 dev;
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volatile ccsr_pcix_t *pcix = (void *)(CONFIG_SYS_MPC85xx_PCIX_ADDR);
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#ifdef CONFIG_MPC85XX_PCI2
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volatile ccsr_pcix_t *pcix2 = (void *)(CONFIG_SYS_MPC85xx_PCIX2_ADDR);
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#endif
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volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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struct pci_controller * hose;
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pci_hose = board_hose;
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hose = &pci_hose[0];
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hose->first_busno = 0;
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hose->last_busno = 0xff;
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pci_setup_indirect(hose,
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(CONFIG_SYS_IMMR+0x8000),
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(CONFIG_SYS_IMMR+0x8004));
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/*
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* Hose scan.
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*/
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dev = PCI_BDF(hose->first_busno, 0, 0);
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pci_hose_read_config_word (hose, dev, PCI_COMMAND, ®16);
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reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
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pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16);
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/*
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* Clear non-reserved bits in status register.
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*/
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pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
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if (!(gur->pordevsr & MPC85xx_PORDEVSR_PCI1)) {
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/* PCI-X init */
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if (CONFIG_SYS_CLK_FREQ < 66000000)
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printf("PCI-X will only work at 66 MHz\n");
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reg16 = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ
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| PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
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pci_hose_write_config_word(hose, dev, PCIX_COMMAND, reg16);
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}
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pcix->potar1 = (CONFIG_SYS_PCI1_MEM_BUS >> 12) & 0x000fffff;
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pcix->potear1 = 0x00000000;
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pcix->powbar1 = (CONFIG_SYS_PCI1_MEM_PHYS >> 12) & 0x000fffff;
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pcix->powbear1 = 0x00000000;
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pcix->powar1 = (POWAR_EN | POWAR_MEM_READ |
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POWAR_MEM_WRITE | (__ilog2(CONFIG_SYS_PCI1_MEM_SIZE) - 1));
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pcix->potar2 = (CONFIG_SYS_PCI1_IO_BUS >> 12) & 0x000fffff;
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pcix->potear2 = 0x00000000;
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pcix->powbar2 = (CONFIG_SYS_PCI1_IO_PHYS >> 12) & 0x000fffff;
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pcix->powbear2 = 0x00000000;
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pcix->powar2 = (POWAR_EN | POWAR_IO_READ |
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POWAR_IO_WRITE | (__ilog2(CONFIG_SYS_PCI1_IO_SIZE) - 1));
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pcix->pitar1 = 0x00000000;
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pcix->piwbar1 = 0x00000000;
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pcix->piwar1 = (PIWAR_EN | PIWAR_PF | PIWAR_LOCAL |
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PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP | PIWAR_MEM_2G);
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pcix->powar3 = 0;
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pcix->powar4 = 0;
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pcix->piwar2 = 0;
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pcix->piwar3 = 0;
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pci_set_region(hose->regions + 0,
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CONFIG_SYS_PCI1_MEM_BUS,
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CONFIG_SYS_PCI1_MEM_PHYS,
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CONFIG_SYS_PCI1_MEM_SIZE,
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PCI_REGION_MEM);
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pci_set_region(hose->regions + 1,
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CONFIG_SYS_PCI1_IO_BUS,
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CONFIG_SYS_PCI1_IO_PHYS,
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CONFIG_SYS_PCI1_IO_SIZE,
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PCI_REGION_IO);
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hose->region_count = 2;
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pci_register_hose(hose);
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hose->last_busno = pci_hose_scan(hose);
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#ifdef CONFIG_MPC85XX_PCI2
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hose = &pci_hose[1];
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hose->first_busno = pci_hose[0].last_busno + 1;
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hose->last_busno = 0xff;
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pci_setup_indirect(hose,
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(CONFIG_SYS_IMMR+0x9000),
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(CONFIG_SYS_IMMR+0x9004));
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dev = PCI_BDF(hose->first_busno, 0, 0);
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pci_hose_read_config_word (hose, dev, PCI_COMMAND, ®16);
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reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
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pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16);
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/*
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* Clear non-reserved bits in status register.
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*/
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pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
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pcix2->potar1 = (CONFIG_SYS_PCI2_MEM_BUS >> 12) & 0x000fffff;
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pcix2->potear1 = 0x00000000;
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pcix2->powbar1 = (CONFIG_SYS_PCI2_MEM_PHYS >> 12) & 0x000fffff;
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pcix2->powbear1 = 0x00000000;
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pcix2->powar1 = (POWAR_EN | POWAR_MEM_READ |
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POWAR_MEM_WRITE | (__ilog2(CONFIG_SYS_PCI2_MEM_SIZE) - 1));
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pcix2->potar2 = (CONFIG_SYS_PCI2_IO_BUS >> 12) & 0x000fffff;
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pcix2->potear2 = 0x00000000;
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pcix2->powbar2 = (CONFIG_SYS_PCI2_IO_PHYS >> 12) & 0x000fffff;
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pcix2->powbear2 = 0x00000000;
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pcix2->powar2 = (POWAR_EN | POWAR_IO_READ |
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POWAR_IO_WRITE | (__ilog2(CONFIG_SYS_PCI2_IO_SIZE) - 1));
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pcix2->pitar1 = 0x00000000;
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pcix2->piwbar1 = 0x00000000;
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pcix2->piwar1 = (PIWAR_EN | PIWAR_PF | PIWAR_LOCAL |
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PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP | PIWAR_MEM_2G);
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pcix2->powar3 = 0;
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pcix2->powar4 = 0;
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pcix2->piwar2 = 0;
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pcix2->piwar3 = 0;
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pci_set_region(hose->regions + 0,
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CONFIG_SYS_PCI2_MEM_BUS,
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CONFIG_SYS_PCI2_MEM_PHYS,
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CONFIG_SYS_PCI2_MEM_SIZE,
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PCI_REGION_MEM);
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pci_set_region(hose->regions + 1,
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CONFIG_SYS_PCI2_IO_BUS,
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CONFIG_SYS_PCI2_IO_PHYS,
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CONFIG_SYS_PCI2_IO_SIZE,
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PCI_REGION_IO);
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hose->region_count = 2;
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/*
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* Hose scan.
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*/
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pci_register_hose(hose);
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hose->last_busno = pci_hose_scan(hose);
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#endif
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}
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#endif /* !CONFIG_FSL_PCI_INIT */
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