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Merge branch 'CR_7124_PCIe_Kevin.xie' into 'jh7110-master'
CR 7124 PCIe dts & driver: Modified reset & link wait timing for better compatbility. See merge request sdk/u-boot!71
This commit is contained in:
commit
5a6195d028
2 changed files with 47 additions and 6 deletions
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@ -1197,7 +1197,7 @@
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<0x9 0x40000000 0x0 0x10000000>;
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reg-names = "reg", "config";
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device_type = "pci";
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starfive,stg-syscon = <&stg_syscon 0xc0 0xc4 0x130>;
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starfive,stg-syscon = <&stg_syscon 0xc0 0xc4 0x130 0x1b8>;
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bus-range = <0x0 0xff>;
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ranges = <0x82000000 0x0 0x30000000 0x0 0x30000000 0x0 0x08000000>,
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<0xc3000000 0x9 0x00000000 0x9 0x00000000 0x0 0x40000000>;
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@ -1236,7 +1236,7 @@
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<0x9 0xc0000000 0x0 0x10000000>;
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reg-names = "reg", "config";
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device_type = "pci";
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starfive,stg-syscon = <&stg_syscon 0x270 0x274 0x2e0>;
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starfive,stg-syscon = <&stg_syscon 0x270 0x274 0x2e0 0x368>;
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bus-range = <0x0 0xff>;
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ranges = <0x82000000 0x0 0x38000000 0x0 0x38000000 0x0 0x08000000>,
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<0xc3000000 0x9 0x80000000 0x9 0x80000000 0x0 0x40000000>;
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@ -40,6 +40,10 @@ DECLARE_GLOBAL_DATA_PTR;
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#define IDS_PCI_TO_PCI_BRIDGE 0x060400
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#define IDS_CLASS_CODE_SHIFT 8
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#define PLDA_LINK_UP 1
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#define PLDA_LINK_DOWN 0
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#define PLDA_DATA_LINK_ACTIVE BIT(5)
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#define PREF_MEM_WIN_64_SUPPORT BIT(3)
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#define PMSG_LTR_SUPPORT BIT(2)
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#define PLDA_FUNCTION_DIS BIT(15)
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@ -92,6 +96,7 @@ struct starfive_pcie {
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u32 stg_arfun;
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u32 stg_awfun;
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u32 stg_rp_nep;
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u32 stg_lnksta;
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struct clk_bulk clks;
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struct reset_ctl_bulk rsts;
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@ -267,7 +272,7 @@ static int starfive_pcie_get_syscon(struct udevice *dev)
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struct starfive_pcie *priv = dev_get_priv(dev);
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struct udevice *syscon;
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struct ofnode_phandle_args syscfg_phandle;
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u32 cells[4];
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u32 cells[5];
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int ret;
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/* get corresponding syscon phandle */
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@ -300,11 +305,12 @@ static int starfive_pcie_get_syscon(struct udevice *dev)
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return -EINVAL;
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}
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dev_dbg(dev, "Get syscon values: %x, %x, %x\n",
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cells[1], cells[2], cells[3]);
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dev_dbg(dev, "Get syscon values: %x, %x, %x, %x\n",
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cells[1], cells[2], cells[3], cells[4]);
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priv->stg_arfun = cells[1];
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priv->stg_awfun = cells[2];
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priv->stg_rp_nep = cells[3];
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priv->stg_lnksta = cells[4];
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return 0;
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}
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@ -431,7 +437,7 @@ static int starfive_pcie_init_port(struct udevice *dev)
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starfive_pcie_atr_init(priv);
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/* Ensure that PERST has been asserted for at least 300 ms */
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mdelay(300);
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mdelay(100);
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ret = pinctrl_select_state(dev, "perst-default");
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if (ret) {
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dev_err(dev, "Set perst-default pinctrl failed: %d\n", ret);
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@ -450,6 +456,33 @@ err_deassert_clk:
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return ret;
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}
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static int plda_pcie_is_link_up(struct udevice *dev)
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{
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struct starfive_pcie *priv = dev_get_priv(dev);
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int ret;
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u32 stg_reg_val;
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/* 100ms timeout value should be enough for Gen1/2 training */
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ret = regmap_read_poll_timeout(priv->regmap,
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priv->stg_lnksta,
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stg_reg_val,
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stg_reg_val & PLDA_DATA_LINK_ACTIVE,
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10 * 1000, 100);
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/* If the link is down (no device in slot), then exit. */
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if (ret == -ETIMEDOUT) {
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dev_err(dev, "Port link down.\n");
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return PLDA_LINK_DOWN;
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} else if (ret == 0) {
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dev_err(dev, "Port link up.\n");
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return PLDA_LINK_UP;
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}
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dev_warn(dev, "Read stg_linksta failed.\n");
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return ret;
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}
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static int starfive_pcie_probe(struct udevice *dev)
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{
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struct starfive_pcie *priv = dev_get_priv(dev);
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@ -482,6 +515,14 @@ static int starfive_pcie_probe(struct udevice *dev)
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if (ret)
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return ret;
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if (plda_pcie_is_link_up(dev) == PLDA_LINK_UP) {
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/* As the requirement in PCIe base spec r6.0, system (<=5GT/s) must
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* wait a minimum of 100 ms following exit from a conventional reset
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* before sending a configuration request to the device.
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*/
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mdelay(100);
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}
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dev_err(dev, "Starfive PCIe bus probed.\n");
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return 0;
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