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fpga: zynqpl: Clean partial bitstream handling
Do not do partial bitstream detection based on bitstream size and use bitstream_type argument which is passed from the fpga core. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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parent
67193864bc
commit
5b815c9c61
1 changed files with 6 additions and 12 deletions
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@ -194,7 +194,7 @@ static int zynq_dma_transfer(u32 srcbuf, u32 srclen, u32 dstbuf, u32 dstlen)
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return FPGA_SUCCESS;
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}
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static int zynq_dma_xfer_init(u32 partialbit)
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static int zynq_dma_xfer_init(bitstream_type bstype)
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{
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u32 status, control, isr_status;
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unsigned long ts;
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@ -202,7 +202,7 @@ static int zynq_dma_xfer_init(u32 partialbit)
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/* Clear loopback bit */
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clrbits_le32(&devcfg_base->mctrl, DEVCFG_MCTRL_PCAP_LPBK);
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if (!partialbit) {
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if (bstype != BIT_PARTIAL) {
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zynq_slcr_devcfg_disable();
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/* Setting PCFG_PROG_B signal to high */
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@ -322,16 +322,11 @@ static u32 *zynq_align_dma_buffer(u32 *buf, u32 len, u32 swap)
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static int zynq_validate_bitstream(xilinx_desc *desc, const void *buf,
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size_t bsize, u32 blocksize, u32 *swap,
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u32 *partialbit)
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bitstream_type *bstype)
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{
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u32 *buf_start;
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u32 diff;
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/* Detect if we are going working with partial or full bitstream */
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if (bsize != desc->size) {
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printf("%s: Working with partial bitstream\n", __func__);
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*partialbit = 1;
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}
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buf_start = check_data((u8 *)buf, blocksize, swap);
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if (!buf_start)
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@ -351,7 +346,7 @@ static int zynq_validate_bitstream(xilinx_desc *desc, const void *buf,
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return FPGA_FAIL;
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}
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if (zynq_dma_xfer_init(*partialbit))
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if (zynq_dma_xfer_init(*bstype))
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return FPGA_FAIL;
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return 0;
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@ -361,7 +356,6 @@ static int zynq_load(xilinx_desc *desc, const void *buf, size_t bsize,
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bitstream_type bstype)
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{
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unsigned long ts; /* Timestamp */
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u32 partialbit = 0;
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u32 isr_status, swap;
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/*
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@ -369,7 +363,7 @@ static int zynq_load(xilinx_desc *desc, const void *buf, size_t bsize,
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* in chunks
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*/
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if (zynq_validate_bitstream(desc, buf, bsize, bsize, &swap,
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&partialbit))
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&bstype))
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return FPGA_FAIL;
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buf = zynq_align_dma_buffer((u32 *)buf, bsize, swap);
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@ -398,7 +392,7 @@ static int zynq_load(xilinx_desc *desc, const void *buf, size_t bsize,
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debug("%s: FPGA config done\n", __func__);
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if (!partialbit)
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if (bstype != BIT_PARTIAL)
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zynq_slcr_devcfg_enable();
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return FPGA_SUCCESS;
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