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driver/ddr/freescale: Fix DDR3 driver for ARM

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Reading DDR register should use ddr_in32() for proper endianess.
This patch fixes incorrect waiting time for ARM platforms.

Signed-off-by: York Sun <yorksun@freescale.com>
This commit is contained in:
York Sun 2014-09-05 13:52:42 +08:00
parent d28cb67142
commit 5cb27c5d44
1 changed files with 1 additions and 1 deletions
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drivers/ddr/fsl/arm_ddr_gen3.c
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@ -194,7 +194,7 @@ step2:
* For example, 2GB on 666MT/s 64-bit bus takes about 402ms * For example, 2GB on 666MT/s 64-bit bus takes about 402ms
* Let's wait for 800ms * Let's wait for 800ms
*/ */
bus_width = 3 - ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK) bus_width = 3 - ((ddr_in32(&ddr->sdram_cfg) & SDRAM_CFG_DBW_MASK)
>> SDRAM_CFG_DBW_SHIFT); >> SDRAM_CFG_DBW_SHIFT);
timeout = ((total_gb_size_per_controller << (6 - bus_width)) * 100 / timeout = ((total_gb_size_per_controller << (6 - bus_width)) * 100 /
(get_ddr_freq(0) >> 20)) << 1; (get_ddr_freq(0) >> 20)) << 1;