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ppc4xx: AMCC PPC460GT/EX PCI-E de-emphasis adjustment fix

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During recent PCI-E tests it has been found that current
driverl level and de-emphasis values are not set correctly.
After sweeping throgh all de-ephasis values, it was found that
0x130 is a right value. Where 0x13 is driver level and 0 is
de-emphasis.

Signed-off-by: Tirumala R Marri <tmarri@amcc.com>
Signed-off-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Tirumala R Marri 2008-08-21 21:54:53 -07:00 • committed by Stefan Roese
parent f556483734
commit 5d4b3d2b31
1 changed files with 5 additions and 5 deletions
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10
cpu/ppc4xx/4xx_pcie.c
View file

@ -638,7 +638,7 @@ int __ppc4xx_init_pcie_port_hw(int port, int rootport)
switch (port) { switch (port) {
case 0: case 0:
SDR_WRITE(PESDR0_L0CDRCTL, 0x00003230); SDR_WRITE(PESDR0_L0CDRCTL, 0x00003230);
SDR_WRITE(PESDR0_L0DRV, 0x00000136); SDR_WRITE(PESDR0_L0DRV, 0x00000130);
SDR_WRITE(PESDR0_L0CLK, 0x00000006); SDR_WRITE(PESDR0_L0CLK, 0x00000006);
SDR_WRITE(PESDR0_PHY_CTL_RST,0x10000000); SDR_WRITE(PESDR0_PHY_CTL_RST,0x10000000);
@ -649,10 +649,10 @@ int __ppc4xx_init_pcie_port_hw(int port, int rootport)
SDR_WRITE(PESDR1_L1CDRCTL, 0x00003230); SDR_WRITE(PESDR1_L1CDRCTL, 0x00003230);
SDR_WRITE(PESDR1_L2CDRCTL, 0x00003230); SDR_WRITE(PESDR1_L2CDRCTL, 0x00003230);
SDR_WRITE(PESDR1_L3CDRCTL, 0x00003230); SDR_WRITE(PESDR1_L3CDRCTL, 0x00003230);
SDR_WRITE(PESDR1_L0DRV, 0x00000136); SDR_WRITE(PESDR1_L0DRV, 0x00000130);
SDR_WRITE(PESDR1_L1DRV, 0x00000136); SDR_WRITE(PESDR1_L1DRV, 0x00000130);
SDR_WRITE(PESDR1_L2DRV, 0x00000136); SDR_WRITE(PESDR1_L2DRV, 0x00000130);
SDR_WRITE(PESDR1_L3DRV, 0x00000136); SDR_WRITE(PESDR1_L3DRV, 0x00000130);
SDR_WRITE(PESDR1_L0CLK, 0x00000006); SDR_WRITE(PESDR1_L0CLK, 0x00000006);
SDR_WRITE(PESDR1_L1CLK, 0x00000006); SDR_WRITE(PESDR1_L1CLK, 0x00000006);
SDR_WRITE(PESDR1_L2CLK, 0x00000006); SDR_WRITE(PESDR1_L2CLK, 0x00000006);