mirror of
https://github.com/Fishwaldo/u-boot.git
synced 2025-03-18 21:21:37 +00:00
Merge branch '2018-11-26-master-imports'
- chiliboard updates - misc TI platform updates
This commit is contained in:
Tom Rini
commit
5d5833af64
25 changed files with 455 additions and 74 deletions
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@ -205,6 +205,15 @@ ENTRY(cpu_init_cp15)
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mov r2, r3, lsl #4 @ shift variant field for combined value
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orr r2, r4, r2 @ r2 has combined CPU variant + revision
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/* Early stack for ERRATA that needs into call C code */
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#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK)
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ldr r0, =(CONFIG_SPL_STACK)
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#else
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ldr r0, =(CONFIG_SYS_INIT_SP_ADDR)
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#endif
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bic r0, r0, #7 /* 8-byte alignment for ABI compliance */
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mov sp, r0
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#ifdef CONFIG_ARM_ERRATA_798870
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cmp r2, #0x30 @ Applies to lower than R3p0
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bge skip_errata_798870 @ skip if not affected rev
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@ -187,7 +187,8 @@ dtb-$(CONFIG_AM33XX) += am335x-boneblack.dtb am335x-bone.dtb \
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am335x-icev2.dtb \
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am335x-pxm50.dtb \
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am335x-rut.dtb \
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am335x-pdu001.dtb
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am335x-pdu001.dtb \
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am335x-chiliboard.dtb
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dtb-$(CONFIG_AM43XX) += am437x-gp-evm.dtb am437x-sk-evm.dtb \
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am43x-epos-evm.dtb \
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am437x-idk-evm.dtb \
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11
arch/arm/dts/am335x-chiliboard-u-boot.dtsi
Normal file
11
arch/arm/dts/am335x-chiliboard-u-boot.dtsi
Normal file
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@ -0,0 +1,11 @@
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// SPDX-License-Identifier: GPL-2.0+ or X11
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/*
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* Copyright (C) 2018 Grinn Sp. z o.o. -- http://www.grinn-global.com/
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* Author: Marcin Niestroj <m.niestroj@grinn-global.com>
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*/
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/ {
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chosen {
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stdout-path = &uart0;
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};
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};
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200
arch/arm/dts/am335x-chiliboard.dts
Normal file
200
arch/arm/dts/am335x-chiliboard.dts
Normal file
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@ -0,0 +1,200 @@
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/*
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* Copyright (C) 2015 Jablotron s.r.o. -- http://www.jablotron.com/
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* Author: Rostislav Lisovy <lisovy@jablotron.cz>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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/dts-v1/;
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#include "am335x-chilisom.dtsi"
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/ {
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model = "AM335x Chiliboard";
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compatible = "grinn,am335x-chiliboard", "grinn,am335x-chilisom",
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"ti,am33xx";
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leds {
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compatible = "gpio-leds";
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pinctrl-names = "default";
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pinctrl-0 = <&led_gpio_pins>;
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led0 {
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label = "led0";
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gpios = <&gpio3 7 GPIO_ACTIVE_LOW>;
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default-state = "keep";
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linux,default-trigger = "heartbeat";
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};
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led1 {
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label = "led1";
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gpios = <&gpio3 8 GPIO_ACTIVE_LOW>;
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default-state = "keep";
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};
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};
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};
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&am33xx_pinmux {
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uart0_pins: pinmux_uart0_pins {
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pinctrl-single,pins = <
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AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */
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AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
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>;
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};
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cpsw_default: cpsw_default {
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pinctrl-single,pins = <
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/* Slave 1 */
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AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_crs.rmii1_crs */
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AM33XX_IOPAD(0x910, PIN_INPUT_PULLUP | MUX_MODE1) /* mii1_rxerr.rmii1_rxerr */
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AM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txen.rmii1_txen */
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AM33XX_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd1.rmii1_txd1 */
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AM33XX_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd0.rmii1_txd0 */
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AM33XX_IOPAD(0x93c, PIN_INPUT_PULLUP | MUX_MODE1) /* mii1_rxd1.rmii1_rxd1 */
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AM33XX_IOPAD(0x940, PIN_INPUT_PULLUP | MUX_MODE1) /* mii1_rxd0.rmii1_rxd0 */
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AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii1_ref_clk.rmii_ref_clk */
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>;
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};
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cpsw_sleep: cpsw_sleep {
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pinctrl-single,pins = <
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/* Slave 1 reset value */
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AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE7)
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AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7)
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AM33XX_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7)
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AM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7)
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AM33XX_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7)
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AM33XX_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7)
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AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7)
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AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7)
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AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE7)
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>;
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};
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davinci_mdio_default: davinci_mdio_default {
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pinctrl-single,pins = <
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/* mdio_data.mdio_data */
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AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)
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/* mdio_clk.mdio_clk */
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AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0)
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>;
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};
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davinci_mdio_sleep: davinci_mdio_sleep {
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pinctrl-single,pins = <
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/* MDIO reset value */
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AM33XX_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7)
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AM33XX_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7)
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>;
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};
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usb1_drvvbus: usb1_drvvbus {
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pinctrl-single,pins = <
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AM33XX_IOPAD(0xa34, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* usb1_drvvbus.usb1_drvvbus */
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>;
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};
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sd_pins: pinmux_sd_card {
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pinctrl-single,pins = <
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AM33XX_IOPAD(0x8f0, PIN_INPUT | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */
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AM33XX_IOPAD(0x8f4, PIN_INPUT | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */
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AM33XX_IOPAD(0x8f8, PIN_INPUT | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */
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AM33XX_IOPAD(0x8fc, PIN_INPUT | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */
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AM33XX_IOPAD(0x900, PIN_INPUT | MUX_MODE0) /* mmc0_clk.mmc0_clk */
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AM33XX_IOPAD(0x904, PIN_INPUT | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */
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AM33XX_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
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>;
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};
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led_gpio_pins: led_gpio_pins {
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pinctrl-single,pins = <
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AM33XX_IOPAD(0x9e4, PIN_OUTPUT | MUX_MODE7) /* emu0.gpio3_7 */
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AM33XX_IOPAD(0x9e8, PIN_OUTPUT | MUX_MODE7) /* emu1.gpio3_8 */
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>;
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};
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};
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&uart0 {
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pinctrl-names = "default";
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pinctrl-0 = <&uart0_pins>;
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status = "okay";
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};
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&ldo4_reg {
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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};
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/* Ethernet */
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&mac {
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slaves = <1>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&cpsw_default>;
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pinctrl-1 = <&cpsw_sleep>;
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status = "okay";
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};
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&davinci_mdio {
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&davinci_mdio_default>;
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pinctrl-1 = <&davinci_mdio_sleep>;
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status = "okay";
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};
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&cpsw_emac0 {
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phy_id = <&davinci_mdio>, <0>;
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phy-mode = "rmii";
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};
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&phy_sel {
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rmii-clock-ext;
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};
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/* USB */
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&usb {
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status = "okay";
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};
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&usb_ctrl_mod {
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status = "okay";
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};
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&usb1_phy {
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status = "okay";
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};
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&usb1 {
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pinctrl-names = "default";
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pinctrl-0 = <&usb1_drvvbus>;
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status = "okay";
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dr_mode = "host";
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};
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&cppi41dma {
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status = "okay";
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};
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/* microSD */
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&mmc1 {
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pinctrl-names = "default";
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pinctrl-0 = <&sd_pins>;
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vmmc-supply = <&ldo4_reg>;
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bus-width = <0x4>;
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cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
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status = "okay";
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};
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&tps {
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interrupt-parent = <&intc>;
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interrupts = <7>; /* NNMI */
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charger {
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status = "okay";
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};
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pwrbutton {
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status = "okay";
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};
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};
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178
arch/arm/dts/am335x-chilisom.dtsi
Normal file
178
arch/arm/dts/am335x-chilisom.dtsi
Normal file
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@ -0,0 +1,178 @@
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/*
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* Copyright (C) 2015 Jablotron s.r.o. -- http://www.jablotron.com/
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* Author: Rostislav Lisovy <lisovy@jablotron.cz>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
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#include "am33xx.dtsi"
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#include <dt-bindings/interrupt-controller/irq.h>
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/ {
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model = "Grinn AM335x ChiliSOM";
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||||
compatible = "grinn,am335x-chilisom", "ti,am33xx";
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||||
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cpus {
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cpu@0 {
|
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cpu0-supply = <&dcdc2_reg>;
|
||||
};
|
||||
};
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||||
|
||||
memory@80000000 {
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device_type = "memory";
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||||
reg = <0x80000000 0x20000000>; /* 512 MB */
|
||||
};
|
||||
};
|
||||
|
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&am33xx_pinmux {
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pinctrl-names = "default";
|
||||
|
||||
i2c0_pins: pinmux_i2c0_pins {
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pinctrl-single,pins = <
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AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */
|
||||
AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */
|
||||
>;
|
||||
};
|
||||
|
||||
nandflash_pins: nandflash_pins {
|
||||
pinctrl-single,pins = <
|
||||
AM33XX_IOPAD(0x800, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
|
||||
AM33XX_IOPAD(0x804, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
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AM33XX_IOPAD(0x808, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
|
||||
AM33XX_IOPAD(0x80c, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
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AM33XX_IOPAD(0x810, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
|
||||
AM33XX_IOPAD(0x814, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
|
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AM33XX_IOPAD(0x818, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
|
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AM33XX_IOPAD(0x81c, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */
|
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|
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AM33XX_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */
|
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AM33XX_IOPAD(0x87c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */
|
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AM33XX_IOPAD(0x890, PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */
|
||||
AM33XX_IOPAD(0x894, PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */
|
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AM33XX_IOPAD(0x898, PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_wen.gpmc_wen */
|
||||
AM33XX_IOPAD(0x89c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c0 {
|
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pinctrl-names = "default";
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pinctrl-0 = <&i2c0_pins>;
|
||||
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
|
||||
tps: tps@24 {
|
||||
reg = <0x24>;
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
/include/ "tps65217.dtsi"
|
||||
|
||||
&tps {
|
||||
regulators {
|
||||
dcdc1_reg: regulator@0 {
|
||||
regulator-name = "vdds_dpr";
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
dcdc2_reg: regulator@1 {
|
||||
/* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
|
||||
regulator-name = "vdd_mpu";
|
||||
regulator-min-microvolt = <925000>;
|
||||
regulator-max-microvolt = <1325000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
dcdc3_reg: regulator@2 {
|
||||
/* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
|
||||
regulator-name = "vdd_core";
|
||||
regulator-min-microvolt = <925000>;
|
||||
regulator-max-microvolt = <1150000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo1_reg: regulator@3 {
|
||||
regulator-name = "vio,vrtc,vdds";
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo2_reg: regulator@4 {
|
||||
regulator-name = "vdd_3v3aux";
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo3_reg: regulator@5 {
|
||||
regulator-name = "vdd_1v8";
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo4_reg: regulator@6 {
|
||||
regulator-name = "vdd_3v3d";
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&rtc {
|
||||
system-power-controller;
|
||||
|
||||
pinctrl-0 = <&ext_wakeup>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
ext_wakeup: ext-wakeup {
|
||||
pins = "ext_wakeup0";
|
||||
input-enable;
|
||||
};
|
||||
};
|
||||
|
||||
/* NAND Flash */
|
||||
&elm {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpmc {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&nandflash_pins>;
|
||||
ranges = <0 0 0x08000000 0x01000000>; /* CS0 0 @addr 0x08000000, size 0x01000000 */
|
||||
nand@0,0 {
|
||||
compatible = "ti,omap2-nand";
|
||||
reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
|
||||
interrupt-parent = <&gpmc>;
|
||||
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
|
||||
<1 IRQ_TYPE_NONE>; /* termcount */
|
||||
rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
|
||||
ti,nand-ecc-opt = "bch8";
|
||||
ti,elm-id = <&elm>;
|
||||
nand-bus-width = <8>;
|
||||
gpmc,device-width = <1>;
|
||||
gpmc,sync-clk-ps = <0>;
|
||||
gpmc,cs-on-ns = <0>;
|
||||
gpmc,cs-rd-off-ns = <44>;
|
||||
gpmc,cs-wr-off-ns = <44>;
|
||||
gpmc,adv-on-ns = <6>;
|
||||
gpmc,adv-rd-off-ns = <34>;
|
||||
gpmc,adv-wr-off-ns = <44>;
|
||||
gpmc,we-on-ns = <0>;
|
||||
gpmc,we-off-ns = <40>;
|
||||
gpmc,oe-on-ns = <0>;
|
||||
gpmc,oe-off-ns = <54>;
|
||||
gpmc,access-ns = <64>;
|
||||
gpmc,rd-cycle-ns = <82>;
|
||||
gpmc,wr-cycle-ns = <82>;
|
||||
gpmc,bus-turnaround-ns = <0>;
|
||||
gpmc,cycle2cycle-delay-ns = <0>;
|
||||
gpmc,clk-activation-ns = <0>;
|
||||
gpmc,wr-access-ns = <40>;
|
||||
gpmc,wr-data-mux-bus-ns = <0>;
|
||||
};
|
||||
};
|
||||
|
|
@ -5,5 +5,5 @@
|
|||
|
||||
obj-$(CONFIG_SOC_K3_AM6) += am6_init.o
|
||||
obj-$(CONFIG_ARM64) += arm64-mmu.o
|
||||
obj-$(CONFIG_CPU_V7R) += r5_mpu.o
|
||||
obj-$(CONFIG_CPU_V7R) += r5_mpu.o lowlevel_init.o
|
||||
obj-y += common.o
|
||||
|
|
|
|||
20
arch/arm/mach-k3/lowlevel_init.S
Normal file
20
arch/arm/mach-k3/lowlevel_init.S
Normal file
|
|
@ -0,0 +1,20 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
|
||||
* Lokesh Vutla <lokeshvutla@ti.com>
|
||||
*/
|
||||
|
||||
#include <linux/linkage.h>
|
||||
|
||||
ENTRY(lowlevel_init)
|
||||
|
||||
mrc p15, 0, r0, c0, c0, 5 @ Read MPIDR
|
||||
and r0, #0xff
|
||||
cmp r0, #0x0
|
||||
bne park_cpu
|
||||
bx lr
|
||||
park_cpu:
|
||||
wfi
|
||||
b park_cpu
|
||||
|
||||
ENDPROC(lowlevel_init)
|
||||
|
|
@ -19,7 +19,6 @@
|
|||
#include <environment.h>
|
||||
#include <errno.h>
|
||||
#include <miiphy.h>
|
||||
#include <serial.h>
|
||||
#include <spl.h>
|
||||
#include <watchdog.h>
|
||||
|
||||
|
|
@ -69,13 +68,6 @@ static void enable_board_pin_mux(void)
|
|||
}
|
||||
#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
|
||||
|
||||
#ifndef CONFIG_DM_SERIAL
|
||||
struct serial_device *default_serial_console(void)
|
||||
{
|
||||
return &eserial1_device;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
|
||||
void set_uart_mux_conf(void)
|
||||
{
|
||||
|
|
@ -150,56 +142,3 @@ int board_late_init(void)
|
|||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if !defined(CONFIG_DM_ETH) && defined(CONFIG_DRIVER_TI_CPSW) && \
|
||||
!defined(CONFIG_SPL_BUILD)
|
||||
static void cpsw_control(int enabled)
|
||||
{
|
||||
/* VTP can be added here */
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
static struct cpsw_slave_data cpsw_slaves[] = {
|
||||
{
|
||||
.slave_reg_ofs = 0x208,
|
||||
.sliver_reg_ofs = 0xd80,
|
||||
.phy_addr = 0,
|
||||
}
|
||||
};
|
||||
|
||||
static struct cpsw_platform_data cpsw_data = {
|
||||
.mdio_base = CPSW_MDIO_BASE,
|
||||
.cpsw_base = CPSW_BASE,
|
||||
.mdio_div = 0xff,
|
||||
.channels = 8,
|
||||
.cpdma_reg_ofs = 0x800,
|
||||
.slaves = 1,
|
||||
.slave_data = cpsw_slaves,
|
||||
.ale_reg_ofs = 0xd00,
|
||||
.ale_entries = 1024,
|
||||
.host_port_reg_ofs = 0x108,
|
||||
.hw_stats_reg_ofs = 0x900,
|
||||
.bd_ram_ofs = 0x2000,
|
||||
.mac_control = (1 << 5),
|
||||
.control = cpsw_control,
|
||||
.host_port_num = 0,
|
||||
.version = CPSW_CTRL_VERSION_2,
|
||||
};
|
||||
|
||||
int board_eth_init(bd_t *bis)
|
||||
{
|
||||
int rv, n = 0;
|
||||
|
||||
writel(RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE, &cdev->miisel);
|
||||
cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RMII;
|
||||
|
||||
rv = cpsw_register(&cpsw_data);
|
||||
if (rv < 0)
|
||||
printf("Error %d registering CPSW switch\n", rv);
|
||||
else
|
||||
n += rv;
|
||||
|
||||
return n;
|
||||
}
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -253,6 +253,7 @@ static struct bootmenu_data *bootmenu_create(int delay)
|
|||
|
||||
int len;
|
||||
char *sep;
|
||||
char *default_str;
|
||||
struct bootmenu_entry *entry;
|
||||
|
||||
menu = malloc(sizeof(struct bootmenu_data));
|
||||
|
|
@ -263,6 +264,10 @@ static struct bootmenu_data *bootmenu_create(int delay)
|
|||
menu->active = 0;
|
||||
menu->first = NULL;
|
||||
|
||||
default_str = env_get("bootmenu_default");
|
||||
if (default_str)
|
||||
menu->active = (int)simple_strtol(default_str, NULL, 10);
|
||||
|
||||
while ((option = bootmenu_getoption(i))) {
|
||||
sep = strchr(option, '=');
|
||||
if (!sep) {
|
||||
|
|
|
|||
|
|
@ -29,19 +29,27 @@ CONFIG_CMD_EXT4_WRITE=y
|
|||
CONFIG_CMD_MTDPARTS=y
|
||||
CONFIG_MTDIDS_DEFAULT="nand0=8000000.nand"
|
||||
CONFIG_MTDPARTS_DEFAULT="mtdparts=8000000.nand:128k(NAND.SPL),128k(NAND.SPL.backup1),128k(NAND.SPL.backup2),128k(NAND.SPL.backup3),256k(NAND.u-boot-spl-os),1m(NAND.u-boot),128k(NAND.u-boot-env),128k(NAND.u-boot-env.backup1),8m(NAND.kernel),-(NAND.file-system)"
|
||||
CONFIG_OF_CONTROL=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="am335x-chiliboard"
|
||||
CONFIG_ENV_IS_IN_MMC=y
|
||||
CONFIG_BOOTCOUNT_LIMIT=y
|
||||
CONFIG_DM_GPIO=y
|
||||
CONFIG_MISC=y
|
||||
CONFIG_DM_MMC=y
|
||||
CONFIG_MMC_OMAP_HS=y
|
||||
CONFIG_NAND=y
|
||||
CONFIG_DRIVER_TI_CPSW=y
|
||||
CONFIG_DM_ETH=y
|
||||
CONFIG_MII=y
|
||||
CONFIG_DRIVER_TI_CPSW=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_OMAP3_SPI=y
|
||||
CONFIG_TIMER=y
|
||||
CONFIG_OMAP_TIMER=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_DM_USB=y
|
||||
CONFIG_USB_MUSB_HOST=y
|
||||
CONFIG_USB_MUSB_DSPS=y
|
||||
CONFIG_USB_MUSB_TI=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_FAT_WRITE=y
|
||||
CONFIG_LZO=y
|
||||
CONFIG_OF_LIBFDT=y
|
||||
|
|
|
|||
|
|
@ -23,12 +23,14 @@ CONFIG_CMD_ARMFLASH=y
|
|||
# CONFIG_CMD_NFS is not set
|
||||
CONFIG_CMD_CACHE=y
|
||||
# CONFIG_CMD_MISC is not set
|
||||
CONFIG_CMD_UBI=y
|
||||
# CONFIG_ISO_PARTITION is not set
|
||||
# CONFIG_EFI_PARTITION is not set
|
||||
CONFIG_ENV_IS_IN_FLASH=y
|
||||
CONFIG_DM=y
|
||||
# CONFIG_MMC is not set
|
||||
CONFIG_MTD_NOR_FLASH=y
|
||||
CONFIG_MTD_DEVICE=y
|
||||
CONFIG_FLASH_CFI_DRIVER=y
|
||||
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
|
||||
CONFIG_SYS_FLASH_PROTECTION=y
|
||||
|
|
|
|||
|
|
@ -23,12 +23,14 @@ CONFIG_CMD_ARMFLASH=y
|
|||
# CONFIG_CMD_NFS is not set
|
||||
CONFIG_CMD_CACHE=y
|
||||
# CONFIG_CMD_MISC is not set
|
||||
CONFIG_CMD_UBI=y
|
||||
# CONFIG_ISO_PARTITION is not set
|
||||
# CONFIG_EFI_PARTITION is not set
|
||||
CONFIG_ENV_IS_IN_FLASH=y
|
||||
CONFIG_DM=y
|
||||
# CONFIG_MMC is not set
|
||||
CONFIG_MTD_NOR_FLASH=y
|
||||
CONFIG_MTD_DEVICE=y
|
||||
CONFIG_FLASH_CFI_DRIVER=y
|
||||
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
|
||||
CONFIG_SYS_FLASH_PROTECTION=y
|
||||
|
|
|
|||
|
|
@ -23,12 +23,14 @@ CONFIG_CMD_ARMFLASH=y
|
|||
# CONFIG_CMD_NFS is not set
|
||||
CONFIG_CMD_CACHE=y
|
||||
# CONFIG_CMD_MISC is not set
|
||||
CONFIG_CMD_UBI=y
|
||||
# CONFIG_ISO_PARTITION is not set
|
||||
# CONFIG_EFI_PARTITION is not set
|
||||
CONFIG_ENV_IS_IN_FLASH=y
|
||||
CONFIG_DM=y
|
||||
# CONFIG_MMC is not set
|
||||
CONFIG_MTD_NOR_FLASH=y
|
||||
CONFIG_MTD_DEVICE=y
|
||||
CONFIG_FLASH_CFI_DRIVER=y
|
||||
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
|
||||
CONFIG_SYS_FLASH_PROTECTION=y
|
||||
|
|
|
|||
|
|
@ -18,8 +18,10 @@ CONFIG_CMD_MMC=y
|
|||
# CONFIG_CMD_SETEXPR is not set
|
||||
# CONFIG_CMD_NFS is not set
|
||||
# CONFIG_CMD_MISC is not set
|
||||
CONFIG_CMD_UBI=y
|
||||
CONFIG_ENV_IS_IN_FLASH=y
|
||||
CONFIG_MTD_NOR_FLASH=y
|
||||
CONFIG_MTD_DEVICE=y
|
||||
CONFIG_FLASH_CFI_DRIVER=y
|
||||
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
|
||||
CONFIG_SYS_FLASH_PROTECTION=y
|
||||
|
|
|
|||
|
|
@ -17,8 +17,10 @@ CONFIG_CMD_MMC=y
|
|||
# CONFIG_CMD_SETEXPR is not set
|
||||
# CONFIG_CMD_NFS is not set
|
||||
# CONFIG_CMD_MISC is not set
|
||||
CONFIG_CMD_UBI=y
|
||||
CONFIG_ENV_IS_IN_FLASH=y
|
||||
CONFIG_MTD_NOR_FLASH=y
|
||||
CONFIG_MTD_DEVICE=y
|
||||
CONFIG_FLASH_CFI_DRIVER=y
|
||||
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
|
||||
CONFIG_SYS_FLASH_PROTECTION=y
|
||||
|
|
|
|||
|
|
@ -17,8 +17,10 @@ CONFIG_CMD_MMC=y
|
|||
# CONFIG_CMD_SETEXPR is not set
|
||||
# CONFIG_CMD_NFS is not set
|
||||
# CONFIG_CMD_MISC is not set
|
||||
CONFIG_CMD_UBI=y
|
||||
CONFIG_ENV_IS_IN_FLASH=y
|
||||
CONFIG_MTD_NOR_FLASH=y
|
||||
CONFIG_MTD_DEVICE=y
|
||||
CONFIG_FLASH_CFI_DRIVER=y
|
||||
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
|
||||
CONFIG_SYS_FLASH_PROTECTION=y
|
||||
|
|
|
|||
|
|
@ -29,7 +29,9 @@
|
|||
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "tispl.bin"
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_CPU_V7R
|
||||
#define CONFIG_SKIP_LOWLEVEL_INIT
|
||||
#endif
|
||||
|
||||
#define CONFIG_SPL_MAX_SIZE CONFIG_SYS_K3_MAX_DOWNLODABLE_IMAGE_SIZE
|
||||
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SPL_TEXT_BASE + \
|
||||
|
|
|
|||
|
|
@ -124,8 +124,9 @@
|
|||
#ifdef CONFIG_SPL_BUILD
|
||||
#define CONFIG_SYS_SPI_BASE DAVINCI_SPI1_BASE
|
||||
#define CONFIG_SF_DEFAULT_SPEED 30000000
|
||||
#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
|
||||
#endif
|
||||
#define CONFIG_ENV_SPI_MAX_HZ 0
|
||||
#define CONFIG_ENV_SPI_MODE 0
|
||||
|
||||
#ifdef CONFIG_USE_SPIFLASH
|
||||
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8000
|
||||
|
|
|
|||
|
|
@ -29,7 +29,6 @@
|
|||
* High Level Configuration Options (easy to change)
|
||||
*/
|
||||
|
||||
#define CONFIG_MARVELL 1
|
||||
#define CONFIG_FEROCEON 1 /* CPU Core subversion */
|
||||
#define CONFIG_88F5182 1 /* SOC Name */
|
||||
|
||||
|
|
|
|||
|
|
@ -22,7 +22,6 @@
|
|||
/*
|
||||
* High Level Configuration Options (easy to change)
|
||||
*/
|
||||
#define CONFIG_MARVELL
|
||||
#define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */
|
||||
#define CONFIG_KW88F6281 /* SOC Name */
|
||||
|
||||
|
|
|
|||
|
|
@ -19,7 +19,6 @@
|
|||
/*
|
||||
* High Level Configuration Options (easy to change)
|
||||
*/
|
||||
#define CONFIG_MARVELL 1
|
||||
|
||||
/*
|
||||
* Custom CONFIG_SYS_TEXT_BASE can be done in <board>.h
|
||||
|
|
|
|||
|
|
@ -120,7 +120,7 @@
|
|||
#define CONFIG_INITRD_TAG 1
|
||||
|
||||
/* Size of malloc() pool */
|
||||
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024)
|
||||
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 512 * 1024) /* >= 512 KiB */
|
||||
|
||||
#define SCTL_BASE V2M_SYSCTL
|
||||
#define VEXPRESS_FLASHPROG_FLVPPEN (1 << 0)
|
||||
|
|
|
|||
|
|
@ -34,9 +34,9 @@
|
|||
"partitions_android=" \
|
||||
"uuid_disk=${uuid_gpt_disk};" \
|
||||
"name=xloader,start=128K,size=256K,uuid=${uuid_gpt_xloader};" \
|
||||
"name=bootloader,size=1792K,uuid=${uuid_gpt_bootloader};" \
|
||||
"name=bootloader,size=2048K,uuid=${uuid_gpt_bootloader};" \
|
||||
"name=reserved,start=2432K,size=256K,uuid=${uuid_gpt_reserved};" \
|
||||
"name=misc,size=128K,uuid=${uuid_gpt_misc};" \
|
||||
"name=reserved,size=256K,uuid=${uuid_gpt_reserved};" \
|
||||
"name=efs,size=16M,uuid=${uuid_gpt_efs};" \
|
||||
"name=crypto,size=16K,uuid=${uuid_gpt_crypto};" \
|
||||
"name=recovery,size=40M,uuid=${uuid_gpt_recovery};" \
|
||||
|
|
|
|||
|
|
@ -1199,7 +1199,6 @@ CONFIG_MALLOC_F_ADDR
|
|||
CONFIG_MALTA
|
||||
CONFIG_MARCO_MEMSET
|
||||
CONFIG_MARUBUN_PCCARD
|
||||
CONFIG_MARVELL
|
||||
CONFIG_MARVELL_GPIO
|
||||
CONFIG_MARVELL_MFP
|
||||
CONFIG_MASK_AER_AO
|
||||
|
|
|
|||
|
|
@ -18,7 +18,6 @@
|
|||
#include <stdio.h>
|
||||
#include <stdlib.h>
|
||||
#include <stdint.h>
|
||||
#include <malloc.h>
|
||||
|
||||
/* Size of the blocks written to the compressed file */
|
||||
#define BLOCK_SIZE 8
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue