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https://github.com/Fishwaldo/u-boot.git
synced 2025-03-18 13:11:31 +00:00
mx6: Factor out common HDMI setup code
Instead of duplicating HDMI setup code for every mx6 board, factor out the common code Signed-off-by: Pardeep Kumar Singla <b45784@freescale.com> Acked-By: Eric Nelson <eric.nelson@boundarydevices.com>
This commit is contained in:
parent
f8b1e86d47
commit
5ea7f0e328
8 changed files with 70 additions and 78 deletions
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@ -468,6 +468,14 @@ int do_mx6_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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return 0;
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}
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void enable_ipu_clock(void)
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{
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struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
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int reg;
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reg = readl(&mxc_ccm->CCGR3);
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reg |= MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET;
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writel(reg, &mxc_ccm->CCGR3);
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}
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/***************************************************/
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U_BOOT_CMD(
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@ -32,6 +32,8 @@
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#include <asm/imx-common/boot_mode.h>
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#include <asm/imx-common/dma.h>
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#include <stdbool.h>
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#include <asm/arch/mxc_hdmi.h>
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#include <asm/arch/crm_regs.h>
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struct scu_regs {
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u32 ctrl;
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@ -228,3 +230,44 @@ const struct boot_mode soc_boot_modes[] = {
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void s_init(void)
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{
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}
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#ifdef CONFIG_IMX_HDMI
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void imx_enable_hdmi_phy(void)
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{
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struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
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u8 reg;
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reg = readb(&hdmi->phy_conf0);
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reg |= HDMI_PHY_CONF0_PDZ_MASK;
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writeb(reg, &hdmi->phy_conf0);
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udelay(3000);
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reg |= HDMI_PHY_CONF0_ENTMDS_MASK;
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writeb(reg, &hdmi->phy_conf0);
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udelay(3000);
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reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK;
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writeb(reg, &hdmi->phy_conf0);
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writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz);
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}
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void imx_setup_hdmi(void)
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{
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struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
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struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
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int reg;
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/* Turn on HDMI PHY clock */
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reg = readl(&mxc_ccm->CCGR2);
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reg |= MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK|
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MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK;
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writel(reg, &mxc_ccm->CCGR2);
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writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz);
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reg = readl(&mxc_ccm->chsccdr);
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reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK|
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MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK|
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MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
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reg |= (CHSCCDR_PODF_DIVIDE_BY_3
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<< MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET)
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|(CHSCCDR_IPU_PRE_CLK_540M_PFD
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<< MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
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writel(reg, &mxc_ccm->chsccdr);
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}
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#endif
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@ -65,5 +65,5 @@ void enable_ocotp_clk(unsigned char enable);
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void enable_usboh3_clk(unsigned char enable);
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int enable_sata_clock(void);
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int enable_i2c_clk(unsigned char enable, unsigned i2c_num);
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void enable_ipu_clock(void);
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#endif /* __ASM_ARCH_CLOCK_H */
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@ -21,6 +21,11 @@
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#ifndef __MXC_HDMI_H__
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#define __MXC_HDMI_H__
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#ifdef CONFIG_IMX_HDMI
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void imx_enable_hdmi_phy(void);
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void imx_setup_hdmi(void);
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#endif
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/*
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* Hdmi controller registers
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*/
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@ -480,22 +480,9 @@ static int detect_hdmi(struct display_info_t const *dev)
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return readb(&hdmi->phy_stat0) & HDMI_PHY_HPD;
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}
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static void enable_hdmi(struct display_info_t const *dev)
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static void do_enable_hdmi(struct display_info_t const *dev)
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{
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struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
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u8 reg;
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printf("%s: setup HDMI monitor\n", __func__);
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reg = readb(&hdmi->phy_conf0);
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reg |= HDMI_PHY_CONF0_PDZ_MASK;
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writeb(reg, &hdmi->phy_conf0);
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udelay(3000);
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reg |= HDMI_PHY_CONF0_ENTMDS_MASK;
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writeb(reg, &hdmi->phy_conf0);
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udelay(3000);
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reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK;
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writeb(reg, &hdmi->phy_conf0);
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writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz);
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imx_enable_hdmi_phy();
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}
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static int detect_i2c(struct display_info_t const *dev)
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@ -528,7 +515,7 @@ static struct display_info_t const displays[] = {{
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.addr = 0,
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.pixfmt = IPU_PIX_FMT_RGB24,
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.detect = detect_hdmi,
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.enable = enable_hdmi,
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.enable = do_enable_hdmi,
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.mode = {
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.name = "HDMI",
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.refresh = 60,
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@ -653,25 +640,15 @@ static void setup_display(void)
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struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
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struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
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struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
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struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
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int reg;
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enable_ipu_clock();
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imx_setup_hdmi();
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/* Turn on LDB0,IPU,IPU DI0 clocks */
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reg = __raw_readl(&mxc_ccm->CCGR3);
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reg |= MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET
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|MXC_CCM_CCGR3_LDB_DI0_MASK;
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reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
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writel(reg, &mxc_ccm->CCGR3);
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/* Turn on HDMI PHY clock */
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reg = __raw_readl(&mxc_ccm->CCGR2);
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reg |= MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK
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|MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK;
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writel(reg, &mxc_ccm->CCGR2);
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/* clear HDMI PHY reset */
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writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz);
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/* set PFD1_FRAC to 0x13 == 455 MHz (480*18)/0x13 */
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writel(ANATOP_PFD_480_PFD1_FRAC_MASK, &anatop->pfd_480_clr);
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writel(0x13<<ANATOP_PFD_480_PFD1_FRAC_SHIFT, &anatop->pfd_480_set);
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@ -689,15 +666,8 @@ static void setup_display(void)
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writel(reg, &mxc_ccm->cscmr2);
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reg = readl(&mxc_ccm->chsccdr);
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reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK
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|MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK
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|MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
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reg |= (CHSCCDR_CLK_SEL_LDB_DI0
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<<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET)
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|(CHSCCDR_PODF_DIVIDE_BY_3
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<<MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET)
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|(CHSCCDR_IPU_PRE_CLK_540M_PFD
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<<MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
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<<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
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writel(reg, &mxc_ccm->chsccdr);
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reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
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@ -211,23 +211,6 @@ int board_phy_config(struct phy_device *phydev)
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}
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#if defined(CONFIG_VIDEO_IPUV3)
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static void enable_hdmi(void)
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{
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struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
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u8 reg;
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reg = readb(&hdmi->phy_conf0);
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reg |= HDMI_PHY_CONF0_PDZ_MASK;
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writeb(reg, &hdmi->phy_conf0);
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udelay(3000);
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reg |= HDMI_PHY_CONF0_ENTMDS_MASK;
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writeb(reg, &hdmi->phy_conf0);
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udelay(3000);
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reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK;
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writeb(reg, &hdmi->phy_conf0);
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writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz);
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}
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static struct fb_videomode const hdmi = {
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.name = "HDMI",
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.refresh = 60,
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@ -253,7 +236,7 @@ int board_video_skip(void)
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if (ret)
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printf("HDMI cannot be configured: %d\n", ret);
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enable_hdmi();
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imx_enable_hdmi_phy();
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return ret;
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}
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@ -261,33 +244,14 @@ int board_video_skip(void)
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static void setup_display(void)
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{
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struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
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struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
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int reg;
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/* Turn on IPU clock */
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reg = readl(&mxc_ccm->CCGR3);
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reg |= MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET;
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writel(reg, &mxc_ccm->CCGR3);
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/* Turn on HDMI PHY clock */
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reg = readl(&mxc_ccm->CCGR2);
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reg |= MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK
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| MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK;
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writel(reg, &mxc_ccm->CCGR2);
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/* clear HDMI PHY reset */
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writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz);
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enable_ipu_clock();
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imx_setup_hdmi();
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reg = readl(&mxc_ccm->chsccdr);
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reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK
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| MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK
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| MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
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reg |= (CHSCCDR_CLK_SEL_LDB_DI0
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<< MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET)
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| (CHSCCDR_PODF_DIVIDE_BY_3
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<< MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET)
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| (CHSCCDR_IPU_PRE_CLK_540M_PFD
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<< MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
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<< MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
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writel(reg, &mxc_ccm->chsccdr);
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}
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#endif /* CONFIG_VIDEO_IPUV3 */
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@ -154,6 +154,7 @@
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#define CONFIG_IPUV3_CLK 260000000
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#define CONFIG_CMD_HDMIDETECT
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#define CONFIG_CONSOLE_MUX
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#define CONFIG_IMX_HDMI
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/* allow to overwrite serial and ethaddr */
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#define CONFIG_ENV_OVERWRITE
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@ -100,6 +100,7 @@
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#define CONFIG_VIDEO_LOGO
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#define CONFIG_VIDEO_BMP_LOGO
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#define CONFIG_IPUV3_CLK 260000000
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#define CONFIG_IMX_HDMI
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#if defined(CONFIG_MX6DL)
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#define CONFIG_DEFAULT_FDT_FILE "imx6dl-wandboard.dtb"
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