mirror of
https://github.com/Fishwaldo/u-boot.git
synced 2025-03-18 13:11:31 +00:00
Merge git://git.denx.de/u-boot
This commit is contained in:
commit
5f5620ab26
557 changed files with 13369 additions and 2269 deletions
10
Kconfig
10
Kconfig
|
@ -152,6 +152,16 @@ config SPL_STACK_R_MALLOC_SIMPLE_LEN
|
|||
to give board_init_r() a larger heap then the initial heap in
|
||||
SRAM which is limited to SYS_MALLOC_F_LEN bytes.
|
||||
|
||||
config SPL_SEPARATE_BSS
|
||||
depends on SPL
|
||||
bool "BSS section is in a different memory region from text"
|
||||
help
|
||||
Some platforms need a large BSS region in SPL and can provide this
|
||||
because RAM is already set up. In this case BSS can be moved to RAM.
|
||||
This option should then be enabled so that the correct device tree
|
||||
location is used. Normally we put the device tree at the end of BSS
|
||||
but with this option enabled, it goes at _image_binary_end.
|
||||
|
||||
config TPL
|
||||
bool
|
||||
depends on SPL && SUPPORT_TPL
|
||||
|
|
10
Makefile
10
Makefile
|
@ -1,3 +1,7 @@
|
|||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
VERSION = 2015
|
||||
PATCHLEVEL = 10
|
||||
SUBLEVEL =
|
||||
|
@ -605,6 +609,8 @@ KBUILD_CFLAGS += $(KCFLAGS)
|
|||
UBOOTINCLUDE := \
|
||||
-Iinclude \
|
||||
$(if $(KBUILD_SRC), -I$(srctree)/include) \
|
||||
$(if $(CONFIG_SYS_THUMB_BUILD), $(if $(CONFIG_HAS_THUMB2),, \
|
||||
-I$(srctree)/arch/$(ARCH)/thumb1/include),) \
|
||||
-I$(srctree)/arch/$(ARCH)/include \
|
||||
-include $(srctree)/include/linux/kconfig.h
|
||||
|
||||
|
@ -1130,7 +1136,11 @@ spl/u-boot-spl.pbl: spl/u-boot-spl.bin FORCE
|
|||
$(call if_changed,mkimage)
|
||||
|
||||
ifeq ($(ARCH),arm)
|
||||
ifdef CONFIG_DM
|
||||
UBOOT_BINLOAD := u-boot-dtb.img
|
||||
else
|
||||
UBOOT_BINLOAD := u-boot.img
|
||||
endif
|
||||
else
|
||||
UBOOT_BINLOAD := u-boot.bin
|
||||
endif
|
||||
|
|
|
@ -1,3 +1,7 @@
|
|||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
dtb-$(CONFIG_TARGET_ARCANGEL4) += arcangel4.dtb
|
||||
dtb-$(CONFIG_TARGET_TB100) += abilis_tb100.dtb
|
||||
|
||||
|
|
|
@ -16,4 +16,9 @@
|
|||
#define hweight16(x) generic_hweight16(x)
|
||||
#define hweight8(x) generic_hweight8(x)
|
||||
|
||||
#include <asm-generic/bitops/fls.h>
|
||||
#include <asm-generic/bitops/__fls.h>
|
||||
#include <asm-generic/bitops/fls64.h>
|
||||
#include <asm-generic/bitops/__ffs.h>
|
||||
|
||||
#endif /* __ASM_ARC_BITOPS_H */
|
||||
|
|
|
@ -10,6 +10,9 @@ config ARM64
|
|||
config HAS_VBAR
|
||||
bool
|
||||
|
||||
config HAS_THUMB2
|
||||
bool
|
||||
|
||||
config CPU_ARM720T
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||||
bool
|
||||
|
||||
|
@ -32,9 +35,11 @@ config CPU_ARM1176
|
|||
config CPU_V7
|
||||
bool
|
||||
select HAS_VBAR
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||||
select HAS_THUMB2
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||||
|
||||
config CPU_V7M
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||||
bool
|
||||
select HAS_THUMB2
|
||||
|
||||
config CPU_PXA
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||||
bool
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||||
|
@ -543,13 +548,20 @@ config ARCH_ZYNQ
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|||
select CPU_V7
|
||||
select SUPPORT_SPL
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||||
select OF_CONTROL
|
||||
select SPL_OF_CONTROL
|
||||
select DM
|
||||
select SPL_DM
|
||||
select DM_SPI
|
||||
select DM_SERIAL
|
||||
select DM_SPI_FLASH
|
||||
select SPL_SEPARATE_BSS
|
||||
|
||||
config ARCH_ZYNQMP
|
||||
bool "Support Xilinx ZynqMP Platform"
|
||||
select ARM64
|
||||
select DM
|
||||
select OF_CONTROL
|
||||
select DM_SERIAL
|
||||
|
||||
config TEGRA
|
||||
bool "NVIDIA Tegra"
|
||||
|
@ -627,6 +639,14 @@ config TARGET_LS1021ATWR
|
|||
select CPU_V7
|
||||
select SUPPORT_SPL
|
||||
|
||||
config TARGET_LS1043ARDB
|
||||
bool "Support ls1043ardb"
|
||||
select ARM64
|
||||
select ARMV8_MULTIENTRY
|
||||
select SUPPORT_SPL
|
||||
help
|
||||
Support for Freescale LS1043ARDB platform.
|
||||
|
||||
config TARGET_H2200
|
||||
bool "Support h2200"
|
||||
select CPU_PXA
|
||||
|
@ -743,6 +763,7 @@ source "board/freescale/ls2085aqds/Kconfig"
|
|||
source "board/freescale/ls2085ardb/Kconfig"
|
||||
source "board/freescale/ls1021aqds/Kconfig"
|
||||
source "board/freescale/ls1021atwr/Kconfig"
|
||||
source "board/freescale/ls1043ardb/Kconfig"
|
||||
source "board/freescale/mx23evk/Kconfig"
|
||||
source "board/freescale/mx25pdk/Kconfig"
|
||||
source "board/freescale/mx28evk/Kconfig"
|
||||
|
|
|
@ -1 +1,5 @@
|
|||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
obj- += dummy.o
|
||||
|
|
|
@ -20,3 +20,14 @@ obj-$(CONFIG_MX25) += mx25/
|
|||
obj-$(CONFIG_MX27) += mx27/
|
||||
obj-$(if $(filter mxs,$(SOC)),y) += mxs/
|
||||
obj-$(if $(filter spear,$(SOC)),y) += spear/
|
||||
|
||||
# some files can only build in ARM or THUMB2, not THUMB1
|
||||
|
||||
ifdef CONFIG_SYS_THUMB_BUILD
|
||||
ifndef CONFIG_HAS_THUMB2
|
||||
|
||||
CFLAGS_cpu.o := -marm
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||||
CFLAGS_cache.o := -marm
|
||||
|
||||
endif
|
||||
endif
|
||||
|
|
|
@ -82,4 +82,9 @@ void flush_dcache_all(void)
|
|||
/*
|
||||
* Stub implementations for l2 cache operations
|
||||
*/
|
||||
|
||||
__weak void l2_cache_disable(void) {}
|
||||
|
||||
#if defined CONFIG_SYS_THUMB_BUILD
|
||||
__weak void invalidate_l2_cache(void) {}
|
||||
#endif
|
||||
|
|
|
@ -9,6 +9,7 @@ obj-y += clock.o
|
|||
obj-y += timer.o
|
||||
obj-y += fsl_epu.o
|
||||
|
||||
obj-$(CONFIG_SCSI_AHCI_PLAT) += ls102xa_sata.o
|
||||
obj-$(CONFIG_OF_LIBFDT) += fdt.o
|
||||
obj-$(CONFIG_SYS_HAS_SERDES) += fsl_ls1_serdes.o ls102xa_serdes.o
|
||||
obj-$(CONFIG_SPL) += spl.o
|
||||
|
|
|
@ -301,6 +301,7 @@ int arch_cpu_init(void)
|
|||
void *epu_base = (void *)(CONFIG_SYS_DCSRBAR + EPU_BLOCK_OFFSET);
|
||||
void *rcpm2_base =
|
||||
(void *)(CONFIG_SYS_DCSRBAR + DCSR_RCPM2_BLOCK_OFFSET);
|
||||
struct ccsr_scfg *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
|
||||
u32 state;
|
||||
|
||||
/*
|
||||
|
@ -328,6 +329,8 @@ int arch_cpu_init(void)
|
|||
*/
|
||||
fsl_epu_clean(epu_base);
|
||||
|
||||
setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SEC_RD_WR);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
@ -171,7 +171,7 @@ void ft_cpu_setup(void *blob, bd_t *bd)
|
|||
do_fixup_by_compat_u32(blob, "fsl, ls1021a-flexcan",
|
||||
"clock-frequency", busclk / 2, 1);
|
||||
|
||||
#ifdef CONFIG_QSPI_BOOT
|
||||
#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
|
||||
off = fdt_node_offset_by_compat_reg(blob, FSL_IFC_COMPAT,
|
||||
CONFIG_SYS_IFC_ADDR);
|
||||
fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
|
||||
|
|
42
arch/arm/cpu/armv7/ls102xa/ls102xa_sata.c
Normal file
42
arch/arm/cpu/armv7/ls102xa/ls102xa_sata.c
Normal file
|
@ -0,0 +1,42 @@
|
|||
/*
|
||||
* Copyright 2015 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
#include <common.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/immap_ls102xa.h>
|
||||
#include <ahci.h>
|
||||
#include <scsi.h>
|
||||
|
||||
/* port register default value */
|
||||
#define AHCI_PORT_PHY_1_CFG 0xa003fffe
|
||||
#define AHCI_PORT_PHY_2_CFG 0x28183411
|
||||
#define AHCI_PORT_PHY_3_CFG 0x0e081004
|
||||
#define AHCI_PORT_PHY_4_CFG 0x00480811
|
||||
#define AHCI_PORT_PHY_5_CFG 0x192c96a4
|
||||
#define AHCI_PORT_TRANS_CFG 0x08000025
|
||||
|
||||
#define SATA_ECC_REG_ADDR 0x20220520
|
||||
#define SATA_ECC_DISABLE 0x00020000
|
||||
|
||||
int ls1021a_sata_init(void)
|
||||
{
|
||||
struct ccsr_ahci __iomem *ccsr_ahci = (void *)AHCI_BASE_ADDR;
|
||||
|
||||
#ifdef CONFIG_SYS_FSL_ERRATUM_A008407
|
||||
out_le32((void *)SATA_ECC_REG_ADDR, SATA_ECC_DISABLE);
|
||||
#endif
|
||||
|
||||
out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
|
||||
out_le32(&ccsr_ahci->pp2c, AHCI_PORT_PHY_2_CFG);
|
||||
out_le32(&ccsr_ahci->pp3c, AHCI_PORT_PHY_3_CFG);
|
||||
out_le32(&ccsr_ahci->pp4c, AHCI_PORT_PHY_4_CFG);
|
||||
out_le32(&ccsr_ahci->pp5c, AHCI_PORT_PHY_5_CFG);
|
||||
out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
|
||||
|
||||
ahci_init((void __iomem *)AHCI_BASE_ADDR);
|
||||
scsi_scan(0);
|
||||
|
||||
return 0;
|
||||
}
|
|
@ -5,9 +5,12 @@
|
|||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
#include <common.h>
|
||||
#include <fdtdec.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/clk.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
/* Default is s5pc100 */
|
||||
unsigned int s5p_cpu_id = 0xC100;
|
||||
/* Default is EVT1 */
|
||||
|
@ -30,7 +33,16 @@ u32 get_device_type(void)
|
|||
#ifdef CONFIG_DISPLAY_CPUINFO
|
||||
int print_cpuinfo(void)
|
||||
{
|
||||
printf("CPU: %s%X @ ", s5p_get_cpu_name(), s5p_cpu_id);
|
||||
const char *cpu_model;
|
||||
int len;
|
||||
|
||||
/* For SoC with no real CPU ID in naming convention. */
|
||||
cpu_model = fdt_getprop(gd->fdt_blob, 0, "cpu-model", &len);
|
||||
if (cpu_model)
|
||||
printf("CPU: %.*s @ ", len, cpu_model);
|
||||
else
|
||||
printf("CPU: %s%X @ ", s5p_get_cpu_name(), s5p_cpu_id);
|
||||
|
||||
print_freq(get_arm_clk(), "\n");
|
||||
|
||||
return 0;
|
||||
|
|
|
@ -97,6 +97,9 @@ int flash_erase(flash_info_t *info, int first, int last)
|
|||
while (readl(&STM32_FLASH->sr) & STM32_FLASH_SR_BSY)
|
||||
;
|
||||
|
||||
/* clear old sector number before writing a new one */
|
||||
clrbits_le32(&STM32_FLASH->cr, STM32_FLASH_CR_SNB_MASK);
|
||||
|
||||
if (bank == 0) {
|
||||
setbits_le32(&STM32_FLASH->cr,
|
||||
(i << STM32_FLASH_CR_SNB_OFFSET));
|
||||
|
@ -114,9 +117,9 @@ int flash_erase(flash_info_t *info, int first, int last)
|
|||
;
|
||||
|
||||
clrbits_le32(&STM32_FLASH->cr, STM32_FLASH_CR_SER);
|
||||
stm32f4_flash_lock(1);
|
||||
}
|
||||
|
||||
stm32f4_flash_lock(1);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
@ -15,6 +15,6 @@ obj-y += cache.o
|
|||
obj-y += tlb.o
|
||||
obj-y += transition.o
|
||||
|
||||
obj-$(CONFIG_FSL_LSCH3) += fsl-lsch3/
|
||||
obj-$(CONFIG_FSL_LAYERSCAPE) += fsl-layerscape/
|
||||
obj-$(CONFIG_ARCH_ZYNQMP) += zynqmp/
|
||||
obj-$(CONFIG_TARGET_HIKEY) += hisilicon/
|
||||
|
|
|
@ -32,7 +32,7 @@ inline void set_pgtable_table(u64 *page_table, u64 index, u64 *table_addr)
|
|||
}
|
||||
|
||||
/* to activate the MMU we need to set up virtual memory */
|
||||
static void mmu_setup(void)
|
||||
__weak void mmu_setup(void)
|
||||
{
|
||||
bd_t *bd = gd->bd;
|
||||
u64 *page_table = (u64 *)gd->arch.tlb_addr, i, j;
|
||||
|
|
30
arch/arm/cpu/armv8/fsl-layerscape/Makefile
Normal file
30
arch/arm/cpu/armv8/fsl-layerscape/Makefile
Normal file
|
@ -0,0 +1,30 @@
|
|||
#
|
||||
# Copyright 2014-2015, Freescale Semiconductor
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
obj-y += cpu.o
|
||||
obj-y += lowlevel.o
|
||||
obj-y += soc.o
|
||||
obj-$(CONFIG_MP) += mp.o
|
||||
obj-$(CONFIG_OF_LIBFDT) += fdt.o
|
||||
obj-$(CONFIG_SPL) += spl.o
|
||||
|
||||
ifneq ($(CONFIG_FSL_LSCH3),)
|
||||
obj-y += fsl_lsch3_speed.o
|
||||
obj-$(CONFIG_SYS_HAS_SERDES) += fsl_lsch3_serdes.o
|
||||
else
|
||||
ifneq ($(CONFIG_FSL_LSCH2),)
|
||||
obj-y += fsl_lsch2_speed.o
|
||||
obj-$(CONFIG_SYS_HAS_SERDES) += fsl_lsch2_serdes.o
|
||||
endif
|
||||
endif
|
||||
|
||||
ifneq ($(CONFIG_LS2085A),)
|
||||
obj-$(CONFIG_SYS_HAS_SERDES) += ls2085a_serdes.o
|
||||
else
|
||||
ifneq ($(CONFIG_LS1043A),)
|
||||
obj-$(CONFIG_SYS_HAS_SERDES) += ls1043a_serdes.o
|
||||
endif
|
||||
endif
|
10
arch/arm/cpu/armv8/fsl-layerscape/README.lsch2
Normal file
10
arch/arm/cpu/armv8/fsl-layerscape/README.lsch2
Normal file
|
@ -0,0 +1,10 @@
|
|||
#
|
||||
# Copyright 2015 Freescale Semiconductor
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
Freescale LayerScape with Chassis Generation 2
|
||||
|
||||
This architecture supports Freescale ARMv8 SoCs with Chassis generation 2,
|
||||
for example LS1043A.
|
|
@ -1,5 +1,5 @@
|
|||
#
|
||||
# Copyright 2014 Freescale Semiconductor
|
||||
# Copyright 2014-2015 Freescale Semiconductor
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright 2014 Freescale Semiconductor, Inc.
|
||||
* Copyright 2014-2015 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
@ -10,34 +10,28 @@
|
|||
#include <asm/system.h>
|
||||
#include <asm/armv8/mmu.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch-fsl-lsch3/soc.h>
|
||||
#include <asm/arch-fsl-lsch3/immap_lsch3.h>
|
||||
#include <asm/arch/fsl_serdes.h>
|
||||
#include <asm/arch/soc.h>
|
||||
#include <asm/arch/cpu.h>
|
||||
#include <asm/arch/speed.h>
|
||||
#ifdef CONFIG_MP
|
||||
#include <asm/arch/mp.h>
|
||||
#endif
|
||||
#include <fm_eth.h>
|
||||
#include <fsl_debug_server.h>
|
||||
#include <fsl-mc/fsl_mc.h>
|
||||
#include <asm/arch/fsl_serdes.h>
|
||||
#ifdef CONFIG_FSL_ESDHC
|
||||
#include <fsl_esdhc.h>
|
||||
#endif
|
||||
#include "cpu.h"
|
||||
#include "mp.h"
|
||||
#include "speed.h"
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
static struct cpu_type cpu_type_list[] = {
|
||||
#ifdef CONFIG_LS2085A
|
||||
CPU_TYPE_ENTRY(LS2085, LS2085, 8),
|
||||
CPU_TYPE_ENTRY(LS2080, LS2080, 8),
|
||||
CPU_TYPE_ENTRY(LS2045, LS2045, 4),
|
||||
#endif
|
||||
};
|
||||
|
||||
void cpu_name(char *name)
|
||||
{
|
||||
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
|
||||
unsigned int i, svr, ver;
|
||||
|
||||
svr = in_le32(&gur->svr);
|
||||
svr = gur_in32(&gur->svr);
|
||||
ver = SVR_SOC_VER(svr);
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++)
|
||||
|
@ -54,146 +48,6 @@ void cpu_name(char *name)
|
|||
}
|
||||
|
||||
#ifndef CONFIG_SYS_DCACHE_OFF
|
||||
|
||||
#define SECTION_SHIFT_L0 39UL
|
||||
#define SECTION_SHIFT_L1 30UL
|
||||
#define SECTION_SHIFT_L2 21UL
|
||||
#define BLOCK_SIZE_L0 0x8000000000
|
||||
#define BLOCK_SIZE_L1 0x40000000
|
||||
#define BLOCK_SIZE_L2 0x200000
|
||||
|
||||
#define NUM_OF_ENTRY 512
|
||||
|
||||
#define TCR_EL2_PS_40BIT (2 << 16)
|
||||
#define LSCH3_VA_BITS (40)
|
||||
#define LSCH3_TCR (TCR_TG0_4K | \
|
||||
TCR_EL2_PS_40BIT | \
|
||||
TCR_SHARED_NON | \
|
||||
TCR_ORGN_NC | \
|
||||
TCR_IRGN_NC | \
|
||||
TCR_T0SZ(LSCH3_VA_BITS))
|
||||
#define LSCH3_TCR_FINAL (TCR_TG0_4K | \
|
||||
TCR_EL2_PS_40BIT | \
|
||||
TCR_SHARED_OUTER | \
|
||||
TCR_ORGN_WBWA | \
|
||||
TCR_IRGN_WBWA | \
|
||||
TCR_T0SZ(LSCH3_VA_BITS))
|
||||
|
||||
#define CONFIG_SYS_FSL_CCSR_BASE 0x00000000
|
||||
#define CONFIG_SYS_FSL_CCSR_SIZE 0x10000000
|
||||
#define CONFIG_SYS_FSL_QSPI_BASE1 0x20000000
|
||||
#define CONFIG_SYS_FSL_QSPI_SIZE1 0x10000000
|
||||
#define CONFIG_SYS_FSL_IFC_BASE1 0x30000000
|
||||
#define CONFIG_SYS_FSL_IFC_SIZE1 0x10000000
|
||||
#define CONFIG_SYS_FSL_IFC_SIZE1_1 0x400000
|
||||
#define CONFIG_SYS_FSL_DRAM_BASE1 0x80000000
|
||||
#define CONFIG_SYS_FSL_DRAM_SIZE1 0x80000000
|
||||
#define CONFIG_SYS_FSL_QSPI_BASE2 0x400000000
|
||||
#define CONFIG_SYS_FSL_QSPI_SIZE2 0x100000000
|
||||
#define CONFIG_SYS_FSL_IFC_BASE2 0x500000000
|
||||
#define CONFIG_SYS_FSL_IFC_SIZE2 0x100000000
|
||||
#define CONFIG_SYS_FSL_DCSR_BASE 0x700000000
|
||||
#define CONFIG_SYS_FSL_DCSR_SIZE 0x40000000
|
||||
#define CONFIG_SYS_FSL_MC_BASE 0x80c000000
|
||||
#define CONFIG_SYS_FSL_MC_SIZE 0x4000000
|
||||
#define CONFIG_SYS_FSL_NI_BASE 0x810000000
|
||||
#define CONFIG_SYS_FSL_NI_SIZE 0x8000000
|
||||
#define CONFIG_SYS_FSL_QBMAN_BASE 0x818000000
|
||||
#define CONFIG_SYS_FSL_QBMAN_SIZE 0x8000000
|
||||
#define CONFIG_SYS_FSL_QBMAN_SIZE_1 0x4000000
|
||||
#define CONFIG_SYS_PCIE1_PHYS_SIZE 0x200000000
|
||||
#define CONFIG_SYS_PCIE2_PHYS_SIZE 0x200000000
|
||||
#define CONFIG_SYS_PCIE3_PHYS_SIZE 0x200000000
|
||||
#define CONFIG_SYS_PCIE4_PHYS_SIZE 0x200000000
|
||||
#define CONFIG_SYS_FSL_WRIOP1_BASE 0x4300000000
|
||||
#define CONFIG_SYS_FSL_WRIOP1_SIZE 0x100000000
|
||||
#define CONFIG_SYS_FSL_AIOP1_BASE 0x4b00000000
|
||||
#define CONFIG_SYS_FSL_AIOP1_SIZE 0x100000000
|
||||
#define CONFIG_SYS_FSL_PEBUF_BASE 0x4c00000000
|
||||
#define CONFIG_SYS_FSL_PEBUF_SIZE 0x400000000
|
||||
#define CONFIG_SYS_FSL_DRAM_BASE2 0x8080000000
|
||||
#define CONFIG_SYS_FSL_DRAM_SIZE2 0x7F80000000
|
||||
|
||||
struct sys_mmu_table {
|
||||
u64 virt_addr;
|
||||
u64 phys_addr;
|
||||
u64 size;
|
||||
u64 memory_type;
|
||||
u64 share;
|
||||
};
|
||||
|
||||
static const struct sys_mmu_table lsch3_early_mmu_table[] = {
|
||||
{ CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
|
||||
CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
|
||||
{ CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
|
||||
CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PMD_SECT_NON_SHARE },
|
||||
/* For IFC Region #1, only the first 4MB is cache-enabled */
|
||||
{ CONFIG_SYS_FSL_IFC_BASE1, CONFIG_SYS_FSL_IFC_BASE1,
|
||||
CONFIG_SYS_FSL_IFC_SIZE1_1, MT_NORMAL, PMD_SECT_NON_SHARE },
|
||||
{ CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1,
|
||||
CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1,
|
||||
CONFIG_SYS_FSL_IFC_SIZE1 - CONFIG_SYS_FSL_IFC_SIZE1_1,
|
||||
MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
|
||||
{ CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FSL_IFC_BASE1,
|
||||
CONFIG_SYS_FSL_IFC_SIZE1, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
|
||||
{ CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
|
||||
CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL, PMD_SECT_OUTER_SHARE },
|
||||
{ CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
|
||||
CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
|
||||
{ CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
|
||||
CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, PMD_SECT_OUTER_SHARE },
|
||||
};
|
||||
|
||||
static const struct sys_mmu_table lsch3_final_mmu_table[] = {
|
||||
{ CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
|
||||
CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
|
||||
{ CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
|
||||
CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PMD_SECT_NON_SHARE },
|
||||
{ CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
|
||||
CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL, PMD_SECT_OUTER_SHARE },
|
||||
{ CONFIG_SYS_FSL_QSPI_BASE2, CONFIG_SYS_FSL_QSPI_BASE2,
|
||||
CONFIG_SYS_FSL_QSPI_SIZE2, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
|
||||
{ CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2,
|
||||
CONFIG_SYS_FSL_IFC_SIZE2, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
|
||||
{ CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
|
||||
CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
|
||||
{ CONFIG_SYS_FSL_MC_BASE, CONFIG_SYS_FSL_MC_BASE,
|
||||
CONFIG_SYS_FSL_MC_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
|
||||
{ CONFIG_SYS_FSL_NI_BASE, CONFIG_SYS_FSL_NI_BASE,
|
||||
CONFIG_SYS_FSL_NI_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
|
||||
/* For QBMAN portal, only the first 64MB is cache-enabled */
|
||||
{ CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE,
|
||||
CONFIG_SYS_FSL_QBMAN_SIZE_1, MT_NORMAL, PMD_SECT_NON_SHARE },
|
||||
{ CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1,
|
||||
CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1,
|
||||
CONFIG_SYS_FSL_QBMAN_SIZE - CONFIG_SYS_FSL_QBMAN_SIZE_1,
|
||||
MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
|
||||
{ CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR,
|
||||
CONFIG_SYS_PCIE1_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
|
||||
{ CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR,
|
||||
CONFIG_SYS_PCIE2_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
|
||||
{ CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR,
|
||||
CONFIG_SYS_PCIE3_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
|
||||
#ifdef CONFIG_LS2085A
|
||||
{ CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_ADDR,
|
||||
CONFIG_SYS_PCIE4_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
|
||||
#endif
|
||||
{ CONFIG_SYS_FSL_WRIOP1_BASE, CONFIG_SYS_FSL_WRIOP1_BASE,
|
||||
CONFIG_SYS_FSL_WRIOP1_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
|
||||
{ CONFIG_SYS_FSL_AIOP1_BASE, CONFIG_SYS_FSL_AIOP1_BASE,
|
||||
CONFIG_SYS_FSL_AIOP1_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
|
||||
{ CONFIG_SYS_FSL_PEBUF_BASE, CONFIG_SYS_FSL_PEBUF_BASE,
|
||||
CONFIG_SYS_FSL_PEBUF_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
|
||||
{ CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
|
||||
CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, PMD_SECT_OUTER_SHARE },
|
||||
};
|
||||
|
||||
struct table_info {
|
||||
u64 *ptr;
|
||||
u64 table_base;
|
||||
u64 entry_size;
|
||||
};
|
||||
|
||||
/*
|
||||
* Set the block entries according to the information of the table.
|
||||
*/
|
||||
|
@ -311,6 +165,7 @@ static inline void early_mmu_setup(void)
|
|||
u64 *level1_table1 = (u64 *)(CONFIG_SYS_FSL_OCRAM_BASE + 0x2000);
|
||||
u64 *level2_table0 = (u64 *)(CONFIG_SYS_FSL_OCRAM_BASE + 0x3000);
|
||||
u64 *level2_table1 = (u64 *)(CONFIG_SYS_FSL_OCRAM_BASE + 0x4000);
|
||||
|
||||
struct table_info table = {level0_table, 0, BLOCK_SIZE_L0};
|
||||
|
||||
/* Invalidate all table entries */
|
||||
|
@ -320,19 +175,23 @@ static inline void early_mmu_setup(void)
|
|||
set_pgtable_table(level0_table, 0, level1_table0);
|
||||
set_pgtable_table(level0_table, 1, level1_table1);
|
||||
set_pgtable_table(level1_table0, 0, level2_table0);
|
||||
|
||||
#ifdef CONFIG_FSL_LSCH3
|
||||
set_pgtable_table(level1_table0,
|
||||
CONFIG_SYS_FLASH_BASE >> SECTION_SHIFT_L1,
|
||||
level2_table1);
|
||||
|
||||
#elif defined(CONFIG_FSL_LSCH2)
|
||||
set_pgtable_table(level1_table0, 1, level2_table1);
|
||||
#endif
|
||||
/* Find the table and fill in the block entries */
|
||||
for (i = 0; i < ARRAY_SIZE(lsch3_early_mmu_table); i++) {
|
||||
if (find_table(&lsch3_early_mmu_table[i],
|
||||
for (i = 0; i < ARRAY_SIZE(early_mmu_table); i++) {
|
||||
if (find_table(&early_mmu_table[i],
|
||||
&table, level0_table) == 0) {
|
||||
/*
|
||||
* If find_table() returns error, it cannot be dealt
|
||||
* with here. Breakpoint can be added for debugging.
|
||||
*/
|
||||
set_block_entry(&lsch3_early_mmu_table[i], &table);
|
||||
set_block_entry(&early_mmu_table[i], &table);
|
||||
/*
|
||||
* If set_block_entry() returns error, it cannot be
|
||||
* dealt with here too.
|
||||
|
@ -341,7 +200,9 @@ static inline void early_mmu_setup(void)
|
|||
}
|
||||
|
||||
el = current_el();
|
||||
set_ttbr_tcr_mair(el, (u64)level0_table, LSCH3_TCR, MEMORY_ATTRIBUTES);
|
||||
|
||||
set_ttbr_tcr_mair(el, (u64)level0_table, LAYERSCAPE_TCR,
|
||||
MEMORY_ATTRIBUTES);
|
||||
set_sctlr(get_sctlr() | CR_M);
|
||||
}
|
||||
|
||||
|
@ -353,7 +214,12 @@ static inline void early_mmu_setup(void)
|
|||
* Level 1 table 0 contains 512 entries for each 1GB from 0 to 512GB.
|
||||
* Level 1 table 1 contains 512 entries for each 1GB from 512GB to 1TB.
|
||||
* Level 2 table 0 contains 512 entries for each 2MB from 0 to 1GB.
|
||||
*
|
||||
* For LSCH3:
|
||||
* Level 2 table 1 contains 512 entries for each 2MB from 32GB to 33GB.
|
||||
* For LSCH2:
|
||||
* Level 2 table 1 contains 512 entries for each 2MB from 1GB to 2GB.
|
||||
* Level 2 table 2 contains 512 entries for each 2MB from 20GB to 21GB.
|
||||
*/
|
||||
static inline void final_mmu_setup(void)
|
||||
{
|
||||
|
@ -362,7 +228,12 @@ static inline void final_mmu_setup(void)
|
|||
u64 *level1_table0 = (u64 *)(gd->arch.tlb_addr + 0x1000);
|
||||
u64 *level1_table1 = (u64 *)(gd->arch.tlb_addr + 0x2000);
|
||||
u64 *level2_table0 = (u64 *)(gd->arch.tlb_addr + 0x3000);
|
||||
#ifdef CONFIG_FSL_LSCH3
|
||||
u64 *level2_table1 = (u64 *)(gd->arch.tlb_addr + 0x4000);
|
||||
#elif defined(CONFIG_FSL_LSCH2)
|
||||
u64 *level2_table1 = (u64 *)(gd->arch.tlb_addr + 0x4000);
|
||||
u64 *level2_table2 = (u64 *)(gd->arch.tlb_addr + 0x5000);
|
||||
#endif
|
||||
struct table_info table = {level0_table, 0, BLOCK_SIZE_L0};
|
||||
|
||||
/* Invalidate all table entries */
|
||||
|
@ -372,23 +243,30 @@ static inline void final_mmu_setup(void)
|
|||
set_pgtable_table(level0_table, 0, level1_table0);
|
||||
set_pgtable_table(level0_table, 1, level1_table1);
|
||||
set_pgtable_table(level1_table0, 0, level2_table0);
|
||||
#ifdef CONFIG_FSL_LSCH3
|
||||
set_pgtable_table(level1_table0,
|
||||
CONFIG_SYS_FSL_QBMAN_BASE >> SECTION_SHIFT_L1,
|
||||
level2_table1);
|
||||
#elif defined(CONFIG_FSL_LSCH2)
|
||||
set_pgtable_table(level1_table0, 1, level2_table1);
|
||||
set_pgtable_table(level1_table0,
|
||||
CONFIG_SYS_FSL_QBMAN_BASE >> SECTION_SHIFT_L1,
|
||||
level2_table2);
|
||||
#endif
|
||||
|
||||
/* Find the table and fill in the block entries */
|
||||
for (i = 0; i < ARRAY_SIZE(lsch3_final_mmu_table); i++) {
|
||||
if (find_table(&lsch3_final_mmu_table[i],
|
||||
for (i = 0; i < ARRAY_SIZE(final_mmu_table); i++) {
|
||||
if (find_table(&final_mmu_table[i],
|
||||
&table, level0_table) == 0) {
|
||||
if (set_block_entry(&lsch3_final_mmu_table[i],
|
||||
if (set_block_entry(&final_mmu_table[i],
|
||||
&table) != 0) {
|
||||
printf("MMU error: could not set block entry for %p\n",
|
||||
&lsch3_final_mmu_table[i]);
|
||||
&final_mmu_table[i]);
|
||||
}
|
||||
|
||||
} else {
|
||||
printf("MMU error: could not find the table for %p\n",
|
||||
&lsch3_final_mmu_table[i]);
|
||||
&final_mmu_table[i]);
|
||||
}
|
||||
}
|
||||
|
||||
|
@ -396,9 +274,13 @@ static inline void final_mmu_setup(void)
|
|||
flush_dcache_range(gd->arch.tlb_addr,
|
||||
gd->arch.tlb_addr + gd->arch.tlb_size);
|
||||
|
||||
#ifdef CONFIG_SYS_DPAA_FMAN
|
||||
flush_dcache_all();
|
||||
#endif
|
||||
/* point TTBR to the new table */
|
||||
el = current_el();
|
||||
set_ttbr_tcr_mair(el, (u64)level0_table, LSCH3_TCR_FINAL,
|
||||
|
||||
set_ttbr_tcr_mair(el, (u64)level0_table, LAYERSCAPE_TCR_FINAL,
|
||||
MEMORY_ATTRIBUTES);
|
||||
/*
|
||||
* MMU is already enabled, just need to invalidate TLB to load the
|
||||
|
@ -434,8 +316,9 @@ static inline u32 initiator_type(u32 cluster, int init_id)
|
|||
{
|
||||
struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
|
||||
u32 idx = (cluster >> (init_id * 8)) & TP_CLUSTER_INIT_MASK;
|
||||
u32 type = in_le32(&gur->tp_ityp[idx]);
|
||||
u32 type = 0;
|
||||
|
||||
type = gur_in32(&gur->tp_ityp[idx]);
|
||||
if (type & TP_ITYP_AV)
|
||||
return type;
|
||||
|
||||
|
@ -450,7 +333,8 @@ u32 cpu_mask(void)
|
|||
|
||||
do {
|
||||
int j;
|
||||
cluster = in_le32(&gur->tp_cluster[i].lower);
|
||||
|
||||
cluster = gur_in32(&gur->tp_cluster[i].lower);
|
||||
for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
|
||||
type = initiator_type(cluster, j);
|
||||
if (type) {
|
||||
|
@ -460,7 +344,7 @@ u32 cpu_mask(void)
|
|||
}
|
||||
}
|
||||
i++;
|
||||
} while ((cluster & TP_CLUSTER_EOC) != TP_CLUSTER_EOC);
|
||||
} while ((cluster & TP_CLUSTER_EOC) == 0x0);
|
||||
|
||||
return mask;
|
||||
}
|
||||
|
@ -482,7 +366,8 @@ int fsl_qoriq_core_to_cluster(unsigned int core)
|
|||
|
||||
do {
|
||||
int j;
|
||||
cluster = in_le32(&gur->tp_cluster[i].lower);
|
||||
|
||||
cluster = gur_in32(&gur->tp_cluster[i].lower);
|
||||
for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
|
||||
if (initiator_type(cluster, j)) {
|
||||
if (count == core)
|
||||
|
@ -491,7 +376,7 @@ int fsl_qoriq_core_to_cluster(unsigned int core)
|
|||
}
|
||||
}
|
||||
i++;
|
||||
} while ((cluster & TP_CLUSTER_EOC) != TP_CLUSTER_EOC);
|
||||
} while ((cluster & TP_CLUSTER_EOC) == 0x0);
|
||||
|
||||
return -1; /* cannot identify the cluster */
|
||||
}
|
||||
|
@ -505,7 +390,8 @@ u32 fsl_qoriq_core_to_type(unsigned int core)
|
|||
|
||||
do {
|
||||
int j;
|
||||
cluster = in_le32(&gur->tp_cluster[i].lower);
|
||||
|
||||
cluster = gur_in32(&gur->tp_cluster[i].lower);
|
||||
for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
|
||||
type = initiator_type(cluster, j);
|
||||
if (type) {
|
||||
|
@ -515,7 +401,7 @@ u32 fsl_qoriq_core_to_type(unsigned int core)
|
|||
}
|
||||
}
|
||||
i++;
|
||||
} while ((cluster & TP_CLUSTER_EOC) != TP_CLUSTER_EOC);
|
||||
} while ((cluster & TP_CLUSTER_EOC) == 0x0);
|
||||
|
||||
return -1; /* cannot identify the cluster */
|
||||
}
|
||||
|
@ -527,15 +413,13 @@ int print_cpuinfo(void)
|
|||
struct sys_info sysinfo;
|
||||
char buf[32];
|
||||
unsigned int i, core;
|
||||
u32 type;
|
||||
u32 type, rcw;
|
||||
|
||||
puts("SoC: ");
|
||||
|
||||
cpu_name(buf);
|
||||
printf(" %s (0x%x)\n", buf, in_le32(&gur->svr));
|
||||
|
||||
printf(" %s (0x%x)\n", buf, gur_in32(&gur->svr));
|
||||
memset((u8 *)buf, 0x00, ARRAY_SIZE(buf));
|
||||
|
||||
get_sys_info(&sysinfo);
|
||||
puts("Clock Configuration:");
|
||||
for_each_cpu(i, core, cpu_numcores(), cpu_mask()) {
|
||||
|
@ -551,18 +435,23 @@ int print_cpuinfo(void)
|
|||
printf("\n Bus: %-4s MHz ",
|
||||
strmhz(buf, sysinfo.freq_systembus));
|
||||
printf("DDR: %-4s MT/s", strmhz(buf, sysinfo.freq_ddrbus));
|
||||
#ifdef CONFIG_SYS_DPAA_FMAN
|
||||
printf(" FMAN: %-4s MHz", strmhz(buf, sysinfo.freq_fman[0]));
|
||||
#endif
|
||||
#ifdef CONFIG_FSL_LSCH3
|
||||
printf(" DP-DDR: %-4s MT/s", strmhz(buf, sysinfo.freq_ddrbus2));
|
||||
#endif
|
||||
puts("\n");
|
||||
|
||||
/* Display the RCW, so that no one gets confused as to what RCW
|
||||
/*
|
||||
* Display the RCW, so that no one gets confused as to what RCW
|
||||
* we're actually using for this boot.
|
||||
*/
|
||||
puts("Reset Configuration Word (RCW):");
|
||||
for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) {
|
||||
u32 rcw = in_le32(&gur->rcwsr[i]);
|
||||
|
||||
rcw = gur_in32(&gur->rcwsr[i]);
|
||||
if ((i % 4) == 0)
|
||||
printf("\n %02x:", i * 4);
|
||||
printf("\n %08x:", i * 4);
|
||||
printf(" %08x", rcw);
|
||||
}
|
||||
puts("\n");
|
||||
|
@ -584,20 +473,28 @@ int cpu_eth_init(bd_t *bis)
|
|||
|
||||
#ifdef CONFIG_FSL_MC_ENET
|
||||
error = fsl_mc_ldpaa_init(bis);
|
||||
#endif
|
||||
#ifdef CONFIG_FMAN_ENET
|
||||
fm_standard_init(bis);
|
||||
#endif
|
||||
return error;
|
||||
}
|
||||
|
||||
int arch_early_init_r(void)
|
||||
{
|
||||
int rv;
|
||||
rv = fsl_lsch3_wake_seconday_cores();
|
||||
#ifdef CONFIG_MP
|
||||
int rv = 1;
|
||||
|
||||
rv = fsl_layerscape_wake_seconday_cores();
|
||||
if (rv)
|
||||
printf("Did not wake secondary cores\n");
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SYS_HAS_SERDES
|
||||
fsl_serdes_init();
|
||||
#endif
|
||||
#ifdef CONFIG_FMAN_ENET
|
||||
fman_enet_init();
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
|
@ -605,7 +502,9 @@ int arch_early_init_r(void)
|
|||
int timer_init(void)
|
||||
{
|
||||
u32 __iomem *cntcr = (u32 *)CONFIG_SYS_FSL_TIMER_ADDR;
|
||||
#ifdef CONFIG_FSL_LSCH3
|
||||
u32 __iomem *cltbenr = (u32 *)CONFIG_SYS_FSL_PMU_CLTBENR;
|
||||
#endif
|
||||
#ifdef COUNTER_FREQUENCY_REAL
|
||||
unsigned long cntfrq = COUNTER_FREQUENCY_REAL;
|
||||
|
||||
|
@ -613,10 +512,12 @@ int timer_init(void)
|
|||
asm volatile("msr cntfrq_el0, %0" : : "r" (cntfrq) : "memory");
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_FSL_LSCH3
|
||||
/* Enable timebase for all clusters.
|
||||
* It is safe to do so even some clusters are not enabled.
|
||||
*/
|
||||
out_le32(cltbenr, 0xf);
|
||||
#endif
|
||||
|
||||
/* Enable clock for timer
|
||||
* This is a global setting.
|
||||
|
@ -632,7 +533,7 @@ void reset_cpu(ulong addr)
|
|||
u32 val;
|
||||
|
||||
/* Raise RESET_REQ_B */
|
||||
val = in_le32(rstcr);
|
||||
val = scfg_in32(rstcr);
|
||||
val |= 0x02;
|
||||
out_le32(rstcr, val);
|
||||
scfg_out32(rstcr, val);
|
||||
}
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright 2014, Freescale Semiconductor
|
||||
* Copyright 2014-2015, Freescale Semiconductor
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright 2014 Freescale Semiconductor, Inc.
|
||||
* Copyright 2014-2015 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
@ -7,11 +7,22 @@
|
|||
#include <common.h>
|
||||
#include <libfdt.h>
|
||||
#include <fdt_support.h>
|
||||
#include <asm/arch-fsl-lsch3/fdt.h>
|
||||
#include <phy.h>
|
||||
#ifdef CONFIG_FSL_LSCH3
|
||||
#include <asm/arch/fdt.h>
|
||||
#endif
|
||||
#ifdef CONFIG_FSL_ESDHC
|
||||
#include <fsl_esdhc.h>
|
||||
#endif
|
||||
#include "mp.h"
|
||||
#ifdef CONFIG_MP
|
||||
#include <asm/arch/mp.h>
|
||||
#endif
|
||||
|
||||
int fdt_fixup_phy_connection(void *blob, int offset, phy_interface_t phyc)
|
||||
{
|
||||
return fdt_setprop_string(blob, offset, "phy-connection-type",
|
||||
phy_string_for_interface(phyc));
|
||||
}
|
||||
|
||||
#ifdef CONFIG_MP
|
||||
void ft_fixup_cpu(void *blob)
|
||||
|
@ -33,8 +44,8 @@ void ft_fixup_cpu(void *blob)
|
|||
off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
|
||||
while (off != -FDT_ERR_NOTFOUND) {
|
||||
reg = (fdt32_t *)fdt_getprop(blob, off, "reg", 0);
|
||||
core_id = of_read_number(reg, addr_cells);
|
||||
if (reg) {
|
||||
core_id = of_read_number(reg, addr_cells);
|
||||
if (core_id == 0 || (is_core_online(core_id))) {
|
||||
val = spin_tbl_addr;
|
||||
val += id_to_core(core_id) *
|
||||
|
@ -150,6 +161,7 @@ void append_mmu_masters(void *blob, const char *smmu_path,
|
|||
* for all DPAA2 devices.
|
||||
*
|
||||
*/
|
||||
#ifdef CONFIG_FSL_LSCH3
|
||||
static void fdt_fixup_smmu(void *blob)
|
||||
{
|
||||
int nodeoffset;
|
||||
|
@ -165,6 +177,7 @@ static void fdt_fixup_smmu(void *blob)
|
|||
fdt_fixup_smmu_pcie(blob);
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
|
||||
void ft_cpu_setup(void *blob, bd_t *bd)
|
||||
{
|
||||
|
@ -181,9 +194,11 @@ void ft_cpu_setup(void *blob, bd_t *bd)
|
|||
ft_pci_setup(blob, bd);
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_FSL_ESDHC)
|
||||
#ifdef CONFIG_FSL_ESDHC
|
||||
fdt_fixup_esdhc(blob, bd);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_FSL_LSCH3
|
||||
fdt_fixup_smmu(blob);
|
||||
#endif
|
||||
}
|
117
arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c
Normal file
117
arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c
Normal file
|
@ -0,0 +1,117 @@
|
|||
/*
|
||||
* Copyright 2015 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/errno.h>
|
||||
#include <asm/arch/fsl_serdes.h>
|
||||
#include <asm/arch/soc.h>
|
||||
|
||||
#ifdef CONFIG_SYS_FSL_SRDS_1
|
||||
static u8 serdes1_prtcl_map[SERDES_PRCTL_COUNT];
|
||||
#endif
|
||||
|
||||
int is_serdes_configured(enum srds_prtcl device)
|
||||
{
|
||||
int ret = 0;
|
||||
|
||||
#ifdef CONFIG_SYS_FSL_SRDS_1
|
||||
ret |= serdes1_prtcl_map[device];
|
||||
#endif
|
||||
|
||||
return !!ret;
|
||||
}
|
||||
|
||||
int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
|
||||
{
|
||||
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
|
||||
u32 cfg = gur_in32(&gur->rcwsr[4]);
|
||||
int i;
|
||||
|
||||
switch (sd) {
|
||||
#ifdef CONFIG_SYS_FSL_SRDS_1
|
||||
case FSL_SRDS_1:
|
||||
cfg &= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
|
||||
cfg >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
|
||||
break;
|
||||
#endif
|
||||
default:
|
||||
printf("invalid SerDes%d\n", sd);
|
||||
break;
|
||||
}
|
||||
|
||||
/* Is serdes enabled at all? */
|
||||
if (unlikely(cfg == 0))
|
||||
return -ENODEV;
|
||||
|
||||
for (i = 0; i < SRDS_MAX_LANES; i++) {
|
||||
if (serdes_get_prtcl(sd, cfg, i) == device)
|
||||
return i;
|
||||
}
|
||||
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
int get_serdes_protocol(void)
|
||||
{
|
||||
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
|
||||
u32 cfg = gur_in32(&gur->rcwsr[4]) &
|
||||
FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
|
||||
cfg >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
|
||||
|
||||
return cfg;
|
||||
}
|
||||
|
||||
const char *serdes_clock_to_string(u32 clock)
|
||||
{
|
||||
switch (clock) {
|
||||
case SRDS_PLLCR0_RFCK_SEL_100:
|
||||
return "100";
|
||||
case SRDS_PLLCR0_RFCK_SEL_125:
|
||||
return "125";
|
||||
case SRDS_PLLCR0_RFCK_SEL_156_25:
|
||||
return "156.25";
|
||||
default:
|
||||
return "100";
|
||||
}
|
||||
}
|
||||
|
||||
void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift,
|
||||
u8 serdes_prtcl_map[SERDES_PRCTL_COUNT])
|
||||
{
|
||||
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
|
||||
u32 cfg;
|
||||
int lane;
|
||||
|
||||
memset(serdes_prtcl_map, 0, sizeof(serdes_prtcl_map));
|
||||
|
||||
cfg = gur_in32(&gur->rcwsr[4]) & sd_prctl_mask;
|
||||
cfg >>= sd_prctl_shift;
|
||||
printf("Using SERDES%d Protocol: %d (0x%x)\n", sd + 1, cfg, cfg);
|
||||
|
||||
if (!is_serdes_prtcl_valid(sd, cfg))
|
||||
printf("SERDES%d[PRTCL] = 0x%x is not valid\n", sd + 1, cfg);
|
||||
|
||||
for (lane = 0; lane < SRDS_MAX_LANES; lane++) {
|
||||
enum srds_prtcl lane_prtcl = serdes_get_prtcl(sd, cfg, lane);
|
||||
|
||||
if (unlikely(lane_prtcl >= SERDES_PRCTL_COUNT))
|
||||
debug("Unknown SerDes lane protocol %d\n", lane_prtcl);
|
||||
else
|
||||
serdes_prtcl_map[lane_prtcl] = 1;
|
||||
}
|
||||
}
|
||||
|
||||
void fsl_serdes_init(void)
|
||||
{
|
||||
#ifdef CONFIG_SYS_FSL_SRDS_1
|
||||
serdes_init(FSL_SRDS_1,
|
||||
CONFIG_SYS_FSL_SERDES_ADDR,
|
||||
FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK,
|
||||
FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT,
|
||||
serdes1_prtcl_map);
|
||||
#endif
|
||||
}
|
180
arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
Normal file
180
arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
Normal file
|
@ -0,0 +1,180 @@
|
|||
/*
|
||||
* Copyright 2015 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <linux/compiler.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/processor.h>
|
||||
#include <asm/arch/clock.h>
|
||||
#include <asm/arch/soc.h>
|
||||
#include <fsl_ifc.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#ifndef CONFIG_SYS_FSL_NUM_CC_PLLS
|
||||
#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
|
||||
#endif
|
||||
|
||||
void get_sys_info(struct sys_info *sys_info)
|
||||
{
|
||||
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
|
||||
#ifdef CONFIG_FSL_IFC
|
||||
struct fsl_ifc ifc_regs = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
|
||||
u32 ccr;
|
||||
#endif
|
||||
#if defined(CONFIG_FSL_ESDHC) || defined(CONFIG_SYS_DPAA_FMAN)
|
||||
u32 rcw_tmp;
|
||||
#endif
|
||||
struct ccsr_clk *clk = (void *)(CONFIG_SYS_FSL_CLK_ADDR);
|
||||
unsigned int cpu;
|
||||
const u8 core_cplx_pll[8] = {
|
||||
[0] = 0, /* CC1 PPL / 1 */
|
||||
[1] = 0, /* CC1 PPL / 2 */
|
||||
[4] = 1, /* CC2 PPL / 1 */
|
||||
[5] = 1, /* CC2 PPL / 2 */
|
||||
};
|
||||
|
||||
const u8 core_cplx_pll_div[8] = {
|
||||
[0] = 1, /* CC1 PPL / 1 */
|
||||
[1] = 2, /* CC1 PPL / 2 */
|
||||
[4] = 1, /* CC2 PPL / 1 */
|
||||
[5] = 2, /* CC2 PPL / 2 */
|
||||
};
|
||||
|
||||
uint i;
|
||||
uint freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS];
|
||||
uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS];
|
||||
unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
|
||||
|
||||
sys_info->freq_systembus = sysclk;
|
||||
#ifdef CONFIG_DDR_CLK_FREQ
|
||||
sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ;
|
||||
#else
|
||||
sys_info->freq_ddrbus = sysclk;
|
||||
#endif
|
||||
|
||||
sys_info->freq_systembus *= (gur_in32(&gur->rcwsr[0]) >>
|
||||
FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT) &
|
||||
FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK;
|
||||
sys_info->freq_ddrbus *= (gur_in32(&gur->rcwsr[0]) >>
|
||||
FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_SHIFT) &
|
||||
FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK;
|
||||
|
||||
for (i = 0; i < CONFIG_SYS_FSL_NUM_CC_PLLS; i++) {
|
||||
ratio[i] = (in_be32(&clk->pllcgsr[i].pllcngsr) >> 1) & 0xff;
|
||||
if (ratio[i] > 4)
|
||||
freq_c_pll[i] = sysclk * ratio[i];
|
||||
else
|
||||
freq_c_pll[i] = sys_info->freq_systembus * ratio[i];
|
||||
}
|
||||
|
||||
for (cpu = 0; cpu < CONFIG_MAX_CPUS; cpu++) {
|
||||
u32 c_pll_sel = (in_be32(&clk->clkcsr[cpu].clkcncsr) >> 27)
|
||||
& 0xf;
|
||||
u32 cplx_pll = core_cplx_pll[c_pll_sel];
|
||||
|
||||
sys_info->freq_processor[cpu] =
|
||||
freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
|
||||
}
|
||||
|
||||
#define HWA_CGA_M1_CLK_SEL 0xe0000000
|
||||
#define HWA_CGA_M1_CLK_SHIFT 29
|
||||
#ifdef CONFIG_SYS_DPAA_FMAN
|
||||
rcw_tmp = in_be32(&gur->rcwsr[7]);
|
||||
switch ((rcw_tmp & HWA_CGA_M1_CLK_SEL) >> HWA_CGA_M1_CLK_SHIFT) {
|
||||
case 2:
|
||||
sys_info->freq_fman[0] = freq_c_pll[0] / 2;
|
||||
break;
|
||||
case 3:
|
||||
sys_info->freq_fman[0] = freq_c_pll[0] / 3;
|
||||
break;
|
||||
case 6:
|
||||
sys_info->freq_fman[0] = freq_c_pll[1] / 2;
|
||||
break;
|
||||
case 7:
|
||||
sys_info->freq_fman[0] = freq_c_pll[1] / 3;
|
||||
break;
|
||||
default:
|
||||
printf("Error: Unknown FMan1 clock select!\n");
|
||||
break;
|
||||
}
|
||||
#endif
|
||||
|
||||
#define HWA_CGA_M2_CLK_SEL 0x00000007
|
||||
#define HWA_CGA_M2_CLK_SHIFT 0
|
||||
#ifdef CONFIG_FSL_ESDHC
|
||||
rcw_tmp = in_be32(&gur->rcwsr[15]);
|
||||
rcw_tmp = (rcw_tmp & HWA_CGA_M2_CLK_SEL) >> HWA_CGA_M2_CLK_SHIFT;
|
||||
sys_info->freq_sdhc = freq_c_pll[1] / rcw_tmp;
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_FSL_IFC)
|
||||
ccr = ifc_in32(&ifc_regs.gregs->ifc_ccr);
|
||||
ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT) + 1;
|
||||
|
||||
sys_info->freq_localbus = sys_info->freq_systembus / ccr;
|
||||
#endif
|
||||
}
|
||||
|
||||
int get_clocks(void)
|
||||
{
|
||||
struct sys_info sys_info;
|
||||
|
||||
get_sys_info(&sys_info);
|
||||
gd->cpu_clk = sys_info.freq_processor[0];
|
||||
gd->bus_clk = sys_info.freq_systembus;
|
||||
gd->mem_clk = sys_info.freq_ddrbus;
|
||||
|
||||
#ifdef CONFIG_FSL_ESDHC
|
||||
gd->arch.sdhc_clk = sys_info.freq_sdhc;
|
||||
#endif
|
||||
|
||||
if (gd->cpu_clk != 0)
|
||||
return 0;
|
||||
else
|
||||
return 1;
|
||||
}
|
||||
|
||||
ulong get_bus_freq(ulong dummy)
|
||||
{
|
||||
return gd->bus_clk;
|
||||
}
|
||||
|
||||
ulong get_ddr_freq(ulong dummy)
|
||||
{
|
||||
return gd->mem_clk;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_FSL_ESDHC
|
||||
int get_sdhc_freq(ulong dummy)
|
||||
{
|
||||
return gd->arch.sdhc_clk;
|
||||
}
|
||||
#endif
|
||||
|
||||
int get_serial_clock(void)
|
||||
{
|
||||
return gd->bus_clk;
|
||||
}
|
||||
|
||||
unsigned int mxc_get_clock(enum mxc_clock clk)
|
||||
{
|
||||
switch (clk) {
|
||||
case MXC_I2C_CLK:
|
||||
return get_bus_freq(0);
|
||||
#if defined(CONFIG_FSL_ESDHC)
|
||||
case MXC_ESDHC_CLK:
|
||||
return get_sdhc_freq(0);
|
||||
#endif
|
||||
case MXC_DSPI_CLK:
|
||||
return get_bus_freq(0);
|
||||
case MXC_UART_CLK:
|
||||
return get_bus_freq(0);
|
||||
default:
|
||||
printf("Unsupported clock\n");
|
||||
}
|
||||
return 0;
|
||||
}
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright 2015 Freescale Semiconductor, Inc.
|
||||
* Copyright 2014-2015 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
@ -8,7 +8,7 @@
|
|||
#include <asm/io.h>
|
||||
#include <asm/errno.h>
|
||||
#include <asm/arch/fsl_serdes.h>
|
||||
#include <asm/arch-fsl-lsch3/immap_lsch3.h>
|
||||
#include <asm/arch/soc.h>
|
||||
#include <fsl-mc/ldpaa_wriop.h>
|
||||
|
||||
#ifdef CONFIG_SYS_FSL_SRDS_1
|
||||
|
@ -35,7 +35,7 @@ int is_serdes_configured(enum srds_prtcl device)
|
|||
int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
|
||||
{
|
||||
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
|
||||
u32 cfg = in_le32(&gur->rcwsr[28]);
|
||||
u32 cfg = gur_in32(&gur->rcwsr[28]);
|
||||
int i;
|
||||
|
||||
switch (sd) {
|
||||
|
@ -76,7 +76,7 @@ void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift,
|
|||
|
||||
memset(serdes_prtcl_map, 0, sizeof(serdes_prtcl_map));
|
||||
|
||||
cfg = in_le32(&gur->rcwsr[28]) & sd_prctl_mask;
|
||||
cfg = gur_in32(&gur->rcwsr[28]) & sd_prctl_mask;
|
||||
cfg >>= sd_prctl_shift;
|
||||
printf("Using SERDES%d Protocol: %d (0x%x)\n", sd + 1, cfg, cfg);
|
||||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright 2014, Freescale Semiconductor, Inc.
|
||||
* Copyright 2014-2015, Freescale Semiconductor, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*
|
||||
|
@ -11,8 +11,8 @@
|
|||
#include <fsl_ifc.h>
|
||||
#include <asm/processor.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch-fsl-lsch3/immap_lsch3.h>
|
||||
#include <asm/arch/clock.h>
|
||||
#include <asm/arch/soc.h>
|
||||
#include "cpu.h"
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
@ -83,15 +83,15 @@ void get_sys_info(struct sys_info *sys_info)
|
|||
sys_info->freq_ddrbus2 = sysclk;
|
||||
#endif
|
||||
|
||||
sys_info->freq_systembus *= (in_le32(&gur->rcwsr[0]) >>
|
||||
sys_info->freq_systembus *= (gur_in32(&gur->rcwsr[0]) >>
|
||||
FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_SHIFT) &
|
||||
FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_MASK;
|
||||
/* Platform clock is half of platform PLL */
|
||||
sys_info->freq_systembus /= 2;
|
||||
sys_info->freq_ddrbus *= (in_le32(&gur->rcwsr[0]) >>
|
||||
sys_info->freq_ddrbus *= (gur_in32(&gur->rcwsr[0]) >>
|
||||
FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_SHIFT) &
|
||||
FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK;
|
||||
sys_info->freq_ddrbus2 *= (in_le32(&gur->rcwsr[0]) >>
|
||||
sys_info->freq_ddrbus2 *= (gur_in32(&gur->rcwsr[0]) >>
|
||||
FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_SHIFT) &
|
||||
FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_MASK;
|
||||
|
||||
|
@ -118,7 +118,7 @@ void get_sys_info(struct sys_info *sys_info)
|
|||
}
|
||||
|
||||
#if defined(CONFIG_FSL_IFC)
|
||||
ccr = in_le32(&ifc_regs.gregs->ifc_ccr);
|
||||
ccr = ifc_in32(&ifc_regs.gregs->ifc_ccr);
|
||||
ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT) + 1;
|
||||
|
||||
sys_info->freq_localbus = sys_info->freq_systembus / ccr;
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* (C) Copyright 2014 Freescale Semiconductor
|
||||
* (C) Copyright 2014-2015 Freescale Semiconductor
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*
|
||||
|
@ -10,11 +10,14 @@
|
|||
#include <linux/linkage.h>
|
||||
#include <asm/gic.h>
|
||||
#include <asm/macro.h>
|
||||
#include "mp.h"
|
||||
#ifdef CONFIG_MP
|
||||
#include <asm/arch/mp.h>
|
||||
#endif
|
||||
|
||||
ENTRY(lowlevel_init)
|
||||
mov x29, lr /* Save LR */
|
||||
|
||||
#ifdef CONFIG_FSL_LSCH3
|
||||
/* Add fully-coherent masters to DVM domain */
|
||||
ldr x0, =CCI_MN_BASE
|
||||
ldr x1, =CCI_MN_RNF_NODEID_LIST
|
||||
|
@ -81,6 +84,7 @@ ENTRY(lowlevel_init)
|
|||
ldr x0, =CCI_S2_QOS_CONTROL_BASE(20)
|
||||
ldr x1, =0x00FF000C
|
||||
bl ccn504_set_qos
|
||||
#endif
|
||||
|
||||
/* Set the SMMU page size in the sACR register */
|
||||
ldr x1, =SMMU_BASE
|
||||
|
@ -106,10 +110,12 @@ ENTRY(lowlevel_init)
|
|||
|
||||
branch_if_master x0, x1, 2f
|
||||
|
||||
#if defined(CONFIG_MP) && defined(CONFIG_ARMV8_MULTIENTRY)
|
||||
ldr x0, =secondary_boot_func
|
||||
blr x0
|
||||
2:
|
||||
#endif
|
||||
|
||||
2:
|
||||
#ifdef CONFIG_FSL_TZPC_BP147
|
||||
/* Set Non Secure access for all devices protected via TZPC */
|
||||
ldr x1, =TZPCDECPROT_0_SET_BASE /* Decode Protection-0 Set Reg */
|
||||
|
@ -245,6 +251,7 @@ ENTRY(__asm_flush_l3_cache)
|
|||
ret
|
||||
ENDPROC(__asm_flush_l3_cache)
|
||||
|
||||
#ifdef CONFIG_MP
|
||||
/* Keep literals not used by the secondary boot code outside it */
|
||||
.ltorg
|
||||
|
||||
|
@ -353,3 +360,4 @@ __real_cntfrq:
|
|||
/* Secondary Boot Code ends here */
|
||||
__secondary_boot_code_size:
|
||||
.quad .-secondary_boot_code
|
||||
#endif
|
86
arch/arm/cpu/armv8/fsl-layerscape/ls1043a_serdes.c
Normal file
86
arch/arm/cpu/armv8/fsl-layerscape/ls1043a_serdes.c
Normal file
|
@ -0,0 +1,86 @@
|
|||
/*
|
||||
* Copyright 2015 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/arch/fsl_serdes.h>
|
||||
#include <asm/arch/immap_lsch2.h>
|
||||
|
||||
struct serdes_config {
|
||||
u32 protocol;
|
||||
u8 lanes[SRDS_MAX_LANES];
|
||||
};
|
||||
|
||||
static struct serdes_config serdes1_cfg_tbl[] = {
|
||||
/* SerDes 1 */
|
||||
{0x1555, {XFI_FM1_MAC9, PCIE1, PCIE2, PCIE3} },
|
||||
{0x2555, {SGMII_2500_FM1_DTSEC9, PCIE1, PCIE2, PCIE3} },
|
||||
{0x4555, {QSGMII_FM1_A, PCIE1, PCIE2, PCIE3} },
|
||||
{0x4558, {QSGMII_FM1_A, PCIE1, PCIE2, SATA1} },
|
||||
{0x1355, {XFI_FM1_MAC9, SGMII_FM1_DTSEC2, PCIE2, PCIE3} },
|
||||
{0x2355, {SGMII_2500_FM1_DTSEC9, SGMII_FM1_DTSEC2, PCIE2, PCIE3} },
|
||||
{0x3335, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC5,
|
||||
PCIE3} },
|
||||
{0x3355, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC2, PCIE2, PCIE3} },
|
||||
{0x3358, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC2, PCIE2, SATA1} },
|
||||
{0x3555, {SGMII_FM1_DTSEC9, PCIE1, PCIE2, PCIE3} },
|
||||
{0x3558, {SGMII_FM1_DTSEC9, PCIE1, PCIE2, SATA1} },
|
||||
{0x7000, {PCIE1, PCIE1, PCIE1, PCIE1} },
|
||||
{0x9998, {PCIE1, PCIE2, PCIE3, SATA1} },
|
||||
{0x6058, {PCIE1, PCIE1, PCIE2, SATA1} },
|
||||
{0x1455, {XFI_FM1_MAC9, QSGMII_FM1_A, PCIE2, PCIE3} },
|
||||
{0x2455, {SGMII_2500_FM1_DTSEC9, QSGMII_FM1_A, PCIE2, PCIE3} },
|
||||
{0x2255, {SGMII_2500_FM1_DTSEC9, SGMII_2500_FM1_DTSEC2, PCIE2, PCIE3} },
|
||||
{0x3333, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC5,
|
||||
SGMII_FM1_DTSEC6} },
|
||||
{}
|
||||
};
|
||||
|
||||
static struct serdes_config *serdes_cfg_tbl[] = {
|
||||
serdes1_cfg_tbl,
|
||||
};
|
||||
|
||||
enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane)
|
||||
{
|
||||
struct serdes_config *ptr;
|
||||
|
||||
if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
|
||||
return 0;
|
||||
|
||||
ptr = serdes_cfg_tbl[serdes];
|
||||
while (ptr->protocol) {
|
||||
if (ptr->protocol == cfg)
|
||||
return ptr->lanes[lane];
|
||||
ptr++;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int is_serdes_prtcl_valid(int serdes, u32 prtcl)
|
||||
{
|
||||
int i;
|
||||
struct serdes_config *ptr;
|
||||
|
||||
if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
|
||||
return 0;
|
||||
|
||||
ptr = serdes_cfg_tbl[serdes];
|
||||
while (ptr->protocol) {
|
||||
if (ptr->protocol == prtcl)
|
||||
break;
|
||||
ptr++;
|
||||
}
|
||||
|
||||
if (!ptr->protocol)
|
||||
return 0;
|
||||
|
||||
for (i = 0; i < SRDS_MAX_LANES; i++) {
|
||||
if (ptr->lanes[i] != NONE)
|
||||
return 1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
|
@ -1,12 +1,11 @@
|
|||
/*
|
||||
* Copyright 2015 Freescale Semiconductor, Inc.
|
||||
* Copyright 2014-2015 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/arch/fsl_serdes.h>
|
||||
#include <asm/arch-fsl-lsch3/immap_lsch3.h>
|
||||
|
||||
struct serdes_config {
|
||||
u8 protocol;
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright 2014 Freescale Semiconductor, Inc.
|
||||
* Copyright 2014-2015 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
@ -7,9 +7,8 @@
|
|||
#include <common.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/system.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch-fsl-lsch3/immap_lsch3.h>
|
||||
#include "mp.h"
|
||||
#include <asm/arch/mp.h>
|
||||
#include <asm/arch/soc.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
|
@ -23,10 +22,14 @@ phys_addr_t determine_mp_bootpg(void)
|
|||
return (phys_addr_t)&secondary_boot_code;
|
||||
}
|
||||
|
||||
int fsl_lsch3_wake_seconday_cores(void)
|
||||
int fsl_layerscape_wake_seconday_cores(void)
|
||||
{
|
||||
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
|
||||
#ifdef CONFIG_FSL_LSCH3
|
||||
struct ccsr_reset __iomem *rst = (void *)(CONFIG_SYS_FSL_RST_ADDR);
|
||||
#elif defined(CONFIG_FSL_LSCH2)
|
||||
struct ccsr_scfg __iomem *scfg = (void *)(CONFIG_SYS_FSL_SCFG_ADDR);
|
||||
#endif
|
||||
u32 cores, cpu_up_mask = 1;
|
||||
int i, timeout = 10;
|
||||
u64 *table = get_spin_tbl_addr();
|
||||
|
@ -48,13 +51,24 @@ int fsl_lsch3_wake_seconday_cores(void)
|
|||
(CONFIG_MAX_CPUS*SPIN_TABLE_ELEM_SIZE));
|
||||
|
||||
printf("Waking secondary cores to start from %lx\n", gd->relocaddr);
|
||||
out_le32(&gur->bootlocptrh, (u32)(gd->relocaddr >> 32));
|
||||
out_le32(&gur->bootlocptrl, (u32)gd->relocaddr);
|
||||
out_le32(&gur->scratchrw[6], 1);
|
||||
|
||||
#ifdef CONFIG_FSL_LSCH3
|
||||
gur_out32(&gur->bootlocptrh, (u32)(gd->relocaddr >> 32));
|
||||
gur_out32(&gur->bootlocptrl, (u32)gd->relocaddr);
|
||||
gur_out32(&gur->scratchrw[6], 1);
|
||||
asm volatile("dsb st" : : : "memory");
|
||||
rst->brrl = cores;
|
||||
asm volatile("dsb st" : : : "memory");
|
||||
#elif defined(CONFIG_FSL_LSCH2)
|
||||
scfg_out32(&scfg->scratchrw[0], (u32)(gd->relocaddr >> 32));
|
||||
scfg_out32(&scfg->scratchrw[1], (u32)gd->relocaddr);
|
||||
asm volatile("dsb st" : : : "memory");
|
||||
gur_out32(&gur->brrl, cores);
|
||||
asm volatile("dsb st" : : : "memory");
|
||||
|
||||
/* Bootup online cores */
|
||||
scfg_out32(&scfg->corebcr, cores);
|
||||
#endif
|
||||
/* This is needed as a precautionary measure.
|
||||
* If some code before this has accidentally released the secondary
|
||||
* cores then the pre-bootloader code will trap them in a "wfe" unless
|
|
@ -1,19 +1,18 @@
|
|||
/*
|
||||
* Copyright 2015 Freescale Semiconductor
|
||||
* Copyright 2014-2015 Freescale Semiconductor
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <fsl_ifc.h>
|
||||
#include <nand.h>
|
||||
#include <spl.h>
|
||||
#include <asm/arch-fsl-lsch3/soc.h>
|
||||
#include <asm/arch/soc.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/global_data.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#ifdef CONFIG_LS2085A
|
||||
static void erratum_a008751(void)
|
||||
{
|
||||
#ifdef CONFIG_SYS_FSL_ERRATUM_A008751
|
||||
|
@ -78,30 +77,27 @@ void fsl_lsch3_early_init_f(void)
|
|||
erratum_a009203();
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SPL_BUILD
|
||||
void board_init_f(ulong dummy)
|
||||
#elif defined(CONFIG_LS1043A)
|
||||
void fsl_lsch2_early_init_f(void)
|
||||
{
|
||||
/* Clear global data */
|
||||
memset((void *)gd, 0, sizeof(gd_t));
|
||||
struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
|
||||
|
||||
arch_cpu_init();
|
||||
board_early_init_f();
|
||||
timer_init();
|
||||
env_init();
|
||||
gd->baudrate = getenv_ulong("baudrate", 10, CONFIG_BAUDRATE);
|
||||
#ifdef CONFIG_FSL_IFC
|
||||
init_early_memctl_regs(); /* tighten IFC timing */
|
||||
#endif
|
||||
|
||||
serial_init();
|
||||
console_init_f();
|
||||
dram_init();
|
||||
|
||||
/* Clear the BSS. */
|
||||
memset(__bss_start, 0, __bss_end - __bss_start);
|
||||
|
||||
board_init_r(NULL, 0);
|
||||
}
|
||||
|
||||
u32 spl_boot_device(void)
|
||||
{
|
||||
return BOOT_DEVICE_NAND;
|
||||
/*
|
||||
* Enable snoop requests and DVM message requests for
|
||||
* Slave insterface S4 (A53 core cluster)
|
||||
*/
|
||||
out_le32(&cci->slave[4].snoop_ctrl,
|
||||
CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_BOARD_LATE_INIT
|
||||
int board_late_init(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
#endif
|
79
arch/arm/cpu/armv8/fsl-layerscape/spl.c
Normal file
79
arch/arm/cpu/armv8/fsl-layerscape/spl.c
Normal file
|
@ -0,0 +1,79 @@
|
|||
/*
|
||||
* Copyright 2014-2015 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <spl.h>
|
||||
#include <asm/io.h>
|
||||
#include <fsl_ifc.h>
|
||||
#include <fsl_csu.h>
|
||||
#include <i2c.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
u32 spl_boot_device(void)
|
||||
{
|
||||
#ifdef CONFIG_SPL_MMC_SUPPORT
|
||||
return BOOT_DEVICE_MMC1;
|
||||
#endif
|
||||
#ifdef CONFIG_SPL_NAND_SUPPORT
|
||||
return BOOT_DEVICE_NAND;
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
|
||||
u32 spl_boot_mode(void)
|
||||
{
|
||||
switch (spl_boot_device()) {
|
||||
case BOOT_DEVICE_MMC1:
|
||||
#ifdef CONFIG_SPL_FAT_SUPPORT
|
||||
return MMCSD_MODE_FAT;
|
||||
#else
|
||||
return MMCSD_MODE_RAW;
|
||||
#endif
|
||||
case BOOT_DEVICE_NAND:
|
||||
return 0;
|
||||
default:
|
||||
puts("spl: error: unsupported device\n");
|
||||
hang();
|
||||
}
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SPL_BUILD
|
||||
void board_init_f(ulong dummy)
|
||||
{
|
||||
/* Set global data pointer */
|
||||
gd = &gdata;
|
||||
/* Clear global data */
|
||||
memset((void *)gd, 0, sizeof(gd_t));
|
||||
#ifdef CONFIG_LS2085A
|
||||
arch_cpu_init();
|
||||
#endif
|
||||
#ifdef CONFIG_FSL_IFC
|
||||
init_early_memctl_regs();
|
||||
#endif
|
||||
board_early_init_f();
|
||||
timer_init();
|
||||
#ifdef CONFIG_LS2085A
|
||||
env_init();
|
||||
#endif
|
||||
get_clocks();
|
||||
|
||||
preloader_console_init();
|
||||
|
||||
#ifdef CONFIG_SPL_I2C_SUPPORT
|
||||
i2c_init_all();
|
||||
#endif
|
||||
dram_init();
|
||||
|
||||
/* Clear the BSS */
|
||||
memset(__bss_start, 0, __bss_end - __bss_start);
|
||||
|
||||
#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
|
||||
enable_layerscape_ns_access();
|
||||
#endif
|
||||
board_init_r(NULL, 0);
|
||||
}
|
||||
#endif
|
|
@ -1,13 +0,0 @@
|
|||
#
|
||||
# Copyright 2014, Freescale Semiconductor
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
obj-y += cpu.o
|
||||
obj-y += lowlevel.o
|
||||
obj-y += soc.o
|
||||
obj-y += speed.o
|
||||
obj-$(CONFIG_SYS_HAS_SERDES) += fsl_lsch3_serdes.o ls2085a_serdes.o
|
||||
obj-$(CONFIG_MP) += mp.o
|
||||
obj-$(CONFIG_OF_LIBFDT) += fdt.o
|
|
@ -1,7 +0,0 @@
|
|||
/*
|
||||
* Copyright 2014, Freescale Semiconductor, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
void get_sys_info(struct sys_info *sys_info);
|
|
@ -1,3 +1,7 @@
|
|||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
dtb-$(CONFIG_S5PC100) += s5pc1xx-smdkc100.dtb
|
||||
dtb-$(CONFIG_S5PC110) += s5pc1xx-goni.dtb
|
||||
dtb-$(CONFIG_EXYNOS4) += exynos4210-origen.dtb \
|
||||
|
@ -65,6 +69,8 @@ dtb-$(CONFIG_ARCH_ZYNQ) += zynq-zc702.dtb \
|
|||
zynq-zc770-xm011.dtb \
|
||||
zynq-zc770-xm012.dtb \
|
||||
zynq-zc770-xm013.dtb
|
||||
dtb-$(CONFIG_ARCH_ZYNQMP) += \
|
||||
zynqmp-ep108.dtb
|
||||
dtb-$(CONFIG_AM33XX) += am335x-boneblack.dtb am335x-evm.dtb
|
||||
dtb-$(CONFIG_AM43XX) += am437x-gp-evm.dtb am437x-sk-evm.dtb
|
||||
|
||||
|
|
|
@ -31,6 +31,18 @@
|
|||
0xb0000000 0xea00000>;
|
||||
};
|
||||
|
||||
adc@12D10000 {
|
||||
u-boot,dm-pre-reloc;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
i2c@12CA0000 {
|
||||
s2mps11_pmic@66 {
|
||||
compatible = "samsung,s2mps11-pmic";
|
||||
reg = <0x66>;
|
||||
};
|
||||
};
|
||||
|
||||
ehci@12110000 {
|
||||
samsung,vbus-gpio = <&gpx2 6 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
|
|
@ -42,6 +42,13 @@
|
|||
xhci1 = "/xhci@12400000";
|
||||
};
|
||||
|
||||
adc@12D10000 {
|
||||
compatible = "samsung,exynos-adc-v2";
|
||||
reg = <0x12D10000 0x100>;
|
||||
interrupts = <0 106 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c@12CA0000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
|
@ -12,6 +12,7 @@
|
|||
|
||||
/ {
|
||||
model = "Samsung/Google Peach Pi board based on Exynos5800";
|
||||
cpu-model = "Exynos5800";
|
||||
|
||||
compatible = "google,pit-rev#", "google,pit",
|
||||
"google,peach", "samsung,exynos5800", "samsung,exynos5";
|
||||
|
|
|
@ -89,7 +89,7 @@
|
|||
#size-cells = <1>;
|
||||
compatible = "n25q00";
|
||||
reg = <0>; /* chip select */
|
||||
spi-max-frequency = <50000000>;
|
||||
spi-max-frequency = <100000000>;
|
||||
m25p,fast-read;
|
||||
page-size = <256>;
|
||||
block-size = <16>; /* 2^16, 64KB */
|
||||
|
|
|
@ -54,6 +54,14 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&usb0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* for U-boot only */
|
||||
/ {
|
||||
soc {
|
||||
|
|
|
@ -221,7 +221,7 @@
|
|||
reg = <0x65c00000 0x100>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usb1>;
|
||||
interrupts = <0 135 4>;
|
||||
interrupts = <0 137 4>;
|
||||
};
|
||||
|
||||
pinctrl: pinctrl@5f801000 {
|
||||
|
|
|
@ -44,6 +44,10 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&usb1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* for U-boot only */
|
||||
/ {
|
||||
soc {
|
||||
|
|
|
@ -210,6 +210,24 @@
|
|||
reg = <0x60001000 0x1000>,
|
||||
<0x60000100 0x100>;
|
||||
};
|
||||
|
||||
usb0: usb@65a00000 {
|
||||
compatible = "socionext,uniphier-xhci", "generic-xhci";
|
||||
status = "disabled";
|
||||
reg = <0x65a00000 0x100>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usb0>;
|
||||
interrupts = <0 134 4>;
|
||||
};
|
||||
|
||||
usb1: usb@65c00000 {
|
||||
compatible = "socionext,uniphier-xhci", "generic-xhci";
|
||||
status = "disabled";
|
||||
reg = <0x65c00000 0x100>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb2>;
|
||||
interrupts = <0 137 4>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
@ -42,6 +42,14 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&usb0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* for U-boot only */
|
||||
/ {
|
||||
soc {
|
||||
|
|
|
@ -42,6 +42,10 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&usb0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* for U-boot only */
|
||||
/ {
|
||||
soc {
|
||||
|
|
|
@ -235,6 +235,24 @@
|
|||
reg = <0x60001000 0x1000>,
|
||||
<0x60000100 0x100>;
|
||||
};
|
||||
|
||||
usb0: usb@65a00000 {
|
||||
compatible = "socionext,uniphier-xhci", "generic-xhci";
|
||||
status = "disabled";
|
||||
reg = <0x65a00000 0x100>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>;
|
||||
interrupts = <0 134 4>;
|
||||
};
|
||||
|
||||
usb1: usb@65c00000 {
|
||||
compatible = "socionext,uniphier-xhci", "generic-xhci";
|
||||
status = "disabled";
|
||||
reg = <0x65c00000 0x100>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>;
|
||||
interrupts = <0 137 4>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
@ -54,6 +54,7 @@
|
|||
};
|
||||
|
||||
amba: amba {
|
||||
u-boot,dm-pre-reloc;
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
|
|
@ -26,3 +26,8 @@
|
|||
&qspi {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
u-boot,dm-pre-reloc;
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
@ -21,3 +21,8 @@
|
|||
reg = <0 0x40000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
u-boot,dm-pre-reloc;
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
@ -376,6 +376,7 @@
|
|||
};
|
||||
|
||||
&uart1 {
|
||||
u-boot,dm-pre-reloc;
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart1_default>;
|
||||
|
|
|
@ -297,6 +297,7 @@
|
|||
};
|
||||
|
||||
&uart1 {
|
||||
u-boot,dm-pre-reloc;
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart1_default>;
|
||||
|
|
|
@ -88,6 +88,7 @@
|
|||
};
|
||||
|
||||
&uart1 {
|
||||
u-boot,dm-pre-reloc;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
|
|
@ -55,6 +55,7 @@
|
|||
};
|
||||
|
||||
&uart1 {
|
||||
u-boot,dm-pre-reloc;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
|
|
@ -62,5 +62,6 @@
|
|||
};
|
||||
|
||||
&uart1 {
|
||||
u-boot,dm-pre-reloc;
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
@ -75,5 +75,6 @@
|
|||
};
|
||||
|
||||
&uart0 {
|
||||
u-boot,dm-pre-reloc;
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
@ -54,6 +54,7 @@
|
|||
};
|
||||
|
||||
&uart1 {
|
||||
u-boot,dm-pre-reloc;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
|
|
@ -49,5 +49,6 @@
|
|||
};
|
||||
|
||||
&uart1 {
|
||||
u-boot,dm-pre-reloc;
|
||||
status = "okay";
|
||||
};
|
||||
|
|
119
arch/arm/dts/zynqmp-ep108-clk.dtsi
Normal file
119
arch/arm/dts/zynqmp-ep108-clk.dtsi
Normal file
|
@ -0,0 +1,119 @@
|
|||
/*
|
||||
* clock specification for Xilinx ZynqMP ep108 development board
|
||||
*
|
||||
* (C) Copyright 2015, Xilinx, Inc.
|
||||
*
|
||||
* Michal Simek <michal.simek@xilinx.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
&amba {
|
||||
misc_clk: misc_clk {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <25000000>;
|
||||
};
|
||||
|
||||
i2c_clk: i2c_clk {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0x0>;
|
||||
clock-frequency = <111111111>;
|
||||
};
|
||||
|
||||
sata_clk: sata_clk {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <75000000>;
|
||||
};
|
||||
|
||||
dp_aclk: clock0 {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <50000000>;
|
||||
clock-accuracy = <100>;
|
||||
};
|
||||
|
||||
dp_aud_clk: clock1 {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <22579200>;
|
||||
clock-accuracy = <100>;
|
||||
};
|
||||
};
|
||||
|
||||
&can0 {
|
||||
clocks = <&misc_clk &misc_clk>;
|
||||
};
|
||||
|
||||
&gem0 {
|
||||
clocks = <&misc_clk>, <&misc_clk>, <&misc_clk>;
|
||||
};
|
||||
|
||||
&gpio {
|
||||
clocks = <&misc_clk>;
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
clocks = <&i2c_clk>;
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
clocks = <&i2c_clk>;
|
||||
};
|
||||
|
||||
&qspi {
|
||||
clocks = <&misc_clk &misc_clk>;
|
||||
};
|
||||
|
||||
&sata {
|
||||
clocks = <&sata_clk>;
|
||||
};
|
||||
|
||||
&sdhci0 {
|
||||
clocks = <&misc_clk>, <&misc_clk>;
|
||||
};
|
||||
|
||||
&sdhci1 {
|
||||
clocks = <&misc_clk>, <&misc_clk>;
|
||||
};
|
||||
|
||||
&spi0 {
|
||||
clocks = <&misc_clk &misc_clk>;
|
||||
};
|
||||
|
||||
&spi1 {
|
||||
clocks = <&misc_clk &misc_clk>;
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
clocks = <&misc_clk &misc_clk>;
|
||||
};
|
||||
|
||||
&usb0 {
|
||||
clocks = <&misc_clk>, <&misc_clk>;
|
||||
};
|
||||
|
||||
&usb1 {
|
||||
clocks = <&misc_clk>, <&misc_clk>;
|
||||
};
|
||||
|
||||
&watchdog0 {
|
||||
clocks= <&misc_clk>;
|
||||
};
|
||||
|
||||
&xilinx_drm {
|
||||
clocks = <&misc_clk>;
|
||||
};
|
||||
|
||||
&xlnx_dp {
|
||||
clocks = <&dp_aclk>, <&dp_aud_clk>;
|
||||
};
|
||||
|
||||
&xlnx_dp_snd_codec0 {
|
||||
clocks = <&dp_aud_clk>;
|
||||
};
|
||||
|
||||
&xlnx_dpdma {
|
||||
clocks = <&misc_clk>;
|
||||
};
|
174
arch/arm/dts/zynqmp-ep108.dts
Normal file
174
arch/arm/dts/zynqmp-ep108.dts
Normal file
|
@ -0,0 +1,174 @@
|
|||
/*
|
||||
* dts file for Xilinx ZynqMP ep108 development board
|
||||
*
|
||||
* (C) Copyright 2014 - 2015, Xilinx, Inc.
|
||||
*
|
||||
* Michal Simek <michal.simek@xilinx.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/include/ "zynqmp.dtsi"
|
||||
/include/ "zynqmp-ep108-clk.dtsi"
|
||||
|
||||
/ {
|
||||
model = "ZynqMP EP108";
|
||||
|
||||
aliases {
|
||||
serial0 = &uart0;
|
||||
spi0 = &qspi;
|
||||
spi1 = &spi0;
|
||||
spi2 = &spi1;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x0 0x40000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&can0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gem0 {
|
||||
status = "okay";
|
||||
phy-handle = <&phy0>;
|
||||
phy-mode = "rgmii-id";
|
||||
phy0: phy@0{
|
||||
reg = <0>;
|
||||
max-speed = <100>;
|
||||
};
|
||||
};
|
||||
|
||||
&gpio {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
eeprom@54 {
|
||||
compatible = "at,24c64";
|
||||
reg = <0x54>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
eeprom@55 {
|
||||
compatible = "at,24c64";
|
||||
reg = <0x55>;
|
||||
};
|
||||
};
|
||||
|
||||
&qspi {
|
||||
status = "okay";
|
||||
flash@0 {
|
||||
compatible = "n25q512a11";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x0>;
|
||||
spi-tx-bus-width = <1>;
|
||||
spi-rx-bus-width = <4>;
|
||||
spi-max-frequency = <10000000>;
|
||||
partition@qspi-fsbl-uboot { /* for testing purpose */
|
||||
label = "qspi-fsbl-uboot";
|
||||
reg = <0x0 0x100000>;
|
||||
};
|
||||
partition@qspi-linux { /* for testing purpose */
|
||||
label = "qspi-linux";
|
||||
reg = <0x100000 0x500000>;
|
||||
};
|
||||
partition@qspi-device-tree { /* for testing purpose */
|
||||
label = "qspi-device-tree";
|
||||
reg = <0x600000 0x20000>;
|
||||
};
|
||||
partition@qspi-rootfs { /* for testing purpose */
|
||||
label = "qspi-rootfs";
|
||||
reg = <0x620000 0x5E0000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&sata {
|
||||
status = "okay";
|
||||
ceva,broken-gen2;
|
||||
};
|
||||
|
||||
&sdhci0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhci1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&spi0 {
|
||||
status = "okay";
|
||||
num-cs = <1>;
|
||||
spi0_flash0: spi0_flash0@0 {
|
||||
compatible = "m25p80";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
spi-max-frequency = <50000000>;
|
||||
reg = <0>;
|
||||
|
||||
spi0_flash0@00000000 {
|
||||
label = "spi0_flash0";
|
||||
reg = <0x0 0x100000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&spi1 {
|
||||
status = "okay";
|
||||
num-cs = <1>;
|
||||
spi1_flash0: spi1_flash0@0 {
|
||||
compatible = "m25p80";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
spi-max-frequency = <50000000>;
|
||||
reg = <0>;
|
||||
|
||||
spi1_flash0@00000000 {
|
||||
label = "spi1_flash0";
|
||||
reg = <0x0 0x100000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb0 {
|
||||
status = "okay";
|
||||
dr_mode = "peripheral";
|
||||
maximum-speed = "high-speed";
|
||||
};
|
||||
|
||||
&usb1 {
|
||||
status = "okay";
|
||||
dr_mode = "host";
|
||||
maximum-speed = "high-speed";
|
||||
};
|
||||
|
||||
&watchdog0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&xlnx_dp {
|
||||
xlnx,max-pclock-frequency = <200000>;
|
||||
};
|
||||
|
||||
&xlnx_dpdma {
|
||||
xlnx,axi-clock-freq = <200000000>;
|
||||
};
|
668
arch/arm/dts/zynqmp.dtsi
Normal file
668
arch/arm/dts/zynqmp.dtsi
Normal file
|
@ -0,0 +1,668 @@
|
|||
/*
|
||||
* dts file for Xilinx ZynqMP
|
||||
*
|
||||
* (C) Copyright 2014 - 2015, Xilinx, Inc.
|
||||
*
|
||||
* Michal Simek <michal.simek@xilinx.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
/ {
|
||||
compatible = "xlnx,zynqmp";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@0 {
|
||||
compatible = "arm,cortex-a53", "arm,armv8";
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
reg = <0x0>;
|
||||
};
|
||||
|
||||
cpu@1 {
|
||||
compatible = "arm,cortex-a53", "arm,armv8";
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
reg = <0x1>;
|
||||
};
|
||||
|
||||
cpu@2 {
|
||||
compatible = "arm,cortex-a53", "arm,armv8";
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
reg = <0x2>;
|
||||
};
|
||||
|
||||
cpu@3 {
|
||||
compatible = "arm,cortex-a53", "arm,armv8";
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
reg = <0x3>;
|
||||
};
|
||||
};
|
||||
|
||||
pmu {
|
||||
compatible = "arm,armv8-pmuv3";
|
||||
interrupts = <0 143 4>,
|
||||
<0 144 4>,
|
||||
<0 145 4>,
|
||||
<0 146 4>;
|
||||
};
|
||||
|
||||
psci {
|
||||
compatible = "arm,psci-0.2";
|
||||
method = "smc";
|
||||
};
|
||||
|
||||
firmware {
|
||||
compatible = "xlnx,zynqmp-pm";
|
||||
method = "smc";
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <1 13 0xf01>,
|
||||
<1 14 0xf01>,
|
||||
<1 11 0xf01>,
|
||||
<1 10 0xf01>;
|
||||
};
|
||||
|
||||
amba_apu: amba_apu {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
gic: interrupt-controller@f9010000 {
|
||||
compatible = "arm,gic-400", "arm,cortex-a15-gic";
|
||||
#interrupt-cells = <3>;
|
||||
reg = <0x0 0xf9010000 0x10000>,
|
||||
<0x0 0xf902f000 0x2000>,
|
||||
<0x0 0xf9040000 0x20000>,
|
||||
<0x0 0xf906f000 0x2000>;
|
||||
interrupt-controller;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <1 9 0xf04>;
|
||||
};
|
||||
};
|
||||
|
||||
amba: amba {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
can0: can@ff060000 {
|
||||
compatible = "xlnx,zynq-can-1.0";
|
||||
status = "disabled";
|
||||
clock-names = "can_clk", "pclk";
|
||||
reg = <0x0 0xff060000 0x1000>;
|
||||
interrupts = <0 23 4>;
|
||||
interrupt-parent = <&gic>;
|
||||
tx-fifo-depth = <0x40>;
|
||||
rx-fifo-depth = <0x40>;
|
||||
};
|
||||
|
||||
can1: can@ff070000 {
|
||||
compatible = "xlnx,zynq-can-1.0";
|
||||
status = "disabled";
|
||||
clock-names = "can_clk", "pclk";
|
||||
reg = <0x0 0xff070000 0x1000>;
|
||||
interrupts = <0 24 4>;
|
||||
interrupt-parent = <&gic>;
|
||||
tx-fifo-depth = <0x40>;
|
||||
rx-fifo-depth = <0x40>;
|
||||
};
|
||||
|
||||
/* GDMA */
|
||||
fpd_dma_chan1: dma@fd500000 {
|
||||
status = "disabled";
|
||||
compatible = "xlnx,zynqmp-dma-1.0";
|
||||
reg = <0x0 0xfd500000 0x1000>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 124 4>;
|
||||
xlnx,id = <0>;
|
||||
xlnx,bus-width = <128>;
|
||||
};
|
||||
|
||||
fpd_dma_chan2: dma@fd510000 {
|
||||
status = "disabled";
|
||||
compatible = "xlnx,zynqmp-dma-1.0";
|
||||
reg = <0x0 0xfd510000 0x1000>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 125 4>;
|
||||
xlnx,id = <1>;
|
||||
xlnx,bus-width = <128>;
|
||||
};
|
||||
|
||||
fpd_dma_chan3: dma@fd520000 {
|
||||
status = "disabled";
|
||||
compatible = "xlnx,zynqmp-dma-1.0";
|
||||
reg = <0x0 0xfd520000 0x1000>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 126 4>;
|
||||
xlnx,id = <2>;
|
||||
xlnx,bus-width = <128>;
|
||||
};
|
||||
|
||||
fpd_dma_chan4: dma@fd530000 {
|
||||
status = "disabled";
|
||||
compatible = "xlnx,zynqmp-dma-1.0";
|
||||
reg = <0x0 0xfd530000 0x1000>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 127 4>;
|
||||
xlnx,id = <3>;
|
||||
xlnx,bus-width = <128>;
|
||||
};
|
||||
|
||||
fpd_dma_chan5: dma@fd540000 {
|
||||
status = "disabled";
|
||||
compatible = "xlnx,zynqmp-dma-1.0";
|
||||
reg = <0x0 0xfd540000 0x1000>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 128 4>;
|
||||
xlnx,id = <4>;
|
||||
xlnx,bus-width = <128>;
|
||||
};
|
||||
|
||||
fpd_dma_chan6: dma@fd550000 {
|
||||
status = "disabled";
|
||||
compatible = "xlnx,zynqmp-dma-1.0";
|
||||
reg = <0x0 0xfd550000 0x1000>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 129 4>;
|
||||
xlnx,id = <5>;
|
||||
xlnx,bus-width = <128>;
|
||||
};
|
||||
|
||||
fpd_dma_chan7: dma@fd560000 {
|
||||
status = "disabled";
|
||||
compatible = "xlnx,zynqmp-dma-1.0";
|
||||
reg = <0x0 0xfd560000 0x1000>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 130 4>;
|
||||
xlnx,id = <6>;
|
||||
xlnx,bus-width = <128>;
|
||||
};
|
||||
|
||||
fpd_dma_chan8: dma@fd570000 {
|
||||
status = "disabled";
|
||||
compatible = "xlnx,zynqmp-dma-1.0";
|
||||
reg = <0x0 0xfd570000 0x1000>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 131 4>;
|
||||
xlnx,id = <7>;
|
||||
xlnx,bus-width = <128>;
|
||||
};
|
||||
|
||||
gpu: gpu@fd4b0000 {
|
||||
status = "disabled";
|
||||
compatible = "arm,mali-400", "arm,mali-utgard";
|
||||
reg = <0x0 0xfd4b0000 0x30000>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>;
|
||||
interrupt-names = "IRQGP", "IRQGPMMU", "IRQPP0", "IRQPPMMU0", "IRQPP1", "IRQPPMMU1";
|
||||
};
|
||||
|
||||
/* ADMA */
|
||||
lpd_dma_chan1: dma@ffa80000 {
|
||||
status = "disabled";
|
||||
compatible = "xlnx,zynqmp-dma-1.0";
|
||||
reg = <0x0 0xffa80000 0x1000>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 77 4>;
|
||||
xlnx,id = <0>;
|
||||
xlnx,bus-width = <64>;
|
||||
};
|
||||
|
||||
lpd_dma_chan2: dma@ffa90000 {
|
||||
status = "disabled";
|
||||
compatible = "xlnx,zynqmp-dma-1.0";
|
||||
reg = <0x0 0xffa90000 0x1000>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 78 4>;
|
||||
xlnx,id = <1>;
|
||||
xlnx,bus-width = <64>;
|
||||
};
|
||||
|
||||
lpd_dma_chan3: dma@ffaa0000 {
|
||||
status = "disabled";
|
||||
compatible = "xlnx,zynqmp-dma-1.0";
|
||||
reg = <0x0 0xffaa0000 0x1000>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 79 4>;
|
||||
xlnx,id = <2>;
|
||||
xlnx,bus-width = <64>;
|
||||
};
|
||||
|
||||
lpd_dma_chan4: dma@ffab0000 {
|
||||
status = "disabled";
|
||||
compatible = "xlnx,zynqmp-dma-1.0";
|
||||
reg = <0x0 0xffab0000 0x1000>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 80 4>;
|
||||
xlnx,id = <3>;
|
||||
xlnx,bus-width = <64>;
|
||||
};
|
||||
|
||||
lpd_dma_chan5: dma@ffac0000 {
|
||||
status = "disabled";
|
||||
compatible = "xlnx,zynqmp-dma-1.0";
|
||||
reg = <0x0 0xffac0000 0x1000>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 81 4>;
|
||||
xlnx,id = <4>;
|
||||
xlnx,bus-width = <64>;
|
||||
};
|
||||
|
||||
lpd_dma_chan6: dma@ffad0000 {
|
||||
status = "disabled";
|
||||
compatible = "xlnx,zynqmp-dma-1.0";
|
||||
reg = <0x0 0xffad0000 0x1000>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 82 4>;
|
||||
xlnx,id = <5>;
|
||||
xlnx,bus-width = <64>;
|
||||
};
|
||||
|
||||
lpd_dma_chan7: dma@ffae0000 {
|
||||
status = "disabled";
|
||||
compatible = "xlnx,zynqmp-dma-1.0";
|
||||
reg = <0x0 0xffae0000 0x1000>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 83 4>;
|
||||
xlnx,id = <6>;
|
||||
xlnx,bus-width = <64>;
|
||||
};
|
||||
|
||||
lpd_dma_chan8: dma@ffaf0000 {
|
||||
status = "disabled";
|
||||
compatible = "xlnx,zynqmp-dma-1.0";
|
||||
reg = <0x0 0xffaf0000 0x1000>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 84 4>;
|
||||
xlnx,id = <7>;
|
||||
xlnx,bus-width = <64>;
|
||||
};
|
||||
|
||||
nand0: nand@ff100000 {
|
||||
compatible = "arasan,nfc-v3p10";
|
||||
status = "disabled";
|
||||
reg = <0x0 0xff100000 0x1000>;
|
||||
clock-names = "clk_sys", "clk_flash";
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 14 4>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
};
|
||||
|
||||
gem0: ethernet@ff0b0000 {
|
||||
compatible = "cdns,gem";
|
||||
status = "disabled";
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 57 4>, <0 57 4>;
|
||||
reg = <0x0 0xff0b0000 0x1000>;
|
||||
clock-names = "pclk", "hclk", "tx_clk";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
jumbo-max-len = <10240>;
|
||||
jumbo-supported;
|
||||
};
|
||||
|
||||
gem1: ethernet@ff0c0000 {
|
||||
compatible = "cdns,gem";
|
||||
status = "disabled";
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 59 4>, <0 59 4>;
|
||||
reg = <0x0 0xff0c0000 0x1000>;
|
||||
clock-names = "pclk", "hclk", "tx_clk";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
jumbo-max-len = <10240>;
|
||||
jumbo-supported;
|
||||
};
|
||||
|
||||
gem2: ethernet@ff0d0000 {
|
||||
compatible = "cdns,gem";
|
||||
status = "disabled";
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 61 4>, <0 61 4>;
|
||||
reg = <0x0 0xff0d0000 0x1000>;
|
||||
clock-names = "pclk", "hclk", "tx_clk";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
jumbo-max-len = <10240>;
|
||||
jumbo-supported;
|
||||
};
|
||||
|
||||
gem3: ethernet@ff0e0000 {
|
||||
compatible = "cdns,gem";
|
||||
status = "disabled";
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 63 4>, <0 63 4>;
|
||||
reg = <0x0 0xff0e0000 0x1000>;
|
||||
clock-names = "pclk", "hclk", "tx_clk";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
jumbo-max-len = <10240>;
|
||||
jumbo-supported;
|
||||
};
|
||||
|
||||
gpio: gpio@ff0a0000 {
|
||||
compatible = "xlnx,zynqmp-gpio-1.0";
|
||||
status = "disabled";
|
||||
#gpio-cells = <0x2>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 16 4>;
|
||||
reg = <0x0 0xff0a0000 0x1000>;
|
||||
};
|
||||
|
||||
i2c0: i2c@ff020000 {
|
||||
compatible = "cdns,i2c-r1p10";
|
||||
status = "disabled";
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 17 4>;
|
||||
reg = <0x0 0xff020000 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
i2c1: i2c@ff030000 {
|
||||
compatible = "cdns,i2c-r1p10";
|
||||
status = "disabled";
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 18 4>;
|
||||
reg = <0x0 0xff030000 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
pcie: pcie@fd0e0000 {
|
||||
compatible = "xlnx,nwl-pcie-2.11";
|
||||
status = "disabled";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
device_type = "pci";
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = < 0 118 4>,
|
||||
< 0 116 4>,
|
||||
< 0 115 4>, /* MSI_1 [63...32] */
|
||||
< 0 114 4 >; /* MSI_0 [31...0] */
|
||||
interrupt-names = "misc", "intx", "msi_1", "msi_0";
|
||||
reg = <0x0 0xfd0e0000 0x1000>,
|
||||
<0x0 0xfd480000 0x1000>,
|
||||
<0x0 0xe0000000 0x1000000>;
|
||||
reg-names = "breg", "pcireg", "cfg";
|
||||
ranges = <0x02000000 0x00000000 0xe1000000 0x00000000 0xe1000000 0 0x0f000000>;
|
||||
};
|
||||
|
||||
qspi: spi@ff0f0000 {
|
||||
compatible = "xlnx,zynqmp-qspi-1.0";
|
||||
status = "disabled";
|
||||
clock-names = "ref_clk", "pclk";
|
||||
interrupts = <0 15 4>;
|
||||
interrupt-parent = <&gic>;
|
||||
num-cs = <1>;
|
||||
reg = <0x0 0xff0f0000 0x1000 0x0 0xc0000000 0x8000000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
rtc: rtc@ffa60000 {
|
||||
compatible = "xlnx,zynqmp-rtc";
|
||||
status = "disabled";
|
||||
reg = <0x0 0xffa60000 0x100>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 26 4>, <0 27 4>;
|
||||
interrupt-names = "alarm", "sec";
|
||||
};
|
||||
|
||||
sata: ahci@fd0c0000 {
|
||||
compatible = "ceva,ahci-1v84";
|
||||
status = "disabled";
|
||||
reg = <0x0 0xfd0c0000 0x2000>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 133 4>;
|
||||
};
|
||||
|
||||
sdhci0: sdhci@ff160000 {
|
||||
compatible = "arasan,sdhci-8.9a";
|
||||
status = "disabled";
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 48 4>;
|
||||
reg = <0x0 0xff160000 0x1000>;
|
||||
clock-names = "clk_xin", "clk_ahb";
|
||||
};
|
||||
|
||||
sdhci1: sdhci@ff170000 {
|
||||
compatible = "arasan,sdhci-8.9a";
|
||||
status = "disabled";
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 49 4>;
|
||||
reg = <0x0 0xff170000 0x1000>;
|
||||
clock-names = "clk_xin", "clk_ahb";
|
||||
};
|
||||
|
||||
smmu: smmu@fd800000 {
|
||||
compatible = "arm,mmu-500";
|
||||
reg = <0x0 0xfd800000 0x20000>;
|
||||
#global-interrupts = <1>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 157 4>,
|
||||
<0 157 4>, <0 157 4>, <0 157 4>, <0 157 4>,
|
||||
<0 157 4>, <0 157 4>, <0 157 4>, <0 157 4>,
|
||||
<0 157 4>, <0 157 4>, <0 157 4>, <0 157 4>,
|
||||
<0 157 4>, <0 157 4>, <0 157 4>, <0 157 4>;
|
||||
};
|
||||
|
||||
spi0: spi@ff040000 {
|
||||
compatible = "cdns,spi-r1p6";
|
||||
status = "disabled";
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 19 4>;
|
||||
reg = <0x0 0xff040000 0x1000>;
|
||||
clock-names = "ref_clk", "pclk";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
spi1: spi@ff050000 {
|
||||
compatible = "cdns,spi-r1p6";
|
||||
status = "disabled";
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 20 4>;
|
||||
reg = <0x0 0xff050000 0x1000>;
|
||||
clock-names = "ref_clk", "pclk";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
ttc0: timer@ff110000 {
|
||||
compatible = "cdns,ttc";
|
||||
status = "disabled";
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 36 4>, <0 37 4>, <0 38 4>;
|
||||
reg = <0x0 0xff110000 0x1000>;
|
||||
timer-width = <32>;
|
||||
};
|
||||
|
||||
ttc1: timer@ff120000 {
|
||||
compatible = "cdns,ttc";
|
||||
status = "disabled";
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 39 4>, <0 40 4>, <0 41 4>;
|
||||
reg = <0x0 0xff120000 0x1000>;
|
||||
timer-width = <32>;
|
||||
};
|
||||
|
||||
ttc2: timer@ff130000 {
|
||||
compatible = "cdns,ttc";
|
||||
status = "disabled";
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 42 4>, <0 43 4>, <0 44 4>;
|
||||
reg = <0x0 0xff130000 0x1000>;
|
||||
timer-width = <32>;
|
||||
};
|
||||
|
||||
ttc3: timer@ff140000 {
|
||||
compatible = "cdns,ttc";
|
||||
status = "disabled";
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 45 4>, <0 46 4>, <0 47 4>;
|
||||
reg = <0x0 0xff140000 0x1000>;
|
||||
timer-width = <32>;
|
||||
};
|
||||
|
||||
uart0: serial@ff000000 {
|
||||
compatible = "cdns,uart-r1p8";
|
||||
status = "disabled";
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 21 4>;
|
||||
reg = <0x0 0xff000000 0x1000>;
|
||||
clock-names = "uart_clk", "pclk";
|
||||
};
|
||||
|
||||
uart1: serial@ff010000 {
|
||||
compatible = "cdns,uart-r1p8";
|
||||
status = "disabled";
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 22 4>;
|
||||
reg = <0x0 0xff010000 0x1000>;
|
||||
clock-names = "uart_clk", "pclk";
|
||||
};
|
||||
|
||||
usb0: usb@fe200000 {
|
||||
compatible = "snps,dwc3";
|
||||
status = "disabled";
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 65 4>;
|
||||
reg = <0x0 0xfe200000 0x40000>;
|
||||
clock-names = "clk_xin", "clk_ahb";
|
||||
};
|
||||
|
||||
usb1: usb@fe300000 {
|
||||
compatible = "snps,dwc3";
|
||||
status = "disabled";
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 70 4>;
|
||||
reg = <0x0 0xfe300000 0x40000>;
|
||||
clock-names = "clk_xin", "clk_ahb";
|
||||
};
|
||||
|
||||
watchdog0: watchdog@fd4d0000 {
|
||||
compatible = "cdns,wdt-r1p2";
|
||||
status = "disabled";
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 52 1>;
|
||||
reg = <0x0 0xfd4d0000 0x1000>;
|
||||
timeout-sec = <10>;
|
||||
};
|
||||
|
||||
xilinx_drm: xilinx_drm {
|
||||
compatible = "xlnx,drm";
|
||||
status = "disabled";
|
||||
xlnx,encoder-slave = <&xlnx_dp>;
|
||||
xlnx,connector-type = "DisplayPort";
|
||||
xlnx,dp-sub = <&xlnx_dp_sub>;
|
||||
planes {
|
||||
xlnx,pixel-format = "rgb565";
|
||||
plane0 {
|
||||
dmas = <&xlnx_dpdma 3>;
|
||||
dma-names = "dma";
|
||||
};
|
||||
plane1 {
|
||||
dmas = <&xlnx_dpdma 0>;
|
||||
dma-names = "dma";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
xlnx_dp: dp@43c00000 {
|
||||
compatible = "xlnx,v-dp";
|
||||
status = "disabled";
|
||||
reg = <0x0 0xfd4a0000 0x1000>;
|
||||
interrupts = <0 119 4>;
|
||||
interrupt-parent = <&gic>;
|
||||
clock-names = "aclk", "aud_clk";
|
||||
xlnx,dp-version = "v1.2";
|
||||
xlnx,max-lanes = <2>;
|
||||
xlnx,max-link-rate = <540000>;
|
||||
xlnx,max-bpc = <16>;
|
||||
xlnx,enable-ycrcb;
|
||||
xlnx,colormetry = "rgb";
|
||||
xlnx,bpc = <8>;
|
||||
xlnx,audio-chan = <2>;
|
||||
xlnx,dp-sub = <&xlnx_dp_sub>;
|
||||
};
|
||||
|
||||
xlnx_dp_snd_card: dp_snd_card {
|
||||
compatible = "xlnx,dp-snd-card";
|
||||
status = "disabled";
|
||||
xlnx,dp-snd-pcm = <&xlnx_dp_snd_pcm0>, <&xlnx_dp_snd_pcm1>;
|
||||
xlnx,dp-snd-codec = <&xlnx_dp_snd_codec0>;
|
||||
};
|
||||
|
||||
xlnx_dp_snd_codec0: dp_snd_codec0 {
|
||||
compatible = "xlnx,dp-snd-codec";
|
||||
status = "disabled";
|
||||
clock-names = "aud_clk";
|
||||
};
|
||||
|
||||
xlnx_dp_snd_pcm0: dp_snd_pcm0 {
|
||||
compatible = "xlnx,dp-snd-pcm";
|
||||
status = "disabled";
|
||||
dmas = <&xlnx_dpdma 4>;
|
||||
dma-names = "tx";
|
||||
};
|
||||
|
||||
xlnx_dp_snd_pcm1: dp_snd_pcm1 {
|
||||
compatible = "xlnx,dp-snd-pcm";
|
||||
status = "disabled";
|
||||
dmas = <&xlnx_dpdma 5>;
|
||||
dma-names = "tx";
|
||||
};
|
||||
|
||||
xlnx_dp_sub: dp_sub@43c0a000 {
|
||||
compatible = "xlnx,dp-sub";
|
||||
status = "disabled";
|
||||
reg = <0x0 0xfd4aa000 0x1000>, <0x0 0xfd4ab000 0x1000>, <0x0 0xfd4ac000 0x1000>;
|
||||
reg-names = "blend", "av_buf", "aud";
|
||||
xlnx,output-fmt = "rgb";
|
||||
};
|
||||
|
||||
xlnx_dpdma: dma@fd4c0000 {
|
||||
compatible = "xlnx,dpdma";
|
||||
status = "disabled";
|
||||
reg = <0x0 0xfd4c0000 0x1000>;
|
||||
interrupts = <0 122 4>;
|
||||
interrupt-parent = <&gic>;
|
||||
clock-names = "axi_clk";
|
||||
dma-channels = <6>;
|
||||
#dma-cells = <1>;
|
||||
dma-video0channel@43c10000 {
|
||||
compatible = "xlnx,video0";
|
||||
};
|
||||
dma-video1channel@43c10000 {
|
||||
compatible = "xlnx,video1";
|
||||
};
|
||||
dma-video2channel@43c10000 {
|
||||
compatible = "xlnx,video2";
|
||||
};
|
||||
dma-graphicschannel@43c10000 {
|
||||
compatible = "xlnx,graphics";
|
||||
};
|
||||
dma-audio0channel@43c10000 {
|
||||
compatible = "xlnx,audio0";
|
||||
};
|
||||
dma-audio1channel@43c10000 {
|
||||
compatible = "xlnx,audio1";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
|
@ -1,12 +1,12 @@
|
|||
/*
|
||||
* Copyright 2014 Freescale Semiconductor, Inc.
|
||||
* Copyright 2015 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_FSL_LSCH3_CLOCK_H_
|
||||
#define __ASM_ARCH_FSL_LSCH3_CLOCK_H_
|
||||
#ifndef __ASM_ARCH_FSL_LAYERSCAPE_CLOCK_H_
|
||||
#define __ASM_ARCH_FSL_LAYERSCAPE_CLOCK_H_
|
||||
|
||||
#include <common.h>
|
||||
|
||||
|
@ -21,4 +21,4 @@ enum mxc_clock {
|
|||
|
||||
unsigned int mxc_get_clock(enum mxc_clock clk);
|
||||
|
||||
#endif /* __ASM_ARCH_FSL_LSCH3_CLOCK_H_ */
|
||||
#endif /* __ASM_ARCH_FSL_LAYERSCAPE_CLOCK_H_ */
|
143
arch/arm/include/asm/arch-fsl-layerscape/config.h
Normal file
143
arch/arm/include/asm/arch-fsl-layerscape/config.h
Normal file
|
@ -0,0 +1,143 @@
|
|||
/*
|
||||
* Copyright 2015, Freescale Semiconductor
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_
|
||||
#define _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_
|
||||
|
||||
#include <fsl_ddrc_version.h>
|
||||
|
||||
#ifdef CONFIG_SYS_FSL_DDR4
|
||||
#define CONFIG_SYS_FSL_DDRC_GEN4
|
||||
#else
|
||||
#define CONFIG_SYS_FSL_DDRC_ARM_GEN3 /* Enable Freescale ARM DDR3 driver */
|
||||
#endif
|
||||
#define CONFIG_SYS_FSL_DDR /* Freescale DDR driver */
|
||||
#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0
|
||||
|
||||
#if defined(CONFIG_LS2085A)
|
||||
#define CONFIG_MAX_CPUS 16
|
||||
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
|
||||
#define CONFIG_NUM_DDR_CONTROLLERS 3
|
||||
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 }
|
||||
#define SRDS_MAX_LANES 8
|
||||
#define CONFIG_SYS_FSL_SRDS_1
|
||||
#define CONFIG_SYS_FSL_SRDS_2
|
||||
#define CONFIG_SYS_PAGE_SIZE 0x10000
|
||||
#define CONFIG_SYS_CACHELINE_SIZE 64
|
||||
#ifndef L1_CACHE_BYTES
|
||||
#define L1_CACHE_SHIFT 6
|
||||
#define L1_CACHE_BYTES BIT(L1_CACHE_SHIFT)
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
|
||||
#define CONFIG_SYS_FSL_OCRAM_SIZE 0x00200000 /* 2M */
|
||||
|
||||
/* DDR */
|
||||
#define CONFIG_SYS_FSL_DDR_LE
|
||||
#define CONFIG_SYS_LS2_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
|
||||
#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_LS2_DDR_BLOCK1_SIZE
|
||||
|
||||
#define CONFIG_SYS_FSL_CCSR_GUR_LE
|
||||
#define CONFIG_SYS_FSL_CCSR_SCFG_LE
|
||||
#define CONFIG_SYS_FSL_ESDHC_LE
|
||||
#define CONFIG_SYS_FSL_IFC_LE
|
||||
|
||||
#define CONFIG_SYS_MEMAC_LITTLE_ENDIAN
|
||||
|
||||
/* Generic Interrupt Controller Definitions */
|
||||
#define GICD_BASE 0x06000000
|
||||
#define GICR_BASE 0x06100000
|
||||
|
||||
/* SMMU Defintions */
|
||||
#define SMMU_BASE 0x05000000 /* GR0 Base */
|
||||
|
||||
/* Cache Coherent Interconnect */
|
||||
#define CCI_MN_BASE 0x04000000
|
||||
#define CCI_MN_RNF_NODEID_LIST 0x180
|
||||
#define CCI_MN_DVM_DOMAIN_CTL 0x200
|
||||
#define CCI_MN_DVM_DOMAIN_CTL_SET 0x210
|
||||
|
||||
#define CCI_RN_I_0_BASE (CCI_MN_BASE + 0x800000)
|
||||
#define CCI_RN_I_2_BASE (CCI_MN_BASE + 0x820000)
|
||||
#define CCI_RN_I_6_BASE (CCI_MN_BASE + 0x860000)
|
||||
#define CCI_RN_I_12_BASE (CCI_MN_BASE + 0x8C0000)
|
||||
#define CCI_RN_I_16_BASE (CCI_MN_BASE + 0x900000)
|
||||
#define CCI_RN_I_20_BASE (CCI_MN_BASE + 0x940000)
|
||||
|
||||
#define CCI_S0_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x10)
|
||||
#define CCI_S1_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x110)
|
||||
#define CCI_S2_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x210)
|
||||
|
||||
/* TZ Protection Controller Definitions */
|
||||
#define TZPC_BASE 0x02200000
|
||||
#define TZPCR0SIZE_BASE (TZPC_BASE)
|
||||
#define TZPCDECPROT_0_STAT_BASE (TZPC_BASE + 0x800)
|
||||
#define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804)
|
||||
#define TZPCDECPROT_0_CLR_BASE (TZPC_BASE + 0x808)
|
||||
#define TZPCDECPROT_1_STAT_BASE (TZPC_BASE + 0x80C)
|
||||
#define TZPCDECPROT_1_SET_BASE (TZPC_BASE + 0x810)
|
||||
#define TZPCDECPROT_1_CLR_BASE (TZPC_BASE + 0x814)
|
||||
#define TZPCDECPROT_2_STAT_BASE (TZPC_BASE + 0x818)
|
||||
#define TZPCDECPROT_2_SET_BASE (TZPC_BASE + 0x81C)
|
||||
#define TZPCDECPROT_2_CLR_BASE (TZPC_BASE + 0x820)
|
||||
|
||||
#define CONFIG_SYS_FSL_ERRATUM_A008336
|
||||
#define CONFIG_SYS_FSL_ERRATUM_A008511
|
||||
#define CONFIG_SYS_FSL_ERRATUM_A008514
|
||||
#define CONFIG_SYS_FSL_ERRATUM_A008585
|
||||
#define CONFIG_SYS_FSL_ERRATUM_A008751
|
||||
#elif defined(CONFIG_LS1043A)
|
||||
#define CONFIG_MAX_CPUS 4
|
||||
#define CONFIG_SYS_CACHELINE_SIZE 64
|
||||
#define CONFIG_SYS_FMAN_V3
|
||||
#define CONFIG_SYS_NUM_FMAN 1
|
||||
#define CONFIG_SYS_NUM_FM1_DTSEC 7
|
||||
#define CONFIG_SYS_NUM_FM1_10GEC 1
|
||||
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
|
||||
#define CONFIG_NUM_DDR_CONTROLLERS 1
|
||||
#define CONFIG_SYS_CCSRBAR_DEFAULT 0x01000000
|
||||
#define CONFIG_SYS_FSL_SEC_COMPAT 5
|
||||
#define CONFIG_SYS_FSL_OCRAM_BASE 0x10000000 /* initial RAM */
|
||||
#define CONFIG_SYS_FSL_OCRAM_SIZE 0x200000 /* 2 MiB */
|
||||
#define CONFIG_SYS_FSL_DDR_BE
|
||||
#define CONFIG_SYS_LS1_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
|
||||
#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_LS1_DDR_BLOCK1_SIZE
|
||||
|
||||
#define CONFIG_SYS_FSL_CCSR_GUR_BE
|
||||
#define CONFIG_SYS_FSL_CCSR_SCFG_BE
|
||||
#define CONFIG_SYS_FSL_IFC_BE
|
||||
#define CONFIG_SYS_FSL_ESDHC_BE
|
||||
#define CONFIG_SYS_FSL_WDOG_BE
|
||||
#define CONFIG_SYS_FSL_DSPI_BE
|
||||
#define CONFIG_SYS_FSL_QSPI_BE
|
||||
|
||||
#define QE_MURAM_SIZE 0x6000UL
|
||||
#define MAX_QE_RISC 1
|
||||
#define QE_NUM_OF_SNUM 28
|
||||
|
||||
#define SRDS_MAX_LANES 4
|
||||
#define CONFIG_SYS_FSL_SRDS_1
|
||||
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
|
||||
|
||||
#define CONFIG_SYS_FSL_SFP_VER_3_2
|
||||
#define CONFIG_SYS_FSL_SNVS_LE
|
||||
#define CONFIG_SYS_FSL_SEC_LE
|
||||
#define CONFIG_SYS_FSL_SFP_BE
|
||||
#define CONFIG_SYS_FSL_SRK_LE
|
||||
#define CONFIG_KEY_REVOCATION
|
||||
|
||||
/* SMMU Defintions */
|
||||
#define SMMU_BASE 0x09000000
|
||||
|
||||
/* Generic Interrupt Controller Definitions */
|
||||
#define GICD_BASE 0x01401000
|
||||
#define GICC_BASE 0x01402000
|
||||
|
||||
#else
|
||||
#error SoC not defined
|
||||
#endif
|
||||
|
||||
#endif /* _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_ */
|
229
arch/arm/include/asm/arch-fsl-layerscape/cpu.h
Normal file
229
arch/arm/include/asm/arch-fsl-layerscape/cpu.h
Normal file
|
@ -0,0 +1,229 @@
|
|||
/*
|
||||
* Copyright 2014-2015, Freescale Semiconductor
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef _FSL_LAYERSCAPE_CPU_H
|
||||
#define _FSL_LAYERSCAPE_CPU_H
|
||||
|
||||
static struct cpu_type cpu_type_list[] = {
|
||||
CPU_TYPE_ENTRY(LS2085, LS2085, 8),
|
||||
CPU_TYPE_ENTRY(LS2080, LS2080, 8),
|
||||
CPU_TYPE_ENTRY(LS2045, LS2045, 4),
|
||||
CPU_TYPE_ENTRY(LS1043, LS1043, 4),
|
||||
};
|
||||
|
||||
#ifndef CONFIG_SYS_DCACHE_OFF
|
||||
|
||||
#define SECTION_SHIFT_L0 39UL
|
||||
#define SECTION_SHIFT_L1 30UL
|
||||
#define SECTION_SHIFT_L2 21UL
|
||||
#define BLOCK_SIZE_L0 0x8000000000
|
||||
#define BLOCK_SIZE_L1 0x40000000
|
||||
#define BLOCK_SIZE_L2 0x200000
|
||||
#define NUM_OF_ENTRY 512
|
||||
#define TCR_EL2_PS_40BIT (2 << 16)
|
||||
|
||||
#define LAYERSCAPE_VA_BITS (40)
|
||||
#define LAYERSCAPE_TCR (TCR_TG0_4K | \
|
||||
TCR_EL2_PS_40BIT | \
|
||||
TCR_SHARED_NON | \
|
||||
TCR_ORGN_NC | \
|
||||
TCR_IRGN_NC | \
|
||||
TCR_T0SZ(LAYERSCAPE_VA_BITS))
|
||||
#define LAYERSCAPE_TCR_FINAL (TCR_TG0_4K | \
|
||||
TCR_EL2_PS_40BIT | \
|
||||
TCR_SHARED_OUTER | \
|
||||
TCR_ORGN_WBWA | \
|
||||
TCR_IRGN_WBWA | \
|
||||
TCR_T0SZ(LAYERSCAPE_VA_BITS))
|
||||
|
||||
#ifdef CONFIG_FSL_LSCH3
|
||||
#define CONFIG_SYS_FSL_CCSR_BASE 0x00000000
|
||||
#define CONFIG_SYS_FSL_CCSR_SIZE 0x10000000
|
||||
#define CONFIG_SYS_FSL_QSPI_BASE1 0x20000000
|
||||
#define CONFIG_SYS_FSL_QSPI_SIZE1 0x10000000
|
||||
#define CONFIG_SYS_FSL_IFC_BASE1 0x30000000
|
||||
#define CONFIG_SYS_FSL_IFC_SIZE1 0x10000000
|
||||
#define CONFIG_SYS_FSL_IFC_SIZE1_1 0x400000
|
||||
#define CONFIG_SYS_FSL_DRAM_BASE1 0x80000000
|
||||
#define CONFIG_SYS_FSL_DRAM_SIZE1 0x80000000
|
||||
#define CONFIG_SYS_FSL_QSPI_BASE2 0x400000000
|
||||
#define CONFIG_SYS_FSL_QSPI_SIZE2 0x100000000
|
||||
#define CONFIG_SYS_FSL_IFC_BASE2 0x500000000
|
||||
#define CONFIG_SYS_FSL_IFC_SIZE2 0x100000000
|
||||
#define CONFIG_SYS_FSL_DCSR_BASE 0x700000000
|
||||
#define CONFIG_SYS_FSL_DCSR_SIZE 0x40000000
|
||||
#define CONFIG_SYS_FSL_MC_BASE 0x80c000000
|
||||
#define CONFIG_SYS_FSL_MC_SIZE 0x4000000
|
||||
#define CONFIG_SYS_FSL_NI_BASE 0x810000000
|
||||
#define CONFIG_SYS_FSL_NI_SIZE 0x8000000
|
||||
#define CONFIG_SYS_FSL_QBMAN_BASE 0x818000000
|
||||
#define CONFIG_SYS_FSL_QBMAN_SIZE 0x8000000
|
||||
#define CONFIG_SYS_FSL_QBMAN_SIZE_1 0x4000000
|
||||
#define CONFIG_SYS_PCIE1_PHYS_SIZE 0x200000000
|
||||
#define CONFIG_SYS_PCIE2_PHYS_SIZE 0x200000000
|
||||
#define CONFIG_SYS_PCIE3_PHYS_SIZE 0x200000000
|
||||
#define CONFIG_SYS_PCIE4_PHYS_SIZE 0x200000000
|
||||
#define CONFIG_SYS_FSL_WRIOP1_BASE 0x4300000000
|
||||
#define CONFIG_SYS_FSL_WRIOP1_SIZE 0x100000000
|
||||
#define CONFIG_SYS_FSL_AIOP1_BASE 0x4b00000000
|
||||
#define CONFIG_SYS_FSL_AIOP1_SIZE 0x100000000
|
||||
#define CONFIG_SYS_FSL_PEBUF_BASE 0x4c00000000
|
||||
#define CONFIG_SYS_FSL_PEBUF_SIZE 0x400000000
|
||||
#define CONFIG_SYS_FSL_DRAM_BASE2 0x8080000000
|
||||
#define CONFIG_SYS_FSL_DRAM_SIZE2 0x7F80000000
|
||||
#elif defined(CONFIG_FSL_LSCH2)
|
||||
#define CONFIG_SYS_FSL_BOOTROM_BASE 0x0
|
||||
#define CONFIG_SYS_FSL_BOOTROM_SIZE 0x1000000
|
||||
#define CONFIG_SYS_FSL_CCSR_BASE 0x1000000
|
||||
#define CONFIG_SYS_FSL_CCSR_SIZE 0xf000000
|
||||
#define CONFIG_SYS_FSL_DCSR_BASE 0x20000000
|
||||
#define CONFIG_SYS_FSL_DCSR_SIZE 0x4000000
|
||||
#define CONFIG_SYS_FSL_QSPI_BASE 0x40000000
|
||||
#define CONFIG_SYS_FSL_QSPI_SIZE 0x20000000
|
||||
#define CONFIG_SYS_FSL_IFC_BASE 0x60000000
|
||||
#define CONFIG_SYS_FSL_IFC_SIZE 0x20000000
|
||||
#define CONFIG_SYS_FSL_DRAM_BASE1 0x80000000
|
||||
#define CONFIG_SYS_FSL_DRAM_SIZE1 0x80000000
|
||||
#define CONFIG_SYS_FSL_QBMAN_BASE 0x500000000
|
||||
#define CONFIG_SYS_FSL_QBMAN_SIZE 0x10000000
|
||||
#define CONFIG_SYS_FSL_DRAM_BASE2 0x880000000
|
||||
#define CONFIG_SYS_FSL_DRAM_SIZE2 0x780000000 /* 30GB */
|
||||
#define CONFIG_SYS_PCIE1_PHYS_SIZE 0x800000000
|
||||
#define CONFIG_SYS_PCIE2_PHYS_SIZE 0x800000000
|
||||
#define CONFIG_SYS_PCIE3_PHYS_SIZE 0x800000000
|
||||
#define CONFIG_SYS_FSL_DRAM_BASE3 0x8800000000
|
||||
#define CONFIG_SYS_FSL_DRAM_SIZE3 0x7800000000 /* 480GB */
|
||||
#endif
|
||||
|
||||
struct sys_mmu_table {
|
||||
u64 virt_addr;
|
||||
u64 phys_addr;
|
||||
u64 size;
|
||||
u64 memory_type;
|
||||
u64 share;
|
||||
};
|
||||
|
||||
struct table_info {
|
||||
u64 *ptr;
|
||||
u64 table_base;
|
||||
u64 entry_size;
|
||||
};
|
||||
|
||||
static const struct sys_mmu_table early_mmu_table[] = {
|
||||
#ifdef CONFIG_FSL_LSCH3
|
||||
{ CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
|
||||
CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
|
||||
{ CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
|
||||
CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PMD_SECT_NON_SHARE },
|
||||
/* For IFC Region #1, only the first 4MB is cache-enabled */
|
||||
{ CONFIG_SYS_FSL_IFC_BASE1, CONFIG_SYS_FSL_IFC_BASE1,
|
||||
CONFIG_SYS_FSL_IFC_SIZE1_1, MT_NORMAL, PMD_SECT_NON_SHARE },
|
||||
{ CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1,
|
||||
CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1,
|
||||
CONFIG_SYS_FSL_IFC_SIZE1 - CONFIG_SYS_FSL_IFC_SIZE1_1,
|
||||
MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
|
||||
{ CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FSL_IFC_BASE1,
|
||||
CONFIG_SYS_FSL_IFC_SIZE1, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
|
||||
{ CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
|
||||
CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL, PMD_SECT_OUTER_SHARE },
|
||||
{ CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
|
||||
CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
|
||||
{ CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
|
||||
CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, PMD_SECT_OUTER_SHARE },
|
||||
#elif defined(CONFIG_FSL_LSCH2)
|
||||
{ CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
|
||||
CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
|
||||
{ CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
|
||||
CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PMD_SECT_NON_SHARE },
|
||||
{ CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
|
||||
CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
|
||||
{ CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE,
|
||||
CONFIG_SYS_FSL_IFC_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
|
||||
{ CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
|
||||
CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL, PMD_SECT_OUTER_SHARE },
|
||||
{ CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
|
||||
CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, PMD_SECT_OUTER_SHARE },
|
||||
#endif
|
||||
};
|
||||
|
||||
static const struct sys_mmu_table final_mmu_table[] = {
|
||||
#ifdef CONFIG_FSL_LSCH3
|
||||
{ CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
|
||||
CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
|
||||
{ CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
|
||||
CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PMD_SECT_NON_SHARE },
|
||||
{ CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
|
||||
CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL, PMD_SECT_OUTER_SHARE },
|
||||
{ CONFIG_SYS_FSL_QSPI_BASE2, CONFIG_SYS_FSL_QSPI_BASE2,
|
||||
CONFIG_SYS_FSL_QSPI_SIZE2, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
|
||||
{ CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2,
|
||||
CONFIG_SYS_FSL_IFC_SIZE2, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
|
||||
{ CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
|
||||
CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
|
||||
{ CONFIG_SYS_FSL_MC_BASE, CONFIG_SYS_FSL_MC_BASE,
|
||||
CONFIG_SYS_FSL_MC_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
|
||||
{ CONFIG_SYS_FSL_NI_BASE, CONFIG_SYS_FSL_NI_BASE,
|
||||
CONFIG_SYS_FSL_NI_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
|
||||
/* For QBMAN portal, only the first 64MB is cache-enabled */
|
||||
{ CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE,
|
||||
CONFIG_SYS_FSL_QBMAN_SIZE_1, MT_NORMAL, PMD_SECT_NON_SHARE },
|
||||
{ CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1,
|
||||
CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1,
|
||||
CONFIG_SYS_FSL_QBMAN_SIZE - CONFIG_SYS_FSL_QBMAN_SIZE_1,
|
||||
MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
|
||||
{ CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR,
|
||||
CONFIG_SYS_PCIE1_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
|
||||
{ CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR,
|
||||
CONFIG_SYS_PCIE2_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
|
||||
{ CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR,
|
||||
CONFIG_SYS_PCIE3_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
|
||||
#ifdef CONFIG_LS2085A
|
||||
{ CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_ADDR,
|
||||
CONFIG_SYS_PCIE4_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
|
||||
#endif
|
||||
{ CONFIG_SYS_FSL_WRIOP1_BASE, CONFIG_SYS_FSL_WRIOP1_BASE,
|
||||
CONFIG_SYS_FSL_WRIOP1_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
|
||||
{ CONFIG_SYS_FSL_AIOP1_BASE, CONFIG_SYS_FSL_AIOP1_BASE,
|
||||
CONFIG_SYS_FSL_AIOP1_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
|
||||
{ CONFIG_SYS_FSL_PEBUF_BASE, CONFIG_SYS_FSL_PEBUF_BASE,
|
||||
CONFIG_SYS_FSL_PEBUF_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
|
||||
{ CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
|
||||
CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, PMD_SECT_OUTER_SHARE },
|
||||
#elif defined(CONFIG_FSL_LSCH2)
|
||||
{ CONFIG_SYS_FSL_BOOTROM_BASE, CONFIG_SYS_FSL_BOOTROM_BASE,
|
||||
CONFIG_SYS_FSL_BOOTROM_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
|
||||
{ CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
|
||||
CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
|
||||
{ CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
|
||||
CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PMD_SECT_NON_SHARE },
|
||||
{ CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
|
||||
CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
|
||||
{ CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE,
|
||||
CONFIG_SYS_FSL_QSPI_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
|
||||
{ CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE,
|
||||
CONFIG_SYS_FSL_IFC_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
|
||||
{ CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
|
||||
CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL,
|
||||
PMD_SECT_OUTER_SHARE | PMD_SECT_NS },
|
||||
{ CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE,
|
||||
CONFIG_SYS_FSL_QBMAN_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
|
||||
{ CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
|
||||
CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, PMD_SECT_OUTER_SHARE },
|
||||
{ CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR,
|
||||
CONFIG_SYS_PCIE1_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
|
||||
{ CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR,
|
||||
CONFIG_SYS_PCIE2_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
|
||||
{ CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR,
|
||||
CONFIG_SYS_PCIE3_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
|
||||
{ CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3,
|
||||
CONFIG_SYS_FSL_DRAM_SIZE3, MT_NORMAL, PMD_SECT_OUTER_SHARE },
|
||||
#endif
|
||||
};
|
||||
#endif
|
||||
|
||||
int fsl_qoriq_core_to_cluster(unsigned int core);
|
||||
u32 cpu_mask(void);
|
||||
#endif /* _FSL_LAYERSCAPE_CPU_H */
|
|
@ -4,7 +4,11 @@
|
|||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef _ASM_ARMV8_FSL_LAYERSCAPE_FDT_H_
|
||||
#define _ASM_ARMV8_FSL_LAYERSCAPE_FDT_H_
|
||||
|
||||
void alloc_stream_ids(int start_id, int count, u32 *stream_ids, int max_cnt);
|
||||
void append_mmu_masters(void *blob, const char *smmu_path,
|
||||
const char *master_name, u32 *stream_ids, int count);
|
||||
void fdt_fixup_smmu_pcie(void *blob);
|
||||
#endif /* _ASM_ARMV8_FSL_LAYERSCAPE_FDT_H_ */
|
157
arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h
Normal file
157
arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h
Normal file
|
@ -0,0 +1,157 @@
|
|||
/*
|
||||
* Copyright 2015 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __FSL_SERDES_H__
|
||||
#define __FSL_SERDES_H__
|
||||
|
||||
#include <config.h>
|
||||
|
||||
#if defined(CONFIG_LS2085A)
|
||||
enum srds_prtcl {
|
||||
NONE = 0,
|
||||
PCIE1,
|
||||
PCIE2,
|
||||
PCIE3,
|
||||
PCIE4,
|
||||
SATA1,
|
||||
SATA2,
|
||||
XAUI1,
|
||||
XAUI2,
|
||||
XFI1,
|
||||
XFI2,
|
||||
XFI3,
|
||||
XFI4,
|
||||
XFI5,
|
||||
XFI6,
|
||||
XFI7,
|
||||
XFI8,
|
||||
SGMII1,
|
||||
SGMII2,
|
||||
SGMII3,
|
||||
SGMII4,
|
||||
SGMII5,
|
||||
SGMII6,
|
||||
SGMII7,
|
||||
SGMII8,
|
||||
SGMII9,
|
||||
SGMII10,
|
||||
SGMII11,
|
||||
SGMII12,
|
||||
SGMII13,
|
||||
SGMII14,
|
||||
SGMII15,
|
||||
SGMII16,
|
||||
QSGMII_A, /* A indicates MACs 1-4 */
|
||||
QSGMII_B, /* B indicates MACs 5-8 */
|
||||
QSGMII_C, /* C indicates MACs 9-12 */
|
||||
QSGMII_D, /* D indicates MACs 12-16 */
|
||||
SERDES_PRCTL_COUNT
|
||||
};
|
||||
|
||||
enum srds {
|
||||
FSL_SRDS_1 = 0,
|
||||
FSL_SRDS_2 = 1,
|
||||
};
|
||||
#elif defined(CONFIG_LS1043A)
|
||||
enum srds_prtcl {
|
||||
NONE = 0,
|
||||
PCIE1,
|
||||
PCIE2,
|
||||
PCIE3,
|
||||
PCIE4,
|
||||
SATA1,
|
||||
SATA2,
|
||||
SRIO1,
|
||||
SRIO2,
|
||||
SGMII_FM1_DTSEC1,
|
||||
SGMII_FM1_DTSEC2,
|
||||
SGMII_FM1_DTSEC3,
|
||||
SGMII_FM1_DTSEC4,
|
||||
SGMII_FM1_DTSEC5,
|
||||
SGMII_FM1_DTSEC6,
|
||||
SGMII_FM1_DTSEC9,
|
||||
SGMII_FM1_DTSEC10,
|
||||
SGMII_FM2_DTSEC1,
|
||||
SGMII_FM2_DTSEC2,
|
||||
SGMII_FM2_DTSEC3,
|
||||
SGMII_FM2_DTSEC4,
|
||||
SGMII_FM2_DTSEC5,
|
||||
SGMII_FM2_DTSEC6,
|
||||
SGMII_FM2_DTSEC9,
|
||||
SGMII_FM2_DTSEC10,
|
||||
SGMII_TSEC1,
|
||||
SGMII_TSEC2,
|
||||
SGMII_TSEC3,
|
||||
SGMII_TSEC4,
|
||||
XAUI_FM1,
|
||||
XAUI_FM2,
|
||||
AURORA,
|
||||
CPRI1,
|
||||
CPRI2,
|
||||
CPRI3,
|
||||
CPRI4,
|
||||
CPRI5,
|
||||
CPRI6,
|
||||
CPRI7,
|
||||
CPRI8,
|
||||
XAUI_FM1_MAC9,
|
||||
XAUI_FM1_MAC10,
|
||||
XAUI_FM2_MAC9,
|
||||
XAUI_FM2_MAC10,
|
||||
HIGIG_FM1_MAC9,
|
||||
HIGIG_FM1_MAC10,
|
||||
HIGIG_FM2_MAC9,
|
||||
HIGIG_FM2_MAC10,
|
||||
QSGMII_FM1_A, /* A indicates MACs 1,2,5,6 */
|
||||
QSGMII_FM1_B, /* B indicates MACs 5,6,9,10 */
|
||||
QSGMII_FM2_A,
|
||||
QSGMII_FM2_B,
|
||||
XFI_FM1_MAC1,
|
||||
XFI_FM1_MAC2,
|
||||
XFI_FM1_MAC9,
|
||||
XFI_FM1_MAC10,
|
||||
XFI_FM2_MAC9,
|
||||
XFI_FM2_MAC10,
|
||||
INTERLAKEN,
|
||||
QSGMII_SW1_A, /* Indicates ports on L2 Switch */
|
||||
QSGMII_SW1_B,
|
||||
SGMII_2500_FM1_DTSEC1,
|
||||
SGMII_2500_FM1_DTSEC2,
|
||||
SGMII_2500_FM1_DTSEC3,
|
||||
SGMII_2500_FM1_DTSEC4,
|
||||
SGMII_2500_FM1_DTSEC5,
|
||||
SGMII_2500_FM1_DTSEC6,
|
||||
SGMII_2500_FM1_DTSEC9,
|
||||
SGMII_2500_FM1_DTSEC10,
|
||||
SGMII_2500_FM2_DTSEC1,
|
||||
SGMII_2500_FM2_DTSEC2,
|
||||
SGMII_2500_FM2_DTSEC3,
|
||||
SGMII_2500_FM2_DTSEC4,
|
||||
SGMII_2500_FM2_DTSEC5,
|
||||
SGMII_2500_FM2_DTSEC6,
|
||||
SGMII_2500_FM2_DTSEC9,
|
||||
SGMII_2500_FM2_DTSEC10,
|
||||
SERDES_PRCTL_COUNT
|
||||
};
|
||||
|
||||
enum srds {
|
||||
FSL_SRDS_1 = 0,
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
int is_serdes_configured(enum srds_prtcl device);
|
||||
void fsl_serdes_init(void);
|
||||
int serdes_get_first_lane(u32 sd, enum srds_prtcl device);
|
||||
enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane);
|
||||
int is_serdes_prtcl_valid(int serdes, u32 prtcl);
|
||||
|
||||
#ifdef CONFIG_LS1043A
|
||||
const char *serdes_clock_to_string(u32 clock);
|
||||
int get_serdes_protocol(void);
|
||||
#endif
|
||||
|
||||
#endif /* __FSL_SERDES_H__ */
|
555
arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
Normal file
555
arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
Normal file
|
@ -0,0 +1,555 @@
|
|||
/*
|
||||
* Copyright 2013-2015 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __ARCH_FSL_LSCH2_IMMAP_H__
|
||||
#define __ARCH_FSL_LSCH2_IMMAP_H__
|
||||
|
||||
#include <fsl_immap.h>
|
||||
|
||||
#define CONFIG_SYS_IMMR 0x01000000
|
||||
#define CONFIG_SYS_DCSRBAR 0x20000000
|
||||
#define CONFIG_SYS_DCSR_DCFG_ADDR (CONFIG_SYS_DCSRBAR + 0x00220000)
|
||||
|
||||
#define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000)
|
||||
#define CONFIG_SYS_CCI400_ADDR (CONFIG_SYS_IMMR + 0x00180000)
|
||||
#define CONFIG_SYS_GIC400_ADDR (CONFIG_SYS_IMMR + 0x00400000)
|
||||
#define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x00530000)
|
||||
#define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x00560000)
|
||||
#define CONFIG_SYS_FSL_CSU_ADDR (CONFIG_SYS_IMMR + 0x00510000)
|
||||
#define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00ee0000)
|
||||
#define CONFIG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00ee00b0)
|
||||
#define CONFIG_SYS_FSL_SCFG_ADDR (CONFIG_SYS_IMMR + 0x00570000)
|
||||
#define CONFIG_SYS_FSL_FMAN_ADDR (CONFIG_SYS_IMMR + 0x00a00000)
|
||||
#define CONFIG_SYS_FSL_SERDES_ADDR (CONFIG_SYS_IMMR + 0x00ea0000)
|
||||
#define CONFIG_SYS_FSL_DCFG_ADDR (CONFIG_SYS_IMMR + 0x00ee0000)
|
||||
#define CONFIG_SYS_FSL_CLK_ADDR (CONFIG_SYS_IMMR + 0x00ee1000)
|
||||
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011c0500)
|
||||
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011c0600)
|
||||
#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_IMMR + 0x011d0500)
|
||||
#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_IMMR + 0x011d0600)
|
||||
#define CONFIG_SYS_FSL_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x01f00000)
|
||||
#define CONFIG_SYS_FSL_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02000000)
|
||||
#define CONFIG_SYS_FSL_XHCI_USB3_ADDR (CONFIG_SYS_IMMR + 0x02100000)
|
||||
#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000)
|
||||
#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000)
|
||||
#define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_IMMR + 0x2600000)
|
||||
#define CONFIG_SYS_FSL_SEC_ADDR (CONFIG_SYS_IMMR + 0x700000)
|
||||
#define CONFIG_SYS_FSL_JR0_ADDR (CONFIG_SYS_IMMR + 0x710000)
|
||||
#define CONFIG_SYS_SNVS_ADDR (CONFIG_SYS_IMMR + 0xe90000)
|
||||
#define CONFIG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0xe80200)
|
||||
|
||||
#define CONFIG_SYS_FSL_TIMER_ADDR 0x02b00000
|
||||
|
||||
#define I2C1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01180000)
|
||||
#define I2C2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01190000)
|
||||
#define I2C3_BASE_ADDR (CONFIG_SYS_IMMR + 0x011a0000)
|
||||
#define I2C4_BASE_ADDR (CONFIG_SYS_IMMR + 0x011b0000)
|
||||
|
||||
#define WDOG1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01ad0000)
|
||||
|
||||
#define QSPI0_BASE_ADDR (CONFIG_SYS_IMMR + 0x00550000)
|
||||
#define DSPI1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01100000)
|
||||
|
||||
#define LPUART_BASE (CONFIG_SYS_IMMR + 0x01950000)
|
||||
|
||||
#define AHCI_BASE_ADDR (CONFIG_SYS_IMMR + 0x02200000)
|
||||
|
||||
#define CONFIG_SYS_PCIE1_PHYS_ADDR 0x4000000000ULL
|
||||
#define CONFIG_SYS_PCIE2_PHYS_ADDR 0x4800000000ULL
|
||||
#define CONFIG_SYS_PCIE3_PHYS_ADDR 0x5000000000ULL
|
||||
|
||||
/* TZ Address Space Controller Definitions */
|
||||
#define TZASC1_BASE 0x01100000 /* as per CCSR map. */
|
||||
#define TZASC2_BASE 0x01110000 /* as per CCSR map. */
|
||||
#define TZASC3_BASE 0x01120000 /* as per CCSR map. */
|
||||
#define TZASC4_BASE 0x01130000 /* as per CCSR map. */
|
||||
#define TZASC_BUILD_CONFIG_REG(x) ((TZASC1_BASE + (x * 0x10000)))
|
||||
#define TZASC_ACTION_REG(x) ((TZASC1_BASE + (x * 0x10000)) + 0x004)
|
||||
#define TZASC_GATE_KEEPER(x) ((TZASC1_BASE + (x * 0x10000)) + 0x008)
|
||||
#define TZASC_REGION_BASE_LOW_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x100)
|
||||
#define TZASC_REGION_BASE_HIGH_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x104)
|
||||
#define TZASC_REGION_TOP_LOW_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x108)
|
||||
#define TZASC_REGION_TOP_HIGH_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x10C)
|
||||
#define TZASC_REGION_ATTRIBUTES_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x110)
|
||||
#define TZASC_REGION_ID_ACCESS_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x114)
|
||||
|
||||
#define TP_ITYP_AV 0x00000001 /* Initiator available */
|
||||
#define TP_ITYP_TYPE(x) (((x) & 0x6) >> 1) /* Initiator Type */
|
||||
#define TP_ITYP_TYPE_ARM 0x0
|
||||
#define TP_ITYP_TYPE_PPC 0x1 /* PowerPC */
|
||||
#define TP_ITYP_TYPE_OTHER 0x2 /* StarCore DSP */
|
||||
#define TP_ITYP_TYPE_HA 0x3 /* HW Accelerator */
|
||||
#define TP_ITYP_THDS(x) (((x) & 0x18) >> 3) /* # threads */
|
||||
#define TP_ITYP_VER(x) (((x) & 0xe0) >> 5) /* Initiator Version */
|
||||
#define TY_ITYP_VER_A7 0x1
|
||||
#define TY_ITYP_VER_A53 0x2
|
||||
#define TY_ITYP_VER_A57 0x3
|
||||
|
||||
#define TP_CLUSTER_EOC 0xc0000000 /* end of clusters */
|
||||
#define TP_CLUSTER_INIT_MASK 0x0000003f /* initiator mask */
|
||||
#define TP_INIT_PER_CLUSTER 4
|
||||
|
||||
/*
|
||||
* Define default values for some CCSR macros to make header files cleaner*
|
||||
*
|
||||
* To completely disable CCSR relocation in a board header file, define
|
||||
* CONFIG_SYS_CCSR_DO_NOT_RELOCATE. This will force CONFIG_SYS_CCSRBAR_PHYS
|
||||
* to a value that is the same as CONFIG_SYS_CCSRBAR.
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_SYS_CCSRBAR_PHYS
|
||||
#error "Do not define CONFIG_SYS_CCSRBAR_PHYS directly. Use \
|
||||
CONFIG_SYS_CCSRBAR_PHYS_LOW and/or CONFIG_SYS_CCSRBAR_PHYS_HIGH instead."
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SYS_CCSR_DO_NOT_RELOCATE
|
||||
#undef CONFIG_SYS_CCSRBAR_PHYS_HIGH
|
||||
#undef CONFIG_SYS_CCSRBAR_PHYS_LOW
|
||||
#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_SYS_CCSRBAR
|
||||
#define CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_SYS_CCSRBAR_PHYS_HIGH
|
||||
#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_SYS_CCSRBAR_PHYS_LOW
|
||||
#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR_DEFAULT
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_CCSRBAR_PHYS ((CONFIG_SYS_CCSRBAR_PHYS_HIGH * 1ull) << 32 | \
|
||||
CONFIG_SYS_CCSRBAR_PHYS_LOW)
|
||||
|
||||
struct sys_info {
|
||||
unsigned long freq_processor[CONFIG_MAX_CPUS];
|
||||
unsigned long freq_systembus;
|
||||
unsigned long freq_ddrbus;
|
||||
unsigned long freq_localbus;
|
||||
unsigned long freq_sdhc;
|
||||
#ifdef CONFIG_SYS_DPAA_FMAN
|
||||
unsigned long freq_fman[CONFIG_SYS_NUM_FMAN];
|
||||
#endif
|
||||
unsigned long freq_qman;
|
||||
};
|
||||
|
||||
#define CONFIG_SYS_FSL_FM1_OFFSET 0xa00000
|
||||
#define CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET 0xa88000
|
||||
#define CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET 0xa89000
|
||||
#define CONFIG_SYS_FSL_FM1_RX2_1G_OFFSET 0xa8a000
|
||||
#define CONFIG_SYS_FSL_FM1_RX3_1G_OFFSET 0xa8b000
|
||||
#define CONFIG_SYS_FSL_FM1_RX4_1G_OFFSET 0xa8c000
|
||||
#define CONFIG_SYS_FSL_FM1_RX5_1G_OFFSET 0xa8d000
|
||||
|
||||
#define CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET 0xae0000
|
||||
#define CONFIG_SYS_FSL_FM1_ADDR \
|
||||
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_OFFSET)
|
||||
#define CONFIG_SYS_FSL_FM1_DTSEC1_ADDR \
|
||||
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET)
|
||||
|
||||
/* Device Configuration and Pin Control */
|
||||
struct ccsr_gur {
|
||||
u32 porsr1; /* POR status 1 */
|
||||
#define FSL_CHASSIS2_CCSR_PORSR1_RCW_MASK 0xFF800000
|
||||
u32 porsr2; /* POR status 2 */
|
||||
u8 res_008[0x20-0x8];
|
||||
u32 gpporcr1; /* General-purpose POR configuration */
|
||||
u32 gpporcr2;
|
||||
#define FSL_CHASSIS2_DCFG_FUSESR_VID_SHIFT 25
|
||||
#define FSL_CHASSIS2_DCFG_FUSESR_VID_MASK 0x1F
|
||||
#define FSL_CHASSIS2_DCFG_FUSESR_ALTVID_SHIFT 20
|
||||
#define FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK 0x1F
|
||||
u32 dcfg_fusesr; /* Fuse status register */
|
||||
u8 res_02c[0x70-0x2c];
|
||||
u32 devdisr; /* Device disable control */
|
||||
#define FSL_CHASSIS2_DEVDISR2_DTSEC1_1 0x80000000
|
||||
#define FSL_CHASSIS2_DEVDISR2_DTSEC1_2 0x40000000
|
||||
#define FSL_CHASSIS2_DEVDISR2_DTSEC1_3 0x20000000
|
||||
#define FSL_CHASSIS2_DEVDISR2_DTSEC1_4 0x10000000
|
||||
#define FSL_CHASSIS2_DEVDISR2_DTSEC1_5 0x08000000
|
||||
#define FSL_CHASSIS2_DEVDISR2_DTSEC1_6 0x04000000
|
||||
#define FSL_CHASSIS2_DEVDISR2_DTSEC1_9 0x00800000
|
||||
#define FSL_CHASSIS2_DEVDISR2_DTSEC1_10 0x00400000
|
||||
#define FSL_CHASSIS2_DEVDISR2_10GEC1_1 0x00800000
|
||||
#define FSL_CHASSIS2_DEVDISR2_10GEC1_2 0x00400000
|
||||
#define FSL_CHASSIS2_DEVDISR2_10GEC1_3 0x80000000
|
||||
#define FSL_CHASSIS2_DEVDISR2_10GEC1_4 0x40000000
|
||||
u32 devdisr2; /* Device disable control 2 */
|
||||
u32 devdisr3; /* Device disable control 3 */
|
||||
u32 devdisr4; /* Device disable control 4 */
|
||||
u32 devdisr5; /* Device disable control 5 */
|
||||
u32 devdisr6; /* Device disable control 6 */
|
||||
u32 devdisr7; /* Device disable control 7 */
|
||||
u8 res_08c[0x94-0x8c];
|
||||
u32 coredisru; /* uppper portion for support of 64 cores */
|
||||
u32 coredisrl; /* lower portion for support of 64 cores */
|
||||
u8 res_09c[0xa0-0x9c];
|
||||
u32 pvr; /* Processor version */
|
||||
u32 svr; /* System version */
|
||||
u32 mvr; /* Manufacturing version */
|
||||
u8 res_0ac[0xb0-0xac];
|
||||
u32 rstcr; /* Reset control */
|
||||
u32 rstrqpblsr; /* Reset request preboot loader status */
|
||||
u8 res_0b8[0xc0-0xb8];
|
||||
u32 rstrqmr1; /* Reset request mask */
|
||||
u8 res_0c4[0xc8-0xc4];
|
||||
u32 rstrqsr1; /* Reset request status */
|
||||
u8 res_0cc[0xd4-0xcc];
|
||||
u32 rstrqwdtmrl; /* Reset request WDT mask */
|
||||
u8 res_0d8[0xdc-0xd8];
|
||||
u32 rstrqwdtsrl; /* Reset request WDT status */
|
||||
u8 res_0e0[0xe4-0xe0];
|
||||
u32 brrl; /* Boot release */
|
||||
u8 res_0e8[0x100-0xe8];
|
||||
u32 rcwsr[16]; /* Reset control word status */
|
||||
#define FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT 25
|
||||
#define FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK 0x1f
|
||||
#define FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_SHIFT 16
|
||||
#define FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK 0x3f
|
||||
#define FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK 0xffff0000
|
||||
#define FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT 16
|
||||
u8 res_140[0x200-0x140];
|
||||
u32 scratchrw[4]; /* Scratch Read/Write */
|
||||
u8 res_210[0x300-0x210];
|
||||
u32 scratchw1r[4]; /* Scratch Read (Write once) */
|
||||
u8 res_310[0x400-0x310];
|
||||
u32 crstsr[12];
|
||||
u8 res_430[0x500-0x430];
|
||||
|
||||
/* PCI Express n Logical I/O Device Number register */
|
||||
u32 dcfg_ccsr_pex1liodnr;
|
||||
u32 dcfg_ccsr_pex2liodnr;
|
||||
u32 dcfg_ccsr_pex3liodnr;
|
||||
u32 dcfg_ccsr_pex4liodnr;
|
||||
/* RIO n Logical I/O Device Number register */
|
||||
u32 dcfg_ccsr_rio1liodnr;
|
||||
u32 dcfg_ccsr_rio2liodnr;
|
||||
u32 dcfg_ccsr_rio3liodnr;
|
||||
u32 dcfg_ccsr_rio4liodnr;
|
||||
/* USB Logical I/O Device Number register */
|
||||
u32 dcfg_ccsr_usb1liodnr;
|
||||
u32 dcfg_ccsr_usb2liodnr;
|
||||
u32 dcfg_ccsr_usb3liodnr;
|
||||
u32 dcfg_ccsr_usb4liodnr;
|
||||
/* SD/MMC Logical I/O Device Number register */
|
||||
u32 dcfg_ccsr_sdmmc1liodnr;
|
||||
u32 dcfg_ccsr_sdmmc2liodnr;
|
||||
u32 dcfg_ccsr_sdmmc3liodnr;
|
||||
u32 dcfg_ccsr_sdmmc4liodnr;
|
||||
/* RIO Message Unit Logical I/O Device Number register */
|
||||
u32 dcfg_ccsr_riomaintliodnr;
|
||||
|
||||
u8 res_544[0x550-0x544];
|
||||
u32 sataliodnr[4];
|
||||
u8 res_560[0x570-0x560];
|
||||
|
||||
u32 dcfg_ccsr_misc1liodnr;
|
||||
u32 dcfg_ccsr_misc2liodnr;
|
||||
u32 dcfg_ccsr_misc3liodnr;
|
||||
u32 dcfg_ccsr_misc4liodnr;
|
||||
u32 dcfg_ccsr_dma1liodnr;
|
||||
u32 dcfg_ccsr_dma2liodnr;
|
||||
u32 dcfg_ccsr_dma3liodnr;
|
||||
u32 dcfg_ccsr_dma4liodnr;
|
||||
u32 dcfg_ccsr_spare1liodnr;
|
||||
u32 dcfg_ccsr_spare2liodnr;
|
||||
u32 dcfg_ccsr_spare3liodnr;
|
||||
u32 dcfg_ccsr_spare4liodnr;
|
||||
u8 res_5a0[0x600-0x5a0];
|
||||
u32 dcfg_ccsr_pblsr;
|
||||
|
||||
u32 pamubypenr;
|
||||
u32 dmacr1;
|
||||
|
||||
u8 res_60c[0x610-0x60c];
|
||||
u32 dcfg_ccsr_gensr1;
|
||||
u32 dcfg_ccsr_gensr2;
|
||||
u32 dcfg_ccsr_gensr3;
|
||||
u32 dcfg_ccsr_gensr4;
|
||||
u32 dcfg_ccsr_gencr1;
|
||||
u32 dcfg_ccsr_gencr2;
|
||||
u32 dcfg_ccsr_gencr3;
|
||||
u32 dcfg_ccsr_gencr4;
|
||||
u32 dcfg_ccsr_gencr5;
|
||||
u32 dcfg_ccsr_gencr6;
|
||||
u32 dcfg_ccsr_gencr7;
|
||||
u8 res_63c[0x658-0x63c];
|
||||
u32 dcfg_ccsr_cgensr1;
|
||||
u32 dcfg_ccsr_cgensr0;
|
||||
u8 res_660[0x678-0x660];
|
||||
u32 dcfg_ccsr_cgencr1;
|
||||
|
||||
u32 dcfg_ccsr_cgencr0;
|
||||
u8 res_680[0x700-0x680];
|
||||
u32 dcfg_ccsr_sriopstecr;
|
||||
u32 dcfg_ccsr_dcsrcr;
|
||||
|
||||
u8 res_708[0x740-0x708]; /* add more registers when needed */
|
||||
u32 tp_ityp[64]; /* Topology Initiator Type Register */
|
||||
struct {
|
||||
u32 upper;
|
||||
u32 lower;
|
||||
} tp_cluster[16];
|
||||
u8 res_8c0[0xa00-0x8c0]; /* add more registers when needed */
|
||||
u32 dcfg_ccsr_qmbm_warmrst;
|
||||
u8 res_a04[0xa20-0xa04]; /* add more registers when needed */
|
||||
u32 dcfg_ccsr_reserved0;
|
||||
u32 dcfg_ccsr_reserved1;
|
||||
};
|
||||
|
||||
#define SCFG_QSPI_CLKSEL 0x40100000
|
||||
#define SCFG_USBDRVVBUS_SELCR_USB1 0x00000000
|
||||
#define SCFG_USBDRVVBUS_SELCR_USB2 0x00000001
|
||||
#define SCFG_USBDRVVBUS_SELCR_USB3 0x00000002
|
||||
#define SCFG_USBPWRFAULT_INACTIVE 0x00000000
|
||||
#define SCFG_USBPWRFAULT_SHARED 0x00000001
|
||||
#define SCFG_USBPWRFAULT_DEDICATED 0x00000002
|
||||
#define SCFG_USBPWRFAULT_USB3_SHIFT 4
|
||||
#define SCFG_USBPWRFAULT_USB2_SHIFT 2
|
||||
#define SCFG_USBPWRFAULT_USB1_SHIFT 0
|
||||
|
||||
#define SCFG_SNPCNFGCR_SECRDSNP 0x80000000
|
||||
#define SCFG_SNPCNFGCR_SECWRSNP 0x40000000
|
||||
|
||||
/* Supplemental Configuration Unit */
|
||||
struct ccsr_scfg {
|
||||
u8 res_000[0x100-0x000];
|
||||
u32 usb2_icid;
|
||||
u32 usb3_icid;
|
||||
u8 res_108[0x114-0x108];
|
||||
u32 dma_icid;
|
||||
u32 sata_icid;
|
||||
u32 usb1_icid;
|
||||
u32 qe_icid;
|
||||
u32 sdhc_icid;
|
||||
u32 edma_icid;
|
||||
u32 etr_icid;
|
||||
u32 core_sft_rst[4];
|
||||
u8 res_140[0x158-0x140];
|
||||
u32 altcbar;
|
||||
u32 qspi_cfg;
|
||||
u8 res_160[0x180-0x160];
|
||||
u32 dmamcr;
|
||||
u8 res_184[0x18c-0x184];
|
||||
u32 debug_icid;
|
||||
u8 res_190[0x1a4-0x190];
|
||||
u32 snpcnfgcr;
|
||||
u8 res_1a8[0x1ac-0x1a8];
|
||||
u32 intpcr;
|
||||
u8 res_1b0[0x204-0x1b0];
|
||||
u32 coresrencr;
|
||||
u8 res_208[0x220-0x208];
|
||||
u32 rvbar0_0;
|
||||
u32 rvbar0_1;
|
||||
u32 rvbar1_0;
|
||||
u32 rvbar1_1;
|
||||
u32 rvbar2_0;
|
||||
u32 rvbar2_1;
|
||||
u32 rvbar3_0;
|
||||
u32 rvbar3_1;
|
||||
u32 lpmcsr;
|
||||
u8 res_244[0x400-0x244];
|
||||
u32 qspidqscr;
|
||||
u32 ecgtxcmcr;
|
||||
u32 sdhciovselcr;
|
||||
u32 rcwpmuxcr0;
|
||||
u32 usbdrvvbus_selcr;
|
||||
u32 usbpwrfault_selcr;
|
||||
u32 usb_refclk_selcr1;
|
||||
u32 usb_refclk_selcr2;
|
||||
u32 usb_refclk_selcr3;
|
||||
u8 res_424[0x600-0x424];
|
||||
u32 scratchrw[4];
|
||||
u8 res_610[0x680-0x610];
|
||||
u32 corebcr;
|
||||
u8 res_684[0x1000-0x684];
|
||||
u32 pex1msiir;
|
||||
u32 pex1msir;
|
||||
u8 res_1008[0x2000-0x1008];
|
||||
u32 pex2;
|
||||
u32 pex2msir;
|
||||
u8 res_2008[0x3000-0x2008];
|
||||
u32 pex3msiir;
|
||||
u32 pex3msir;
|
||||
};
|
||||
|
||||
/* Clocking */
|
||||
struct ccsr_clk {
|
||||
struct {
|
||||
u32 clkcncsr; /* core cluster n clock control status */
|
||||
u8 res_004[0x0c];
|
||||
u32 clkcghwacsr; /* Clock generator n hardware accelerator */
|
||||
u8 res_014[0x0c];
|
||||
} clkcsr[4];
|
||||
u8 res_040[0x780]; /* 0x100 */
|
||||
struct {
|
||||
u32 pllcngsr;
|
||||
u8 res_804[0x1c];
|
||||
} pllcgsr[2];
|
||||
u8 res_840[0x1c0];
|
||||
u32 clkpcsr; /* 0xa00 Platform clock domain control/status */
|
||||
u8 res_a04[0x1fc];
|
||||
u32 pllpgsr; /* 0xc00 Platform PLL General Status */
|
||||
u8 res_c04[0x1c];
|
||||
u32 plldgsr; /* 0xc20 DDR PLL General Status */
|
||||
u8 res_c24[0x3dc];
|
||||
};
|
||||
|
||||
/* System Counter */
|
||||
struct sctr_regs {
|
||||
u32 cntcr;
|
||||
u32 cntsr;
|
||||
u32 cntcv1;
|
||||
u32 cntcv2;
|
||||
u32 resv1[4];
|
||||
u32 cntfid0;
|
||||
u32 cntfid1;
|
||||
u32 resv2[1002];
|
||||
u32 counterid[12];
|
||||
};
|
||||
|
||||
#define SRDS_MAX_LANES 4
|
||||
struct ccsr_serdes {
|
||||
struct {
|
||||
u32 rstctl; /* Reset Control Register */
|
||||
#define SRDS_RSTCTL_RST 0x80000000
|
||||
#define SRDS_RSTCTL_RSTDONE 0x40000000
|
||||
#define SRDS_RSTCTL_RSTERR 0x20000000
|
||||
#define SRDS_RSTCTL_SWRST 0x10000000
|
||||
#define SRDS_RSTCTL_SDEN 0x00000020
|
||||
#define SRDS_RSTCTL_SDRST_B 0x00000040
|
||||
#define SRDS_RSTCTL_PLLRST_B 0x00000080
|
||||
u32 pllcr0; /* PLL Control Register 0 */
|
||||
#define SRDS_PLLCR0_POFF 0x80000000
|
||||
#define SRDS_PLLCR0_RFCK_SEL_MASK 0x70000000
|
||||
#define SRDS_PLLCR0_RFCK_SEL_100 0x00000000
|
||||
#define SRDS_PLLCR0_RFCK_SEL_125 0x10000000
|
||||
#define SRDS_PLLCR0_RFCK_SEL_156_25 0x20000000
|
||||
#define SRDS_PLLCR0_RFCK_SEL_150 0x30000000
|
||||
#define SRDS_PLLCR0_RFCK_SEL_161_13 0x40000000
|
||||
#define SRDS_PLLCR0_RFCK_SEL_122_88 0x50000000
|
||||
#define SRDS_PLLCR0_PLL_LCK 0x00800000
|
||||
#define SRDS_PLLCR0_FRATE_SEL_MASK 0x000f0000
|
||||
#define SRDS_PLLCR0_FRATE_SEL_5 0x00000000
|
||||
#define SRDS_PLLCR0_FRATE_SEL_3_75 0x00050000
|
||||
#define SRDS_PLLCR0_FRATE_SEL_5_15 0x00060000
|
||||
#define SRDS_PLLCR0_FRATE_SEL_4 0x00070000
|
||||
#define SRDS_PLLCR0_FRATE_SEL_3_12 0x00090000
|
||||
#define SRDS_PLLCR0_FRATE_SEL_3 0x000a0000
|
||||
u32 pllcr1; /* PLL Control Register 1 */
|
||||
#define SRDS_PLLCR1_PLL_BWSEL 0x08000000
|
||||
u32 res_0c; /* 0x00c */
|
||||
u32 pllcr3;
|
||||
u32 pllcr4;
|
||||
u8 res_18[0x20-0x18];
|
||||
} bank[2];
|
||||
u8 res_40[0x90-0x40];
|
||||
u32 srdstcalcr; /* 0x90 TX Calibration Control */
|
||||
u8 res_94[0xa0-0x94];
|
||||
u32 srdsrcalcr; /* 0xa0 RX Calibration Control */
|
||||
u8 res_a4[0xb0-0xa4];
|
||||
u32 srdsgr0; /* 0xb0 General Register 0 */
|
||||
u8 res_b4[0xe0-0xb4];
|
||||
u32 srdspccr0; /* 0xe0 Protocol Converter Config 0 */
|
||||
u32 srdspccr1; /* 0xe4 Protocol Converter Config 1 */
|
||||
u32 srdspccr2; /* 0xe8 Protocol Converter Config 2 */
|
||||
u32 srdspccr3; /* 0xec Protocol Converter Config 3 */
|
||||
u32 srdspccr4; /* 0xf0 Protocol Converter Config 4 */
|
||||
u8 res_f4[0x100-0xf4];
|
||||
struct {
|
||||
u32 lnpssr; /* 0x100, 0x120, ..., 0x1e0 */
|
||||
u8 res_104[0x120-0x104];
|
||||
} srdslnpssr[4];
|
||||
u8 res_180[0x300-0x180];
|
||||
u32 srdspexeqcr;
|
||||
u32 srdspexeqpcr[11];
|
||||
u8 res_330[0x400-0x330];
|
||||
u32 srdspexapcr;
|
||||
u8 res_404[0x440-0x404];
|
||||
u32 srdspexbpcr;
|
||||
u8 res_444[0x800-0x444];
|
||||
struct {
|
||||
u32 gcr0; /* 0x800 General Control Register 0 */
|
||||
u32 gcr1; /* 0x804 General Control Register 1 */
|
||||
u32 gcr2; /* 0x808 General Control Register 2 */
|
||||
u32 sscr0;
|
||||
u32 recr0; /* 0x810 Receive Equalization Control */
|
||||
u32 recr1;
|
||||
u32 tecr0; /* 0x818 Transmit Equalization Control */
|
||||
u32 sscr1;
|
||||
u32 ttlcr0; /* 0x820 Transition Tracking Loop Ctrl 0 */
|
||||
u8 res_824[0x83c-0x824];
|
||||
u32 tcsr3;
|
||||
} lane[4]; /* Lane A, B, C, D, E, F, G, H */
|
||||
u8 res_a00[0x1000-0xa00]; /* from 0xa00 to 0xfff */
|
||||
};
|
||||
|
||||
#define CCI400_CTRLORD_TERM_BARRIER 0x00000008
|
||||
#define CCI400_CTRLORD_EN_BARRIER 0
|
||||
#define CCI400_SHAORD_NON_SHAREABLE 0x00000002
|
||||
#define CCI400_DVM_MESSAGE_REQ_EN 0x00000002
|
||||
#define CCI400_SNOOP_REQ_EN 0x00000001
|
||||
|
||||
/* CCI-400 registers */
|
||||
struct ccsr_cci400 {
|
||||
u32 ctrl_ord; /* Control Override */
|
||||
u32 spec_ctrl; /* Speculation Control */
|
||||
u32 secure_access; /* Secure Access */
|
||||
u32 status; /* Status */
|
||||
u32 impr_err; /* Imprecise Error */
|
||||
u8 res_14[0x100 - 0x14];
|
||||
u32 pmcr; /* Performance Monitor Control */
|
||||
u8 res_104[0xfd0 - 0x104];
|
||||
u32 pid[8]; /* Peripheral ID */
|
||||
u32 cid[4]; /* Component ID */
|
||||
struct {
|
||||
u32 snoop_ctrl; /* Snoop Control */
|
||||
u32 sha_ord; /* Shareable Override */
|
||||
u8 res_1008[0x1100 - 0x1008];
|
||||
u32 rc_qos_ord; /* read channel QoS Value Override */
|
||||
u32 wc_qos_ord; /* read channel QoS Value Override */
|
||||
u8 res_1108[0x110c - 0x1108];
|
||||
u32 qos_ctrl; /* QoS Control */
|
||||
u32 max_ot; /* Max OT */
|
||||
u8 res_1114[0x1130 - 0x1114];
|
||||
u32 target_lat; /* Target Latency */
|
||||
u32 latency_regu; /* Latency Regulation */
|
||||
u32 qos_range; /* QoS Range */
|
||||
u8 res_113c[0x2000 - 0x113c];
|
||||
} slave[5]; /* Slave Interface */
|
||||
u8 res_6000[0x9004 - 0x6000];
|
||||
u32 cycle_counter; /* Cycle counter */
|
||||
u32 count_ctrl; /* Count Control */
|
||||
u32 overflow_status; /* Overflow Flag Status */
|
||||
u8 res_9010[0xa000 - 0x9010];
|
||||
struct {
|
||||
u32 event_select; /* Event Select */
|
||||
u32 event_count; /* Event Count */
|
||||
u32 counter_ctrl; /* Counter Control */
|
||||
u32 overflow_status; /* Overflow Flag Status */
|
||||
u8 res_a010[0xb000 - 0xa010];
|
||||
} pcounter[4]; /* Performance Counter */
|
||||
u8 res_e004[0x10000 - 0xe004];
|
||||
};
|
||||
|
||||
/* MMU 500 */
|
||||
#define SMMU_SCR0 (SMMU_BASE + 0x0)
|
||||
#define SMMU_SCR1 (SMMU_BASE + 0x4)
|
||||
#define SMMU_SCR2 (SMMU_BASE + 0x8)
|
||||
#define SMMU_SACR (SMMU_BASE + 0x10)
|
||||
#define SMMU_IDR0 (SMMU_BASE + 0x20)
|
||||
#define SMMU_IDR1 (SMMU_BASE + 0x24)
|
||||
|
||||
#define SMMU_NSCR0 (SMMU_BASE + 0x400)
|
||||
#define SMMU_NSCR2 (SMMU_BASE + 0x408)
|
||||
#define SMMU_NSACR (SMMU_BASE + 0x410)
|
||||
|
||||
#define SCR0_CLIENTPD_MASK 0x00000001
|
||||
#define SCR0_USFCFG_MASK 0x00000400
|
||||
|
||||
#endif /* __ARCH_FSL_LSCH2_IMMAP_H__*/
|
|
@ -6,9 +6,109 @@
|
|||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __ARCH_FSL_LSCH3_IMMAP_H
|
||||
#ifndef __ARCH_FSL_LSCH3_IMMAP_H_
|
||||
#define __ARCH_FSL_LSCH3_IMMAP_H_
|
||||
|
||||
#define CONFIG_SYS_IMMR 0x01000000
|
||||
#define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000)
|
||||
#define CONFIG_SYS_FSL_DDR2_ADDR (CONFIG_SYS_IMMR + 0x00090000)
|
||||
#define CONFIG_SYS_FSL_DDR3_ADDR 0x08210000
|
||||
#define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00E00000)
|
||||
#define CONFIG_SYS_FSL_PMU_ADDR (CONFIG_SYS_IMMR + 0x00E30000)
|
||||
#define CONFIG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00E60000)
|
||||
#define CONFIG_SYS_FSL_CH3_CLK_GRPA_ADDR (CONFIG_SYS_IMMR + 0x00300000)
|
||||
#define CONFIG_SYS_FSL_CH3_CLK_GRPB_ADDR (CONFIG_SYS_IMMR + 0x00310000)
|
||||
#define CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR (CONFIG_SYS_IMMR + 0x00370000)
|
||||
#define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x01140000)
|
||||
#define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x01240000)
|
||||
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011C0500)
|
||||
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011C0600)
|
||||
#define CONFIG_SYS_FSL_TIMER_ADDR 0x023d0000
|
||||
#define CONFIG_SYS_FSL_PMU_CLTBENR (CONFIG_SYS_FSL_PMU_ADDR + \
|
||||
0x18A0)
|
||||
|
||||
#define CONFIG_SYS_FSL_WRIOP1_ADDR (CONFIG_SYS_IMMR + 0x7B80000)
|
||||
#define CONFIG_SYS_FSL_WRIOP1_MDIO1 (CONFIG_SYS_FSL_WRIOP1_ADDR + 0x16000)
|
||||
#define CONFIG_SYS_FSL_WRIOP1_MDIO2 (CONFIG_SYS_FSL_WRIOP1_ADDR + 0x17000)
|
||||
#define CONFIG_SYS_FSL_LSCH3_SERDES_ADDR (CONFIG_SYS_IMMR + 0xEA0000)
|
||||
|
||||
/* SP (Cortex-A5) related */
|
||||
#define CONFIG_SYS_FSL_SP_ADDR (CONFIG_SYS_IMMR + 0x00F00000)
|
||||
#define CONFIG_SYS_FSL_SP_VSG_GIC_ADDR (CONFIG_SYS_FSL_SP_ADDR)
|
||||
#define CONFIG_SYS_FSL_SP_VSG_GIC_VIGR1 (CONFIG_SYS_FSL_SP_ADDR)
|
||||
#define CONFIG_SYS_FSL_SP_VSG_GIC_VIGR2 \
|
||||
(CONFIG_SYS_FSL_SP_ADDR + 0x0008)
|
||||
#define CONFIG_SYS_FSL_SP_LOOPBACK_DUART \
|
||||
(CONFIG_SYS_FSL_SP_ADDR + 0x1000)
|
||||
|
||||
#define CONFIG_SYS_FSL_DCSR_DDR_ADDR 0x70012c000ULL
|
||||
#define CONFIG_SYS_FSL_DCSR_DDR2_ADDR 0x70012d000ULL
|
||||
#define CONFIG_SYS_FSL_DCSR_DDR3_ADDR 0x700132000ULL
|
||||
#define CONFIG_SYS_FSL_DCSR_DDR4_ADDR 0x700133000ULL
|
||||
|
||||
#define I2C1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01000000)
|
||||
#define I2C2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01010000)
|
||||
#define I2C3_BASE_ADDR (CONFIG_SYS_IMMR + 0x01020000)
|
||||
#define I2C4_BASE_ADDR (CONFIG_SYS_IMMR + 0x01030000)
|
||||
|
||||
#define CONFIG_SYS_LS2085A_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x02100000)
|
||||
#define CONFIG_SYS_LS2085A_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02110000)
|
||||
|
||||
/* TZ Address Space Controller Definitions */
|
||||
#define TZASC1_BASE 0x01100000 /* as per CCSR map. */
|
||||
#define TZASC2_BASE 0x01110000 /* as per CCSR map. */
|
||||
#define TZASC3_BASE 0x01120000 /* as per CCSR map. */
|
||||
#define TZASC4_BASE 0x01130000 /* as per CCSR map. */
|
||||
#define TZASC_BUILD_CONFIG_REG(x) ((TZASC1_BASE + (x * 0x10000)))
|
||||
#define TZASC_ACTION_REG(x) ((TZASC1_BASE + (x * 0x10000)) + 0x004)
|
||||
#define TZASC_GATE_KEEPER(x) ((TZASC1_BASE + (x * 0x10000)) + 0x008)
|
||||
#define TZASC_REGION_BASE_LOW_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x100)
|
||||
#define TZASC_REGION_BASE_HIGH_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x104)
|
||||
#define TZASC_REGION_TOP_LOW_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x108)
|
||||
#define TZASC_REGION_TOP_HIGH_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x10C)
|
||||
#define TZASC_REGION_ATTRIBUTES_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x110)
|
||||
#define TZASC_REGION_ID_ACCESS_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x114)
|
||||
|
||||
/* PCIe */
|
||||
#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000)
|
||||
#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000)
|
||||
#define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_IMMR + 0x2600000)
|
||||
#define CONFIG_SYS_PCIE4_ADDR (CONFIG_SYS_IMMR + 0x2700000)
|
||||
#define CONFIG_SYS_PCIE1_PHYS_ADDR 0x1000000000ULL
|
||||
#define CONFIG_SYS_PCIE2_PHYS_ADDR 0x1200000000ULL
|
||||
#define CONFIG_SYS_PCIE3_PHYS_ADDR 0x1400000000ULL
|
||||
#define CONFIG_SYS_PCIE4_PHYS_ADDR 0x1600000000ULL
|
||||
|
||||
/* Device Configuration */
|
||||
#define DCFG_BASE 0x01e00000
|
||||
#define DCFG_PORSR1 0x000
|
||||
#define DCFG_PORSR1_RCW_SRC 0xff800000
|
||||
#define DCFG_PORSR1_RCW_SRC_NOR 0x12f00000
|
||||
#define DCFG_RCWSR13 0x130
|
||||
#define DCFG_RCWSR13_DSPI (0 << 8)
|
||||
|
||||
#define DCFG_DCSR_BASE 0X700100000ULL
|
||||
#define DCFG_DCSR_PORCR1 0x000
|
||||
|
||||
/* Supplemental Configuration */
|
||||
#define SCFG_BASE 0x01fc0000
|
||||
#define SCFG_USB3PRM1CR 0x000
|
||||
|
||||
#define TP_ITYP_AV 0x00000001 /* Initiator available */
|
||||
#define TP_ITYP_TYPE(x) (((x) & 0x6) >> 1) /* Initiator Type */
|
||||
#define TP_ITYP_TYPE_ARM 0x0
|
||||
#define TP_ITYP_TYPE_PPC 0x1 /* PowerPC */
|
||||
#define TP_ITYP_TYPE_OTHER 0x2 /* StarCore DSP */
|
||||
#define TP_ITYP_TYPE_HA 0x3 /* HW Accelerator */
|
||||
#define TP_ITYP_THDS(x) (((x) & 0x18) >> 3) /* # threads */
|
||||
#define TP_ITYP_VER(x) (((x) & 0xe0) >> 5) /* Initiator Version */
|
||||
#define TY_ITYP_VER_A7 0x1
|
||||
#define TY_ITYP_VER_A53 0x2
|
||||
#define TY_ITYP_VER_A57 0x3
|
||||
|
||||
#define TP_CLUSTER_EOC 0x80000000 /* end of clusters */
|
||||
#define TP_CLUSTER_INIT_MASK 0x0000003f /* initiator mask */
|
||||
#define TP_INIT_PER_CLUSTER 4
|
||||
/* This is chassis generation 3 */
|
||||
|
||||
struct sys_info {
|
||||
|
@ -109,21 +209,6 @@ struct ccsr_gur {
|
|||
u8 res_858[0x1000-0x858];
|
||||
};
|
||||
|
||||
#define TP_ITYP_AV 0x00000001 /* Initiator available */
|
||||
#define TP_ITYP_TYPE(x) (((x) & 0x6) >> 1) /* Initiator Type */
|
||||
#define TP_ITYP_TYPE_ARM 0x0
|
||||
#define TP_ITYP_TYPE_PPC 0x1 /* PowerPC */
|
||||
#define TP_ITYP_TYPE_OTHER 0x2 /* StarCore DSP */
|
||||
#define TP_ITYP_TYPE_HA 0x3 /* HW Accelerator */
|
||||
#define TP_ITYP_THDS(x) (((x) & 0x18) >> 3) /* # threads */
|
||||
#define TP_ITYP_VER(x) (((x) & 0xe0) >> 5) /* Initiator Version */
|
||||
#define TY_ITYP_VER_A7 0x1
|
||||
#define TY_ITYP_VER_A53 0x2
|
||||
#define TY_ITYP_VER_A57 0x3
|
||||
|
||||
#define TP_CLUSTER_EOC 0x80000000 /* end of clusters */
|
||||
#define TP_CLUSTER_INIT_MASK 0x0000003f /* initiator mask */
|
||||
#define TP_INIT_PER_CLUSTER 4
|
||||
|
||||
struct ccsr_clk_cluster_group {
|
||||
struct {
|
||||
|
@ -180,4 +265,4 @@ struct ccsr_reset {
|
|||
u32 ip_rev1; /* 0xbf8 */
|
||||
u32 ip_rev2; /* 0xbfc */
|
||||
};
|
||||
#endif /* __ARCH_FSL_LSCH3_IMMAP_H */
|
||||
#endif /* __ARCH_FSL_LSCH3_IMMAP_H_ */
|
55
arch/arm/include/asm/arch-fsl-layerscape/imx-regs.h
Normal file
55
arch/arm/include/asm/arch-fsl-layerscape/imx-regs.h
Normal file
|
@ -0,0 +1,55 @@
|
|||
/*
|
||||
* Copyright 2015 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_FSL_LAYERSCAPE_IMX_REGS_H__
|
||||
#define __ASM_ARCH_FSL_LAYERSCAPE_IMX_REGS_H__
|
||||
|
||||
#define I2C_QUIRK_REG /* enable 8-bit driver */
|
||||
|
||||
#ifdef CONFIG_FSL_LPUART
|
||||
#ifdef CONFIG_LPUART_32B_REG
|
||||
struct lpuart_fsl {
|
||||
u32 baud;
|
||||
u32 stat;
|
||||
u32 ctrl;
|
||||
u32 data;
|
||||
u32 match;
|
||||
u32 modir;
|
||||
u32 fifo;
|
||||
u32 water;
|
||||
};
|
||||
#else
|
||||
struct lpuart_fsl {
|
||||
u8 ubdh;
|
||||
u8 ubdl;
|
||||
u8 uc1;
|
||||
u8 uc2;
|
||||
u8 us1;
|
||||
u8 us2;
|
||||
u8 uc3;
|
||||
u8 ud;
|
||||
u8 uma1;
|
||||
u8 uma2;
|
||||
u8 uc4;
|
||||
u8 uc5;
|
||||
u8 ued;
|
||||
u8 umodem;
|
||||
u8 uir;
|
||||
u8 reserved;
|
||||
u8 upfifo;
|
||||
u8 ucfifo;
|
||||
u8 usfifo;
|
||||
u8 utwfifo;
|
||||
u8 utcfifo;
|
||||
u8 urwfifo;
|
||||
u8 urcfifo;
|
||||
u8 rsvd[28];
|
||||
};
|
||||
#endif
|
||||
#endif /* CONFIG_FSL_LPUART */
|
||||
|
||||
#endif /* __ASM_ARCH_FSL_LAYERSCAPE_IMX_REGS_H__ */
|
10
arch/arm/include/asm/arch-fsl-layerscape/mmu.h
Normal file
10
arch/arm/include/asm/arch-fsl-layerscape/mmu.h
Normal file
|
@ -0,0 +1,10 @@
|
|||
/*
|
||||
* Copyright 2015, Freescale Semiconductor
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef _ASM_ARMV8_FSL_LAYERSCAPE_MMU_H_
|
||||
#define _ASM_ARMV8_FSL_LAYERSCAPE_MMU_H_
|
||||
#include <asm/arch-armv8/mmu.h>
|
||||
#endif /* _ASM_ARMV8_FSL_LAYERSCAPE_MMU_H_ */
|
|
@ -1,11 +1,11 @@
|
|||
/*
|
||||
* Copyright 2014, Freescale Semiconductor
|
||||
* Copyright 2014-2015, Freescale Semiconductor
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef _FSL_CH3_MP_H
|
||||
#define _FSL_CH3_MP_H
|
||||
#ifndef _FSL_LAYERSCAPE_MP_H
|
||||
#define _FSL_LAYERSCAPE_MP_H
|
||||
|
||||
/*
|
||||
* Each spin table element is defined as
|
||||
|
@ -29,10 +29,10 @@ extern u64 __spin_table[];
|
|||
extern u64 __real_cntfrq;
|
||||
extern u64 *secondary_boot_code;
|
||||
extern size_t __secondary_boot_code_size;
|
||||
int fsl_lsch3_wake_seconday_cores(void);
|
||||
int fsl_layerscape_wake_seconday_cores(void);
|
||||
void *get_spin_tbl_addr(void);
|
||||
phys_addr_t determine_mp_bootpg(void);
|
||||
void secondary_boot_func(void);
|
||||
int is_core_online(u64 cpu_id);
|
||||
#endif
|
||||
#endif /* _FSL_CH3_MP_H */
|
||||
#endif /* _FSL_LAYERSCAPE_MP_H */
|
158
arch/arm/include/asm/arch-fsl-layerscape/ns_access.h
Normal file
158
arch/arm/include/asm/arch-fsl-layerscape/ns_access.h
Normal file
|
@ -0,0 +1,158 @@
|
|||
/*
|
||||
* Copyright 2015 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __FSL_NS_ACCESS_H_
|
||||
#define __FSL_NS_ACCESS_H_
|
||||
|
||||
enum csu_cslx_ind {
|
||||
CSU_CSLX_PCIE2_IO = 0,
|
||||
CSU_CSLX_PCIE1_IO,
|
||||
CSU_CSLX_MG2TPR_IP,
|
||||
CSU_CSLX_IFC_MEM,
|
||||
CSU_CSLX_OCRAM,
|
||||
CSU_CSLX_GIC,
|
||||
CSU_CSLX_PCIE1,
|
||||
CSU_CSLX_OCRAM2,
|
||||
CSU_CSLX_QSPI_MEM,
|
||||
CSU_CSLX_PCIE2,
|
||||
CSU_CSLX_SATA,
|
||||
CSU_CSLX_USB1,
|
||||
CSU_CSLX_QM_BM_SWPORTAL,
|
||||
CSU_CSLX_PCIE3 = 16,
|
||||
CSU_CSLX_PCIE3_IO,
|
||||
CSU_CSLX_USB3 = 20,
|
||||
CSU_CSLX_USB2,
|
||||
CSU_CSLX_SERDES = 32,
|
||||
CSU_CSLX_QDMA,
|
||||
CSU_CSLX_LPUART2,
|
||||
CSU_CSLX_LPUART1,
|
||||
CSU_CSLX_LPUART4,
|
||||
CSU_CSLX_LPUART3,
|
||||
CSU_CSLX_LPUART6,
|
||||
CSU_CSLX_LPUART5,
|
||||
CSU_CSLX_DSPI1 = 41,
|
||||
CSU_CSLX_QSPI,
|
||||
CSU_CSLX_ESDHC,
|
||||
CSU_CSLX_IFC = 45,
|
||||
CSU_CSLX_I2C1,
|
||||
CSU_CSLX_I2C3 = 48,
|
||||
CSU_CSLX_I2C2,
|
||||
CSU_CSLX_DUART2 = 50,
|
||||
CSU_CSLX_DUART1,
|
||||
CSU_CSLX_WDT2,
|
||||
CSU_CSLX_WDT1,
|
||||
CSU_CSLX_EDMA,
|
||||
CSU_CSLX_SYS_CNT,
|
||||
CSU_CSLX_DMA_MUX2,
|
||||
CSU_CSLX_DMA_MUX1,
|
||||
CSU_CSLX_DDR,
|
||||
CSU_CSLX_QUICC,
|
||||
CSU_CSLX_DCFG_CCU_RCPM = 60,
|
||||
CSU_CSLX_SECURE_BOOTROM,
|
||||
CSU_CSLX_SFP,
|
||||
CSU_CSLX_TMU,
|
||||
CSU_CSLX_SECURE_MONITOR,
|
||||
CSU_CSLX_SCFG,
|
||||
CSU_CSLX_FM = 66,
|
||||
CSU_CSLX_SEC5_5,
|
||||
CSU_CSLX_BM,
|
||||
CSU_CSLX_QM,
|
||||
CSU_CSLX_GPIO2 = 70,
|
||||
CSU_CSLX_GPIO1,
|
||||
CSU_CSLX_GPIO4,
|
||||
CSU_CSLX_GPIO3,
|
||||
CSU_CSLX_PLATFORM_CONT,
|
||||
CSU_CSLX_CSU,
|
||||
CSU_CSLX_IIC4 = 77,
|
||||
CSU_CSLX_WDT4,
|
||||
CSU_CSLX_WDT3,
|
||||
CSU_CSLX_WDT5 = 81,
|
||||
CSU_CSLX_FTM2 = 86,
|
||||
CSU_CSLX_FTM1,
|
||||
CSU_CSLX_FTM4,
|
||||
CSU_CSLX_FTM3,
|
||||
CSU_CSLX_FTM6 = 90,
|
||||
CSU_CSLX_FTM5,
|
||||
CSU_CSLX_FTM8,
|
||||
CSU_CSLX_FTM7,
|
||||
CSU_CSLX_DSCR = 121,
|
||||
};
|
||||
|
||||
static struct csu_ns_dev ns_dev[] = {
|
||||
{CSU_CSLX_PCIE2_IO, CSU_ALL_RW},
|
||||
{CSU_CSLX_PCIE1_IO, CSU_ALL_RW},
|
||||
{CSU_CSLX_MG2TPR_IP, CSU_ALL_RW},
|
||||
{CSU_CSLX_IFC_MEM, CSU_ALL_RW},
|
||||
{CSU_CSLX_OCRAM, CSU_ALL_RW},
|
||||
{CSU_CSLX_GIC, CSU_ALL_RW},
|
||||
{CSU_CSLX_PCIE1, CSU_ALL_RW},
|
||||
{CSU_CSLX_OCRAM2, CSU_ALL_RW},
|
||||
{CSU_CSLX_QSPI_MEM, CSU_ALL_RW},
|
||||
{CSU_CSLX_PCIE2, CSU_ALL_RW},
|
||||
{CSU_CSLX_SATA, CSU_ALL_RW},
|
||||
{CSU_CSLX_USB1, CSU_ALL_RW},
|
||||
{CSU_CSLX_QM_BM_SWPORTAL, CSU_ALL_RW},
|
||||
{CSU_CSLX_PCIE3, CSU_ALL_RW},
|
||||
{CSU_CSLX_PCIE3_IO, CSU_ALL_RW},
|
||||
{CSU_CSLX_USB3, CSU_ALL_RW},
|
||||
{CSU_CSLX_USB2, CSU_ALL_RW},
|
||||
{CSU_CSLX_SERDES, CSU_ALL_RW},
|
||||
{CSU_CSLX_QDMA, CSU_ALL_RW},
|
||||
{CSU_CSLX_LPUART2, CSU_ALL_RW},
|
||||
{CSU_CSLX_LPUART1, CSU_ALL_RW},
|
||||
{CSU_CSLX_LPUART4, CSU_ALL_RW},
|
||||
{CSU_CSLX_LPUART3, CSU_ALL_RW},
|
||||
{CSU_CSLX_LPUART6, CSU_ALL_RW},
|
||||
{CSU_CSLX_LPUART5, CSU_ALL_RW},
|
||||
{CSU_CSLX_DSPI1, CSU_ALL_RW},
|
||||
{CSU_CSLX_QSPI, CSU_ALL_RW},
|
||||
{CSU_CSLX_ESDHC, CSU_ALL_RW},
|
||||
{CSU_CSLX_IFC, CSU_ALL_RW},
|
||||
{CSU_CSLX_I2C1, CSU_ALL_RW},
|
||||
{CSU_CSLX_I2C3, CSU_ALL_RW},
|
||||
{CSU_CSLX_I2C2, CSU_ALL_RW},
|
||||
{CSU_CSLX_DUART2, CSU_ALL_RW},
|
||||
{CSU_CSLX_DUART1, CSU_ALL_RW},
|
||||
{CSU_CSLX_WDT2, CSU_ALL_RW},
|
||||
{CSU_CSLX_WDT1, CSU_ALL_RW},
|
||||
{CSU_CSLX_EDMA, CSU_ALL_RW},
|
||||
{CSU_CSLX_SYS_CNT, CSU_ALL_RW},
|
||||
{CSU_CSLX_DMA_MUX2, CSU_ALL_RW},
|
||||
{CSU_CSLX_DMA_MUX1, CSU_ALL_RW},
|
||||
{CSU_CSLX_DDR, CSU_ALL_RW},
|
||||
{CSU_CSLX_QUICC, CSU_ALL_RW},
|
||||
{CSU_CSLX_DCFG_CCU_RCPM, CSU_ALL_RW},
|
||||
{CSU_CSLX_SECURE_BOOTROM, CSU_ALL_RW},
|
||||
{CSU_CSLX_SFP, CSU_ALL_RW},
|
||||
{CSU_CSLX_TMU, CSU_ALL_RW},
|
||||
{CSU_CSLX_SECURE_MONITOR, CSU_ALL_RW},
|
||||
{CSU_CSLX_SCFG, CSU_ALL_RW},
|
||||
{CSU_CSLX_FM, CSU_ALL_RW},
|
||||
{CSU_CSLX_SEC5_5, CSU_ALL_RW},
|
||||
{CSU_CSLX_BM, CSU_ALL_RW},
|
||||
{CSU_CSLX_QM, CSU_ALL_RW},
|
||||
{CSU_CSLX_GPIO2, CSU_ALL_RW},
|
||||
{CSU_CSLX_GPIO1, CSU_ALL_RW},
|
||||
{CSU_CSLX_GPIO4, CSU_ALL_RW},
|
||||
{CSU_CSLX_GPIO3, CSU_ALL_RW},
|
||||
{CSU_CSLX_PLATFORM_CONT, CSU_ALL_RW},
|
||||
{CSU_CSLX_CSU, CSU_ALL_RW},
|
||||
{CSU_CSLX_IIC4, CSU_ALL_RW},
|
||||
{CSU_CSLX_WDT4, CSU_ALL_RW},
|
||||
{CSU_CSLX_WDT3, CSU_ALL_RW},
|
||||
{CSU_CSLX_WDT5, CSU_ALL_RW},
|
||||
{CSU_CSLX_FTM2, CSU_ALL_RW},
|
||||
{CSU_CSLX_FTM1, CSU_ALL_RW},
|
||||
{CSU_CSLX_FTM4, CSU_ALL_RW},
|
||||
{CSU_CSLX_FTM3, CSU_ALL_RW},
|
||||
{CSU_CSLX_FTM6, CSU_ALL_RW},
|
||||
{CSU_CSLX_FTM5, CSU_ALL_RW},
|
||||
{CSU_CSLX_FTM8, CSU_ALL_RW},
|
||||
{CSU_CSLX_FTM7, CSU_ALL_RW},
|
||||
{CSU_CSLX_DSCR, CSU_ALL_RW},
|
||||
};
|
||||
|
||||
#endif
|
53
arch/arm/include/asm/arch-fsl-layerscape/soc.h
Normal file
53
arch/arm/include/asm/arch-fsl-layerscape/soc.h
Normal file
|
@ -0,0 +1,53 @@
|
|||
/*
|
||||
* Copyright 2015 Freescale Semiconductor
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_
|
||||
#define _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_
|
||||
|
||||
#ifdef CONFIG_SYS_FSL_CCSR_GUR_LE
|
||||
#define gur_in32(a) in_le32(a)
|
||||
#define gur_out32(a, v) out_le32(a, v)
|
||||
#elif defined(CONFIG_SYS_FSL_CCSR_GUR_BE)
|
||||
#define gur_in32(a) in_be32(a)
|
||||
#define gur_out32(a, v) out_be32(a, v)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SYS_FSL_CCSR_SCFG_LE
|
||||
#define scfg_in32(a) in_le32(a)
|
||||
#define scfg_out32(a, v) out_le32(a, v)
|
||||
#elif defined(CONFIG_SYS_FSL_CCSR_SCFG_BE)
|
||||
#define scfg_in32(a) in_be32(a)
|
||||
#define scfg_out32(a, v) out_be32(a, v)
|
||||
#endif
|
||||
|
||||
struct cpu_type {
|
||||
char name[15];
|
||||
u32 soc_ver;
|
||||
u32 num_cores;
|
||||
};
|
||||
|
||||
#define CPU_TYPE_ENTRY(n, v, nc) \
|
||||
{ .name = #n, .soc_ver = SVR_##v, .num_cores = (nc)}
|
||||
|
||||
#define SVR_WO_E 0xFFFFFE
|
||||
#define SVR_LS1043 0x879204
|
||||
#define SVR_LS2045 0x870120
|
||||
#define SVR_LS2080 0x870110
|
||||
#define SVR_LS2085 0x870100
|
||||
|
||||
#define SVR_MAJ(svr) (((svr) >> 4) & 0xf)
|
||||
#define SVR_MIN(svr) (((svr) >> 0) & 0xf)
|
||||
#define SVR_SOC_VER(svr) (((svr) >> 8) & SVR_WO_E)
|
||||
#define IS_E_PROCESSOR(svr) (!((svr >> 8) & 0x1))
|
||||
|
||||
#ifdef CONFIG_FSL_LSCH3
|
||||
void fsl_lsch3_early_init_f(void);
|
||||
#elif defined(CONFIG_FSL_LSCH2)
|
||||
void fsl_lsch2_early_init_f(void);
|
||||
#endif
|
||||
|
||||
void cpu_name(char *name);
|
||||
#endif /* _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_ */
|
10
arch/arm/include/asm/arch-fsl-layerscape/speed.h
Normal file
10
arch/arm/include/asm/arch-fsl-layerscape/speed.h
Normal file
|
@ -0,0 +1,10 @@
|
|||
/*
|
||||
* Copyright 2014-2015, Freescale Semiconductor, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef _FSL_LAYERSCAPE_SPEED_H
|
||||
#define _FSL_LAYERSCAPE_SPEED_H
|
||||
void get_sys_info(struct sys_info *sys_info);
|
||||
#endif /* _FSL_LAYERSCAPE_SPEED_H */
|
|
@ -1,185 +0,0 @@
|
|||
/*
|
||||
* Copyright 2014, Freescale Semiconductor
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef _ASM_ARMV8_FSL_LSCH3_CONFIG_
|
||||
#define _ASM_ARMV8_FSL_LSCH3_CONFIG_
|
||||
|
||||
#include <fsl_ddrc_version.h>
|
||||
|
||||
#define CONFIG_SYS_PAGE_SIZE 0x10000
|
||||
#define CONFIG_SYS_CACHELINE_SIZE 64
|
||||
|
||||
#ifndef L1_CACHE_BYTES
|
||||
#define L1_CACHE_SHIFT 6
|
||||
#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
|
||||
#endif
|
||||
|
||||
#define CONFIG_MP
|
||||
#define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
|
||||
#define CONFIG_SYS_FSL_OCRAM_SIZE 0x00200000 /* 2M */
|
||||
/* Link Definitions */
|
||||
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
|
||||
|
||||
#define CONFIG_SYS_IMMR 0x01000000
|
||||
#define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000)
|
||||
#define CONFIG_SYS_FSL_DDR2_ADDR (CONFIG_SYS_IMMR + 0x00090000)
|
||||
#define CONFIG_SYS_FSL_DDR3_ADDR 0x08210000
|
||||
#define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00E00000)
|
||||
#define CONFIG_SYS_FSL_PMU_ADDR (CONFIG_SYS_IMMR + 0x00E30000)
|
||||
#define CONFIG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00E60000)
|
||||
#define CONFIG_SYS_FSL_CH3_CLK_GRPA_ADDR (CONFIG_SYS_IMMR + 0x00300000)
|
||||
#define CONFIG_SYS_FSL_CH3_CLK_GRPB_ADDR (CONFIG_SYS_IMMR + 0x00310000)
|
||||
#define CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR (CONFIG_SYS_IMMR + 0x00370000)
|
||||
#define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x01140000)
|
||||
#define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x01240000)
|
||||
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011C0500)
|
||||
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011C0600)
|
||||
#define CONFIG_SYS_FSL_TIMER_ADDR 0x023d0000
|
||||
#define CONFIG_SYS_FSL_PMU_CLTBENR (CONFIG_SYS_FSL_PMU_ADDR + \
|
||||
0x18A0)
|
||||
|
||||
#define CONFIG_SYS_FSL_WRIOP1_ADDR (CONFIG_SYS_IMMR + 0x7B80000)
|
||||
#define CONFIG_SYS_FSL_WRIOP1_MDIO1 (CONFIG_SYS_FSL_WRIOP1_ADDR + 0x16000)
|
||||
#define CONFIG_SYS_FSL_WRIOP1_MDIO2 (CONFIG_SYS_FSL_WRIOP1_ADDR + 0x17000)
|
||||
#define CONFIG_SYS_FSL_LSCH3_SERDES_ADDR (CONFIG_SYS_IMMR + 0xEA0000)
|
||||
|
||||
/* SP (Cortex-A5) related */
|
||||
#define CONFIG_SYS_FSL_SP_ADDR (CONFIG_SYS_IMMR + 0x00F00000)
|
||||
#define CONFIG_SYS_FSL_SP_VSG_GIC_ADDR (CONFIG_SYS_FSL_SP_ADDR)
|
||||
#define CONFIG_SYS_FSL_SP_VSG_GIC_VIGR1 (CONFIG_SYS_FSL_SP_ADDR)
|
||||
#define CONFIG_SYS_FSL_SP_VSG_GIC_VIGR2 \
|
||||
(CONFIG_SYS_FSL_SP_ADDR + 0x0008)
|
||||
#define CONFIG_SYS_FSL_SP_LOOPBACK_DUART \
|
||||
(CONFIG_SYS_FSL_SP_ADDR + 0x1000)
|
||||
|
||||
#define CONFIG_SYS_FSL_DCSR_DDR_ADDR 0x70012c000ULL
|
||||
#define CONFIG_SYS_FSL_DCSR_DDR2_ADDR 0x70012d000ULL
|
||||
#define CONFIG_SYS_FSL_DCSR_DDR3_ADDR 0x700132000ULL
|
||||
#define CONFIG_SYS_FSL_DCSR_DDR4_ADDR 0x700133000ULL
|
||||
|
||||
#define I2C1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01000000)
|
||||
#define I2C2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01010000)
|
||||
#define I2C3_BASE_ADDR (CONFIG_SYS_IMMR + 0x01020000)
|
||||
#define I2C4_BASE_ADDR (CONFIG_SYS_IMMR + 0x01030000)
|
||||
|
||||
#define CONFIG_SYS_LS2085A_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x02100000)
|
||||
#define CONFIG_SYS_LS2085A_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02110000)
|
||||
|
||||
/* TZ Protection Controller Definitions */
|
||||
#define TZPC_BASE 0x02200000
|
||||
#define TZPCR0SIZE_BASE (TZPC_BASE)
|
||||
#define TZPCDECPROT_0_STAT_BASE (TZPC_BASE + 0x800)
|
||||
#define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804)
|
||||
#define TZPCDECPROT_0_CLR_BASE (TZPC_BASE + 0x808)
|
||||
#define TZPCDECPROT_1_STAT_BASE (TZPC_BASE + 0x80C)
|
||||
#define TZPCDECPROT_1_SET_BASE (TZPC_BASE + 0x810)
|
||||
#define TZPCDECPROT_1_CLR_BASE (TZPC_BASE + 0x814)
|
||||
#define TZPCDECPROT_2_STAT_BASE (TZPC_BASE + 0x818)
|
||||
#define TZPCDECPROT_2_SET_BASE (TZPC_BASE + 0x81C)
|
||||
#define TZPCDECPROT_2_CLR_BASE (TZPC_BASE + 0x820)
|
||||
|
||||
/* TZ Address Space Controller Definitions */
|
||||
#define TZASC1_BASE 0x01100000 /* as per CCSR map. */
|
||||
#define TZASC2_BASE 0x01110000 /* as per CCSR map. */
|
||||
#define TZASC3_BASE 0x01120000 /* as per CCSR map. */
|
||||
#define TZASC4_BASE 0x01130000 /* as per CCSR map. */
|
||||
#define TZASC_BUILD_CONFIG_REG(x) ((TZASC1_BASE + (x * 0x10000)))
|
||||
#define TZASC_ACTION_REG(x) ((TZASC1_BASE + (x * 0x10000)) + 0x004)
|
||||
#define TZASC_GATE_KEEPER(x) ((TZASC1_BASE + (x * 0x10000)) + 0x008)
|
||||
#define TZASC_REGION_BASE_LOW_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x100)
|
||||
#define TZASC_REGION_BASE_HIGH_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x104)
|
||||
#define TZASC_REGION_TOP_LOW_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x108)
|
||||
#define TZASC_REGION_TOP_HIGH_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x10C)
|
||||
#define TZASC_REGION_ATTRIBUTES_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x110)
|
||||
#define TZASC_REGION_ID_ACCESS_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x114)
|
||||
|
||||
/* Generic Interrupt Controller Definitions */
|
||||
#define GICD_BASE 0x06000000
|
||||
#define GICR_BASE 0x06100000
|
||||
|
||||
/* SMMU Defintions */
|
||||
#define SMMU_BASE 0x05000000 /* GR0 Base */
|
||||
|
||||
/* DDR */
|
||||
#define CONFIG_SYS_FSL_DDR_LE
|
||||
#define CONFIG_VERY_BIG_RAM
|
||||
#ifdef CONFIG_SYS_FSL_DDR4
|
||||
#define CONFIG_SYS_FSL_DDRC_GEN4
|
||||
#else
|
||||
#define CONFIG_SYS_FSL_DDRC_ARM_GEN3 /* Enable Freescale ARM DDR3 driver */
|
||||
#endif
|
||||
#define CONFIG_SYS_FSL_DDR /* Freescale DDR driver */
|
||||
#define CONFIG_SYS_LS2_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
|
||||
#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_LS2_DDR_BLOCK1_SIZE
|
||||
#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0
|
||||
|
||||
#define CONFIG_SYS_FSL_ESDHC_LE
|
||||
/* IFC */
|
||||
#define CONFIG_SYS_FSL_IFC_LE
|
||||
#define CONFIG_SYS_MEMAC_LITTLE_ENDIAN
|
||||
|
||||
/* PCIe */
|
||||
#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000)
|
||||
#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000)
|
||||
#define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_IMMR + 0x2600000)
|
||||
#define CONFIG_SYS_PCIE4_ADDR (CONFIG_SYS_IMMR + 0x2700000)
|
||||
#define CONFIG_SYS_PCIE1_PHYS_ADDR 0x1000000000ULL
|
||||
#define CONFIG_SYS_PCIE2_PHYS_ADDR 0x1200000000ULL
|
||||
#define CONFIG_SYS_PCIE3_PHYS_ADDR 0x1400000000ULL
|
||||
#define CONFIG_SYS_PCIE4_PHYS_ADDR 0x1600000000ULL
|
||||
|
||||
/* Cache Coherent Interconnect */
|
||||
#define CCI_MN_BASE 0x04000000
|
||||
#define CCI_MN_RNF_NODEID_LIST 0x180
|
||||
#define CCI_MN_DVM_DOMAIN_CTL 0x200
|
||||
#define CCI_MN_DVM_DOMAIN_CTL_SET 0x210
|
||||
|
||||
#define CCI_RN_I_0_BASE (CCI_MN_BASE + 0x800000)
|
||||
#define CCI_RN_I_2_BASE (CCI_MN_BASE + 0x820000)
|
||||
#define CCI_RN_I_6_BASE (CCI_MN_BASE + 0x860000)
|
||||
#define CCI_RN_I_12_BASE (CCI_MN_BASE + 0x8C0000)
|
||||
#define CCI_RN_I_16_BASE (CCI_MN_BASE + 0x900000)
|
||||
#define CCI_RN_I_20_BASE (CCI_MN_BASE + 0x940000)
|
||||
|
||||
#define CCI_S0_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x10)
|
||||
#define CCI_S1_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x110)
|
||||
#define CCI_S2_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x210)
|
||||
|
||||
/* Device Configuration */
|
||||
#define DCFG_BASE 0x01e00000
|
||||
#define DCFG_PORSR1 0x000
|
||||
#define DCFG_PORSR1_RCW_SRC 0xff800000
|
||||
#define DCFG_PORSR1_RCW_SRC_NOR 0x12f00000
|
||||
#define DCFG_RCWSR13 0x130
|
||||
#define DCFG_RCWSR13_DSPI (0 << 8)
|
||||
|
||||
#define DCFG_DCSR_BASE 0X700100000ULL
|
||||
#define DCFG_DCSR_PORCR1 0x000
|
||||
|
||||
/* Supplemental Configuration */
|
||||
#define SCFG_BASE 0x01fc0000
|
||||
#define SCFG_USB3PRM1CR 0x000
|
||||
|
||||
#ifdef CONFIG_LS2085A
|
||||
#define CONFIG_MAX_CPUS 16
|
||||
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
|
||||
#define CONFIG_NUM_DDR_CONTROLLERS 3
|
||||
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 }
|
||||
#define CONFIG_SYS_FSL_SRDS_1
|
||||
#define CONFIG_SYS_FSL_SRDS_2
|
||||
#else
|
||||
#error SoC not defined
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_LS2085A
|
||||
#define CONFIG_SYS_FSL_ERRATUM_A008336
|
||||
#define CONFIG_SYS_FSL_ERRATUM_A008511
|
||||
#define CONFIG_SYS_FSL_ERRATUM_A008514
|
||||
#define CONFIG_SYS_FSL_ERRATUM_A008585
|
||||
#define CONFIG_SYS_FSL_ERRATUM_A008751
|
||||
#endif
|
||||
|
||||
#endif /* _ASM_ARMV8_FSL_LSCH3_CONFIG_ */
|
|
@ -1,67 +0,0 @@
|
|||
/*
|
||||
* Copyright 2015 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __FSL_SERDES_H
|
||||
#define __FSL_SERDES_H
|
||||
|
||||
#include <config.h>
|
||||
|
||||
#define SRDS_MAX_LANES 8
|
||||
|
||||
enum srds_prtcl {
|
||||
NONE = 0,
|
||||
PCIE1,
|
||||
PCIE2,
|
||||
PCIE3,
|
||||
PCIE4,
|
||||
SATA1,
|
||||
SATA2,
|
||||
XAUI1,
|
||||
XAUI2,
|
||||
XFI1,
|
||||
XFI2,
|
||||
XFI3,
|
||||
XFI4,
|
||||
XFI5,
|
||||
XFI6,
|
||||
XFI7,
|
||||
XFI8,
|
||||
SGMII1,
|
||||
SGMII2,
|
||||
SGMII3,
|
||||
SGMII4,
|
||||
SGMII5,
|
||||
SGMII6,
|
||||
SGMII7,
|
||||
SGMII8,
|
||||
SGMII9,
|
||||
SGMII10,
|
||||
SGMII11,
|
||||
SGMII12,
|
||||
SGMII13,
|
||||
SGMII14,
|
||||
SGMII15,
|
||||
SGMII16,
|
||||
QSGMII_A, /* A indicates MACs 1-4 */
|
||||
QSGMII_B, /* B indicates MACs 5-8 */
|
||||
QSGMII_C, /* C indicates MACs 9-12 */
|
||||
QSGMII_D, /* D indicates MACs 12-16 */
|
||||
SERDES_PRCTL_COUNT
|
||||
};
|
||||
|
||||
enum srds {
|
||||
FSL_SRDS_1 = 0,
|
||||
FSL_SRDS_2 = 1,
|
||||
};
|
||||
|
||||
int is_serdes_configured(enum srds_prtcl device);
|
||||
void fsl_serdes_init(void);
|
||||
|
||||
int serdes_get_first_lane(u32 sd, enum srds_prtcl device);
|
||||
enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane);
|
||||
int is_serdes_prtcl_valid(int serdes, u32 prtcl);
|
||||
|
||||
#endif /* __FSL_SERDES_H */
|
|
@ -1,9 +0,0 @@
|
|||
/*
|
||||
* Copyright 2014, Freescale Semiconductor
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef _ASM_ARMV8_FSL_LSCH3_GPIO_H_
|
||||
#define _ASM_ARMV8_FSL_LSCH3_GPIO_H_
|
||||
#endif /* _ASM_ARMV8_FSL_LSCH3_GPIO_H_ */
|
|
@ -1,13 +0,0 @@
|
|||
/*
|
||||
* Copyright 2014 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_FSL_LSCH3_IMX_REGS_H_
|
||||
#define __ASM_ARCH_FSL_LSCH3_IMX_REGS_H_
|
||||
|
||||
#define I2C_QUIRK_REG /* enable 8-bit driver */
|
||||
|
||||
#endif /* __ASM_ARCH_FSL_LSCH3_IMX_REGS_H_ */
|
|
@ -1,28 +0,0 @@
|
|||
/*
|
||||
* Copyright 2015 Freescale Semiconductor
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
struct cpu_type {
|
||||
char name[15];
|
||||
u32 soc_ver;
|
||||
u32 num_cores;
|
||||
};
|
||||
|
||||
#define CPU_TYPE_ENTRY(n, v, nc) \
|
||||
{ .name = #n, .soc_ver = SVR_##v, .num_cores = (nc)}
|
||||
|
||||
#define SVR_WO_E 0xFFFFFE
|
||||
#define SVR_LS2045 0x870120
|
||||
#define SVR_LS2080 0x870110
|
||||
#define SVR_LS2085 0x870100
|
||||
|
||||
#define SVR_MAJ(svr) (((svr) >> 4) & 0xf)
|
||||
#define SVR_MIN(svr) (((svr) >> 0) & 0xf)
|
||||
#define SVR_SOC_VER(svr) (((svr) >> 8) & SVR_WO_E)
|
||||
#define IS_E_PROCESSOR(svr) (!((svr >> 8) & 0x1))
|
||||
|
||||
void fsl_lsch3_early_init_f(void);
|
||||
void cpu_name(char *name);
|
||||
|
|
@ -79,6 +79,21 @@
|
|||
#define CONFIG_SYS_PCIE2_PHYS_ADDR (CONFIG_SYS_PCIE2_PHYS_BASE + \
|
||||
CONFIG_SYS_PCIE2_VIRT_ADDR)
|
||||
|
||||
/* SATA */
|
||||
#define AHCI_BASE_ADDR (CONFIG_SYS_IMMR + 0x02200000)
|
||||
#define CONFIG_BOARD_LATE_INIT
|
||||
#define CONFIG_CMD_SCSI
|
||||
#define CONFIG_LIBATA
|
||||
#define CONFIG_SCSI_AHCI
|
||||
#define CONFIG_SCSI_AHCI_PLAT
|
||||
#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
|
||||
#define CONFIG_SYS_SCSI_MAX_LUN 1
|
||||
#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
|
||||
CONFIG_SYS_SCSI_MAX_LUN)
|
||||
#define CONFIG_CMD_FAT
|
||||
#define CONFIG_DOS_PARTITION
|
||||
#define CONFIG_SYS_FSL_ERRATUM_A008407
|
||||
|
||||
#ifdef CONFIG_DDR_SPD
|
||||
#define CONFIG_SYS_FSL_DDR_BE
|
||||
#define CONFIG_VERY_BIG_RAM
|
||||
|
|
|
@ -144,6 +144,7 @@ struct ccsr_gur {
|
|||
};
|
||||
|
||||
#define SCFG_ETSECDMAMCR_LE_BD_FR 0x00000c00
|
||||
#define SCFG_SNPCNFGCR_SEC_RD_WR 0xc0000000
|
||||
#define SCFG_ETSECCMCR_GE2_CLK125 0x04000000
|
||||
#define SCFG_ETSECCMCR_GE0_CLK125 0x00000000
|
||||
#define SCFG_ETSECCMCR_GE1_CLK125 0x08000000
|
||||
|
@ -397,4 +398,28 @@ struct ccsr_cci400 {
|
|||
u8 res_e004[0x10000 - 0xe004];
|
||||
};
|
||||
|
||||
/* AHCI (sata) register map */
|
||||
struct ccsr_ahci {
|
||||
u32 res1[0xa4/4]; /* 0x0 - 0xa4 */
|
||||
u32 pcfg; /* port config */
|
||||
u32 ppcfg; /* port phy1 config */
|
||||
u32 pp2c; /* port phy2 config */
|
||||
u32 pp3c; /* port phy3 config */
|
||||
u32 pp4c; /* port phy4 config */
|
||||
u32 pp5c; /* port phy5 config */
|
||||
u32 paxic; /* port AXI config */
|
||||
u32 axicc; /* AXI cache control */
|
||||
u32 axipc; /* AXI PROT control */
|
||||
u32 ptc; /* port Trans Config */
|
||||
u32 pts; /* port Trans Status */
|
||||
u32 plc; /* port link config */
|
||||
u32 plc1; /* port link config1 */
|
||||
u32 plc2; /* port link config2 */
|
||||
u32 pls; /* port link status */
|
||||
u32 pls1; /* port link status1 */
|
||||
u32 pcmdc; /* port CMD config */
|
||||
u32 ppcs; /* port phy control status */
|
||||
u32 pberr; /* port 0/1 BIST error */
|
||||
u32 cmds; /* port 0/1 CMD status error */
|
||||
};
|
||||
#endif /* __ASM_ARCH_LS102XA_IMMAP_H_ */
|
||||
|
|
11
arch/arm/include/asm/arch-ls102xa/ls102xa_sata.h
Normal file
11
arch/arm/include/asm/arch-ls102xa/ls102xa_sata.h
Normal file
|
@ -0,0 +1,11 @@
|
|||
/*
|
||||
* Copyright 2015 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __FSL_SATA_H_
|
||||
#define __FSL_SATA_H_
|
||||
|
||||
int ls1021a_sata_init(void);
|
||||
#endif
|
|
@ -7,22 +7,6 @@
|
|||
#ifndef __FSL_NS_ACCESS_H_
|
||||
#define __FSL_NS_ACCESS_H_
|
||||
|
||||
enum csu_cslx_access {
|
||||
CSU_NS_SUP_R = 0x08,
|
||||
CSU_NS_SUP_W = 0x80,
|
||||
CSU_NS_SUP_RW = 0x88,
|
||||
CSU_NS_USER_R = 0x04,
|
||||
CSU_NS_USER_W = 0x40,
|
||||
CSU_NS_USER_RW = 0x44,
|
||||
CSU_S_SUP_R = 0x02,
|
||||
CSU_S_SUP_W = 0x20,
|
||||
CSU_S_SUP_RW = 0x22,
|
||||
CSU_S_USER_R = 0x01,
|
||||
CSU_S_USER_W = 0x10,
|
||||
CSU_S_USER_RW = 0x11,
|
||||
CSU_ALL_RW = 0xff,
|
||||
};
|
||||
|
||||
enum csu_cslx_ind {
|
||||
CSU_CSLX_PCIE2_IO = 0,
|
||||
CSU_CSLX_PCIE1_IO,
|
||||
|
@ -108,11 +92,88 @@ enum csu_cslx_ind {
|
|||
CSU_CSLX_MAX,
|
||||
};
|
||||
|
||||
struct csu_ns_dev {
|
||||
unsigned long ind;
|
||||
uint32_t val;
|
||||
static struct csu_ns_dev ns_dev[] = {
|
||||
{ CSU_CSLX_PCIE2_IO, CSU_ALL_RW },
|
||||
{ CSU_CSLX_PCIE1_IO, CSU_ALL_RW },
|
||||
{ CSU_CSLX_MG2TPR_IP, CSU_ALL_RW },
|
||||
{ CSU_CSLX_IFC_MEM, CSU_ALL_RW },
|
||||
{ CSU_CSLX_OCRAM, CSU_ALL_RW },
|
||||
{ CSU_CSLX_GIC, CSU_ALL_RW },
|
||||
{ CSU_CSLX_PCIE1, CSU_ALL_RW },
|
||||
{ CSU_CSLX_OCRAM2, CSU_ALL_RW },
|
||||
{ CSU_CSLX_QSPI_MEM, CSU_ALL_RW },
|
||||
{ CSU_CSLX_PCIE2, CSU_ALL_RW },
|
||||
{ CSU_CSLX_SATA, CSU_ALL_RW },
|
||||
{ CSU_CSLX_USB3, CSU_ALL_RW },
|
||||
{ CSU_CSLX_SERDES, CSU_ALL_RW },
|
||||
{ CSU_CSLX_QDMA, CSU_ALL_RW },
|
||||
{ CSU_CSLX_LPUART2, CSU_ALL_RW },
|
||||
{ CSU_CSLX_LPUART1, CSU_ALL_RW },
|
||||
{ CSU_CSLX_LPUART4, CSU_ALL_RW },
|
||||
{ CSU_CSLX_LPUART3, CSU_ALL_RW },
|
||||
{ CSU_CSLX_LPUART6, CSU_ALL_RW },
|
||||
{ CSU_CSLX_LPUART5, CSU_ALL_RW },
|
||||
{ CSU_CSLX_DSPI2, CSU_ALL_RW },
|
||||
{ CSU_CSLX_DSPI1, CSU_ALL_RW },
|
||||
{ CSU_CSLX_QSPI, CSU_ALL_RW },
|
||||
{ CSU_CSLX_ESDHC, CSU_ALL_RW },
|
||||
{ CSU_CSLX_2D_ACE, CSU_ALL_RW },
|
||||
{ CSU_CSLX_IFC, CSU_ALL_RW },
|
||||
{ CSU_CSLX_I2C1, CSU_ALL_RW },
|
||||
{ CSU_CSLX_USB2, CSU_ALL_RW },
|
||||
{ CSU_CSLX_I2C3, CSU_ALL_RW },
|
||||
{ CSU_CSLX_I2C2, CSU_ALL_RW },
|
||||
{ CSU_CSLX_DUART2, CSU_ALL_RW },
|
||||
{ CSU_CSLX_DUART1, CSU_ALL_RW },
|
||||
{ CSU_CSLX_WDT2, CSU_ALL_RW },
|
||||
{ CSU_CSLX_WDT1, CSU_ALL_RW },
|
||||
{ CSU_CSLX_EDMA, CSU_ALL_RW },
|
||||
{ CSU_CSLX_SYS_CNT, CSU_ALL_RW },
|
||||
{ CSU_CSLX_DMA_MUX2, CSU_ALL_RW },
|
||||
{ CSU_CSLX_DMA_MUX1, CSU_ALL_RW },
|
||||
{ CSU_CSLX_DDR, CSU_ALL_RW },
|
||||
{ CSU_CSLX_QUICC, CSU_ALL_RW },
|
||||
{ CSU_CSLX_DCFG_CCU_RCPM, CSU_ALL_RW },
|
||||
{ CSU_CSLX_SECURE_BOOTROM, CSU_ALL_RW },
|
||||
{ CSU_CSLX_SFP, CSU_ALL_RW },
|
||||
{ CSU_CSLX_TMU, CSU_ALL_RW },
|
||||
{ CSU_CSLX_SECURE_MONITOR, CSU_ALL_RW },
|
||||
{ CSU_CSLX_RESERVED0, CSU_ALL_RW },
|
||||
{ CSU_CSLX_ETSEC1, CSU_ALL_RW },
|
||||
{ CSU_CSLX_SEC5_5, CSU_ALL_RW },
|
||||
{ CSU_CSLX_ETSEC3, CSU_ALL_RW },
|
||||
{ CSU_CSLX_ETSEC2, CSU_ALL_RW },
|
||||
{ CSU_CSLX_GPIO2, CSU_ALL_RW },
|
||||
{ CSU_CSLX_GPIO1, CSU_ALL_RW },
|
||||
{ CSU_CSLX_GPIO4, CSU_ALL_RW },
|
||||
{ CSU_CSLX_GPIO3, CSU_ALL_RW },
|
||||
{ CSU_CSLX_PLATFORM_CONT, CSU_ALL_RW },
|
||||
{ CSU_CSLX_CSU, CSU_ALL_RW },
|
||||
{ CSU_CSLX_ASRC, CSU_ALL_RW },
|
||||
{ CSU_CSLX_SPDIF, CSU_ALL_RW },
|
||||
{ CSU_CSLX_FLEXCAN2, CSU_ALL_RW },
|
||||
{ CSU_CSLX_FLEXCAN1, CSU_ALL_RW },
|
||||
{ CSU_CSLX_FLEXCAN4, CSU_ALL_RW },
|
||||
{ CSU_CSLX_FLEXCAN3, CSU_ALL_RW },
|
||||
{ CSU_CSLX_SAI2, CSU_ALL_RW },
|
||||
{ CSU_CSLX_SAI1, CSU_ALL_RW },
|
||||
{ CSU_CSLX_SAI4, CSU_ALL_RW },
|
||||
{ CSU_CSLX_SAI3, CSU_ALL_RW },
|
||||
{ CSU_CSLX_FTM2, CSU_ALL_RW },
|
||||
{ CSU_CSLX_FTM1, CSU_ALL_RW },
|
||||
{ CSU_CSLX_FTM4, CSU_ALL_RW },
|
||||
{ CSU_CSLX_FTM3, CSU_ALL_RW },
|
||||
{ CSU_CSLX_FTM6, CSU_ALL_RW },
|
||||
{ CSU_CSLX_FTM5, CSU_ALL_RW },
|
||||
{ CSU_CSLX_FTM8, CSU_ALL_RW },
|
||||
{ CSU_CSLX_FTM7, CSU_ALL_RW },
|
||||
{ CSU_CSLX_COP_DCSR, CSU_ALL_RW },
|
||||
{ CSU_CSLX_EPU, CSU_ALL_RW },
|
||||
{ CSU_CSLX_GDI, CSU_ALL_RW },
|
||||
{ CSU_CSLX_DDI, CSU_ALL_RW },
|
||||
{ CSU_CSLX_RESERVED1, CSU_ALL_RW },
|
||||
{ CSU_CSLX_USB3_PHY, CSU_ALL_RW },
|
||||
{ CSU_CSLX_RESERVED2, CSU_ALL_RW },
|
||||
};
|
||||
|
||||
void enable_devices_ns_access(struct csu_ns_dev *ns_dev, uint32_t num);
|
||||
|
||||
#endif
|
||||
|
|
|
@ -104,6 +104,7 @@ struct stm32_flash_regs {
|
|||
#define STM32_FLASH_CR_STRT (1 << 16)
|
||||
#define STM32_FLASH_CR_LOCK (1 << 31)
|
||||
#define STM32_FLASH_CR_SNB_OFFSET 3
|
||||
#define STM32_FLASH_CR_SNB_MASK (15 << STM32_FLASH_CR_SNB_OFFSET)
|
||||
|
||||
enum clock {
|
||||
CLOCK_CORE,
|
||||
|
|
|
@ -13,7 +13,7 @@ static inline void zynq_slcr_gem_clk_setup(u32 gem_id, unsigned long clk_rate)
|
|||
{
|
||||
}
|
||||
|
||||
int zynq_sdhci_init(unsigned long regbase);
|
||||
int zynq_sdhci_init(phys_addr_t regbase);
|
||||
int zynq_slcr_get_mio_pin_status(const char *periph);
|
||||
|
||||
unsigned int zynqmp_get_silicon_version(void);
|
||||
|
|
|
@ -65,6 +65,7 @@
|
|||
/*
|
||||
* Section
|
||||
*/
|
||||
#define PMD_SECT_NS (1 << 5)
|
||||
#define PMD_SECT_NON_SHARE (0 << 8)
|
||||
#define PMD_SECT_OUTER_SHARE (2 << 8)
|
||||
#define PMD_SECT_INNER_SHARE (3 << 8)
|
||||
|
|
|
@ -190,4 +190,9 @@ found_middle:
|
|||
|
||||
#endif /* __KERNEL__ */
|
||||
|
||||
#include <asm-generic/bitops/__fls.h>
|
||||
#include <asm-generic/bitops/__ffs.h>
|
||||
#include <asm-generic/bitops/fls.h>
|
||||
#include <asm-generic/bitops/fls64.h>
|
||||
|
||||
#endif /* _ARM_BITOPS_H */
|
||||
|
|
|
@ -16,6 +16,9 @@
|
|||
/*
|
||||
* Invalidate L2 Cache using co-proc instruction
|
||||
*/
|
||||
#ifdef CONFIG_SYS_THUMB_BUILD
|
||||
void invalidate_l2_cache(void);
|
||||
#else
|
||||
static inline void invalidate_l2_cache(void)
|
||||
{
|
||||
unsigned int val=0;
|
||||
|
@ -24,6 +27,7 @@ static inline void invalidate_l2_cache(void)
|
|||
: : "r" (val) : "cc");
|
||||
isb();
|
||||
}
|
||||
#endif
|
||||
|
||||
void l2_cache_enable(void);
|
||||
void l2_cache_disable(void);
|
||||
|
|
|
@ -15,14 +15,11 @@
|
|||
#define CONFIG_STATIC_RELA
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_FSL_LSCH3
|
||||
#include <asm/arch-fsl-lsch3/config.h>
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_LS102XA) || \
|
||||
defined(CONFIG_CPU_PXA27X) || \
|
||||
defined(CONFIG_CPU_MONAHANS) || \
|
||||
defined(CONFIG_CPU_PXA25X)
|
||||
defined(CONFIG_CPU_PXA25X) || \
|
||||
defined(CONFIG_FSL_LAYERSCAPE)
|
||||
#include <asm/arch/config.h>
|
||||
#endif
|
||||
|
||||
|
|
|
@ -46,7 +46,7 @@ static inline void sync(void)
|
|||
static inline void *
|
||||
map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags)
|
||||
{
|
||||
return (void *)paddr;
|
||||
return (void *)((unsigned long)paddr);
|
||||
}
|
||||
|
||||
/*
|
||||
|
@ -59,7 +59,7 @@ static inline void unmap_physmem(void *vaddr, unsigned long flags)
|
|||
|
||||
static inline phys_addr_t virt_to_phys(void * vaddr)
|
||||
{
|
||||
return (phys_addr_t)(vaddr);
|
||||
return (phys_addr_t)((unsigned long)vaddr);
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
|
@ -17,6 +17,7 @@
|
|||
#define PGTABLE_SIZE (0x10000)
|
||||
/* 2MB granularity */
|
||||
#define MMU_SECTION_SHIFT 21
|
||||
#define MMU_SECTION_SIZE (1 << MMU_SECTION_SHIFT)
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
|
@ -278,11 +279,6 @@ enum {
|
|||
*/
|
||||
void mmu_page_table_flush(unsigned long start, unsigned long stop);
|
||||
|
||||
#ifdef CONFIG_SYS_NONCACHED_MEMORY
|
||||
void noncached_init(void);
|
||||
phys_addr_t noncached_alloc(size_t size, size_t align);
|
||||
#endif /* CONFIG_SYS_NONCACHED_MEMORY */
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
#define arch_align_stack(x) (x)
|
||||
|
@ -302,6 +298,11 @@ phys_addr_t noncached_alloc(size_t size, size_t align);
|
|||
void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
|
||||
enum dcache_option option);
|
||||
|
||||
#ifdef CONFIG_SYS_NONCACHED_MEMORY
|
||||
void noncached_init(void);
|
||||
phys_addr_t noncached_alloc(size_t size, size_t align);
|
||||
#endif /* CONFIG_SYS_NONCACHED_MEMORY */
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
#endif
|
||||
|
|
|
@ -45,12 +45,16 @@ typedef unsigned long long u64;
|
|||
#define BITS_PER_LONG 32
|
||||
#endif /* CONFIG_ARM64 */
|
||||
|
||||
/* Dma addresses are 32-bits wide. */
|
||||
|
||||
#ifdef CONFIG_PHYS_64BIT
|
||||
typedef unsigned long long dma_addr_t;
|
||||
typedef unsigned long long phys_addr_t;
|
||||
typedef unsigned long long phys_size_t;
|
||||
#else
|
||||
/* DMA addresses are 32-bits wide */
|
||||
typedef u32 dma_addr_t;
|
||||
|
||||
typedef unsigned long phys_addr_t;
|
||||
typedef unsigned long phys_size_t;
|
||||
#endif
|
||||
|
||||
#endif /* __KERNEL__ */
|
||||
|
||||
|
|
|
@ -60,3 +60,27 @@ obj-$(CONFIG_DEBUG_LL) += debug.o
|
|||
ifneq (,$(findstring -mabi=aapcs-linux,$(PLATFORM_CPPFLAGS)))
|
||||
extra-y += eabi_compat.o
|
||||
endif
|
||||
|
||||
# some files can only build in ARM or THUMB2, not THUMB1
|
||||
|
||||
ifdef CONFIG_SYS_THUMB_BUILD
|
||||
ifndef CONFIG_HAS_THUMB2
|
||||
|
||||
# for C files, just apend -marm, which will override previous -mthumb*
|
||||
|
||||
CFLAGS_cache.o := -marm
|
||||
CFLAGS_cache-cp15.o := -marm
|
||||
|
||||
# For .S, drop -mthumb* and other thumb-related options.
|
||||
# CFLAGS_REMOVE_* would not have an effet, so AFLAGS_REMOVE_*
|
||||
# was implemented and is used here.
|
||||
# Also, define ${target}_NO_THUMB_BUILD for these two targets
|
||||
# so that the code knows it should not use Thumb.
|
||||
|
||||
AFLAGS_REMOVE_memset.o := -mthumb -mthumb-interwork
|
||||
AFLAGS_REMOVE_memcpy.o := -mthumb -mthumb-interwork
|
||||
AFLAGS_memset.o := -DMEMSET_NO_THUMB_BUILD
|
||||
AFLAGS_memcpy.o := -DMEMCPY_NO_THUMB_BUILD
|
||||
|
||||
endif
|
||||
endif
|
||||
|
|
|
@ -88,3 +88,14 @@ phys_addr_t noncached_alloc(size_t size, size_t align)
|
|||
return next;
|
||||
}
|
||||
#endif /* CONFIG_SYS_NONCACHED_MEMORY */
|
||||
|
||||
#if defined(CONFIG_SYS_THUMB_BUILD)
|
||||
void invalidate_l2_cache(void)
|
||||
{
|
||||
unsigned int val = 0;
|
||||
|
||||
asm volatile("mcr p15, 1, %0, c15, c11, 0 @ invl l2 cache"
|
||||
: : "r" (val) : "cc");
|
||||
isb();
|
||||
}
|
||||
#endif
|
||||
|
|
|
@ -13,7 +13,7 @@
|
|||
#include <linux/linkage.h>
|
||||
#include <asm/assembler.h>
|
||||
|
||||
#ifdef CONFIG_SYS_THUMB_BUILD
|
||||
#if defined(CONFIG_SYS_THUMB_BUILD) && !defined(MEMCPY_NO_THUMB_BUILD)
|
||||
#define W(instr) instr.w
|
||||
#else
|
||||
#define W(instr) instr
|
||||
|
@ -62,7 +62,7 @@
|
|||
|
||||
/* Prototype: void *memcpy(void *dest, const void *src, size_t n); */
|
||||
.syntax unified
|
||||
#ifdef CONFIG_SYS_THUMB_BUILD
|
||||
#if defined(CONFIG_SYS_THUMB_BUILD) && !defined(MEMCPY_NO_THUMB_BUILD)
|
||||
.thumb
|
||||
.thumb_func
|
||||
#endif
|
||||
|
|
|
@ -16,7 +16,7 @@
|
|||
.align 5
|
||||
|
||||
.syntax unified
|
||||
#ifdef CONFIG_SYS_THUMB_BUILD
|
||||
#if defined(CONFIG_SYS_THUMB_BUILD) && !defined(MEMSET_NO_THUMB_BUILD)
|
||||
.thumb
|
||||
.thumb_func
|
||||
#endif
|
||||
|
|
|
@ -31,6 +31,8 @@ static noinline long smh_trap(unsigned int sysnum, void *addr)
|
|||
register long result asm("r0");
|
||||
#if defined(CONFIG_ARM64)
|
||||
asm volatile ("hlt #0xf000" : "=r" (result) : "0"(sysnum), "r"(addr));
|
||||
#elif defined(CONFIG_CPU_V7M)
|
||||
asm volatile ("bkpt #0xAB" : "=r" (result) : "0"(sysnum), "r"(addr));
|
||||
#else
|
||||
/* Note - untested placeholder */
|
||||
asm volatile ("svc #0x123456" : "=r" (result) : "0"(sysnum), "r"(addr));
|
||||
|
@ -90,7 +92,7 @@ static long smh_read(long fd, void *memp, size_t len)
|
|||
size_t len;
|
||||
} read;
|
||||
|
||||
debug("%s: fd %ld, memp %p, len %lu\n", __func__, fd, memp, len);
|
||||
debug("%s: fd %ld, memp %p, len %zu\n", __func__, fd, memp, len);
|
||||
|
||||
read.fd = fd;
|
||||
read.memp = memp;
|
||||
|
@ -104,7 +106,7 @@ static long smh_read(long fd, void *memp, size_t len)
|
|||
* hard to maintain partial read loops and such, just fail
|
||||
* with an error message.
|
||||
*/
|
||||
printf("%s: ERROR ret %ld, fd %ld, len %lu memp %p\n",
|
||||
printf("%s: ERROR ret %ld, fd %ld, len %zu memp %p\n",
|
||||
__func__, ret, fd, len, memp);
|
||||
return -1;
|
||||
}
|
||||
|
|
|
@ -1,3 +1,7 @@
|
|||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
obj-$(CONFIG_AT91_WANTS_COMMON_PHY) += phy.o
|
||||
ifneq ($(CONFIG_SPL_BUILD),)
|
||||
obj-$(CONFIG_AT91SAM9260) += sdram.o spl_at91.o
|
||||
|
|
|
@ -5,11 +5,13 @@
|
|||
* Copyright (C) 2005 Ivan Kokshaysky
|
||||
* Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
|
||||
* Copyright (C) 2013 Bo Shen <voice.shen@atmel.com>
|
||||
* Copyright (C) 2015 Wenyou Yang <wenyou.yang@atmel.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/errno.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/hardware.h>
|
||||
#include <asm/arch/at91_pmc.h>
|
||||
|
@ -173,3 +175,96 @@ void at91_periph_clk_disable(int id)
|
|||
|
||||
writel(regval, &pmc->pcr);
|
||||
}
|
||||
|
||||
int at91_enable_periph_generated_clk(u32 id, u32 clk_source, u32 div)
|
||||
{
|
||||
struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
|
||||
u32 regval, status;
|
||||
u32 timeout = 1000;
|
||||
|
||||
if (id > AT91_PMC_PCR_PID_MASK)
|
||||
return -EINVAL;
|
||||
|
||||
if (div > 0xff)
|
||||
return -EINVAL;
|
||||
|
||||
writel(id, &pmc->pcr);
|
||||
regval = readl(&pmc->pcr);
|
||||
regval &= ~AT91_PMC_PCR_GCKCSS;
|
||||
regval &= ~AT91_PMC_PCR_GCKDIV;
|
||||
|
||||
switch (clk_source) {
|
||||
case GCK_CSS_SLOW_CLK:
|
||||
regval |= AT91_PMC_PCR_GCKCSS_SLOW_CLK;
|
||||
break;
|
||||
case GCK_CSS_MAIN_CLK:
|
||||
regval |= AT91_PMC_PCR_GCKCSS_MAIN_CLK;
|
||||
break;
|
||||
case GCK_CSS_PLLA_CLK:
|
||||
regval |= AT91_PMC_PCR_GCKCSS_PLLA_CLK;
|
||||
break;
|
||||
case GCK_CSS_UPLL_CLK:
|
||||
regval |= AT91_PMC_PCR_GCKCSS_UPLL_CLK;
|
||||
break;
|
||||
case GCK_CSS_MCK_CLK:
|
||||
regval |= AT91_PMC_PCR_GCKCSS_MCK_CLK;
|
||||
break;
|
||||
case GCK_CSS_AUDIO_CLK:
|
||||
regval |= AT91_PMC_PCR_GCKCSS_AUDIO_CLK;
|
||||
break;
|
||||
default:
|
||||
printf("Error GCK clock source selection!\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
regval |= AT91_PMC_PCR_CMD_WRITE |
|
||||
AT91_PMC_PCR_GCKDIV_(div) |
|
||||
AT91_PMC_PCR_GCKEN;
|
||||
|
||||
writel(regval, &pmc->pcr);
|
||||
|
||||
do {
|
||||
udelay(1);
|
||||
status = readl(&pmc->sr);
|
||||
} while ((!!(--timeout)) && (!(status & AT91_PMC_GCKRDY)));
|
||||
|
||||
if (!timeout)
|
||||
printf("Timeout waiting for GCK ready!\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
u32 at91_get_periph_generated_clk(u32 id)
|
||||
{
|
||||
struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
|
||||
u32 regval, clk_source, div;
|
||||
u32 freq;
|
||||
|
||||
if (id > AT91_PMC_PCR_PID_MASK)
|
||||
return 0;
|
||||
|
||||
writel(id, &pmc->pcr);
|
||||
regval = readl(&pmc->pcr);
|
||||
|
||||
clk_source = regval & AT91_PMC_PCR_GCKCSS;
|
||||
switch (clk_source) {
|
||||
case AT91_PMC_PCR_GCKCSS_SLOW_CLK:
|
||||
freq = CONFIG_SYS_AT91_SLOW_CLOCK;
|
||||
break;
|
||||
case AT91_PMC_PCR_GCKCSS_MAIN_CLK:
|
||||
freq = gd->arch.main_clk_rate_hz;
|
||||
break;
|
||||
case AT91_PMC_PCR_GCKCSS_PLLA_CLK:
|
||||
freq = gd->arch.plla_rate_hz;
|
||||
break;
|
||||
default:
|
||||
printf("Improper GCK clock source selection!\n");
|
||||
freq = 0;
|
||||
break;
|
||||
}
|
||||
|
||||
div = ((regval & AT91_PMC_PCR_GCKDIV) >> AT91_PMC_PCR_GCKDIV_OFFSET);
|
||||
div += 1;
|
||||
|
||||
return freq / div;
|
||||
}
|
||||
|
|
|
@ -12,7 +12,6 @@
|
|||
#include <common.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/hardware.h>
|
||||
#include <asm/arch/at91_dbu.h>
|
||||
#include <asm/arch/at91_pmc.h>
|
||||
#include <asm/arch/at91_pit.h>
|
||||
#include <asm/arch/at91_gpbr.h>
|
||||
|
@ -65,12 +64,14 @@ void enable_caches(void)
|
|||
dcache_enable();
|
||||
}
|
||||
|
||||
#define ATMEL_CHIPID_CIDR_VERSION 0x1f
|
||||
|
||||
unsigned int get_chip_id(void)
|
||||
{
|
||||
return readl(ATMEL_BASE_DBGU + AT91_DBU_CIDR) & ~AT91_DBU_CIDR_MASK;
|
||||
return readl(ATMEL_CHIPID_CIDR) & ~ATMEL_CHIPID_CIDR_VERSION;
|
||||
}
|
||||
|
||||
unsigned int get_extension_chip_id(void)
|
||||
{
|
||||
return readl(ATMEL_BASE_DBGU + AT91_DBU_EXID);
|
||||
return readl(ATMEL_CHIPID_EXID);
|
||||
}
|
||||
|
|
Some files were not shown because too many files have changed in this diff Show more
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Add table
Reference in a new issue