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EXYNOS5: CLOCK: Modify MPLL clock out for Exynos5250 Rev 1.0

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MPLL clock-out of Exynos5250 Rev 1.0 is always at 1.6GHz.
Adjust the divisor value to get 800MHz as needed by devices
like UART etc

Signed-off-by: Hatim Ali <hatim.rv@samsung.com>
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Acked-by: Joonyoung Shim <jy0922.shim@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This commit is contained in:
Rajeshwari Shinde 2012-07-03 20:02:57 +00:00 • committed by Albert ARIBAUD
parent 87f2e079db
commit 6071bcaec1
2 changed files with 14 additions and 1 deletions
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12
arch/arm/cpu/armv7/exynos/clock.c
View file

@ -98,7 +98,7 @@ static unsigned long exynos5_get_pll_clk(int pllreg)
struct exynos5_clock *clk = struct exynos5_clock *clk =
(struct exynos5_clock *)samsung_get_base_clock(); (struct exynos5_clock *)samsung_get_base_clock();
unsigned long r, m, p, s, k = 0, mask, fout; unsigned long r, m, p, s, k = 0, mask, fout;
unsigned int freq; unsigned int freq, pll_div2_sel, mpll_fout_sel;
switch (pllreg) { switch (pllreg) {
case APLL: case APLL:
@ -155,6 +155,16 @@ static unsigned long exynos5_get_pll_clk(int pllreg)
fout = m * (freq / (p * (1 << (s - 1)))); fout = m * (freq / (p * (1 << (s - 1))));
} }
/* According to the user manual, in EVT1 MPLL always gives
* 1.6GHz clock, so divide by 2 to get 800MHz MPLL clock.*/
if (pllreg == MPLL) {
pll_div2_sel = readl(&clk->pll_div2_sel);
mpll_fout_sel = (pll_div2_sel >> MPLL_FOUT_SEL_SHIFT)
& MPLL_FOUT_SEL_MASK;
if (mpll_fout_sel == 0)
fout /= 2;
}
return fout; return fout;
} }

3
arch/arm/include/asm/arch-exynos/clock.h
View file

@ -596,4 +596,7 @@ struct exynos5_clock {
unsigned char res123[0xf5d8]; unsigned char res123[0xf5d8];
}; };
#endif #endif
#define MPLL_FOUT_SEL_SHIFT 4
#define MPLL_FOUT_SEL_MASK 0x1
#endif #endif