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arm: dts: add PCIe controller for MT7623 SoC
This adds PCIe and its PHY nodes for MT7623. Tested-by: Frank Wunderlich <frank-w@public-files.de> Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
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@ -9,6 +9,7 @@
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/phy/phy.h>
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#include <dt-bindings/power/mt7623-power.h>
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#include <dt-bindings/reset/mtk-reset.h>
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#include "skeleton.dtsi"
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@ -255,6 +256,133 @@
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#reset-cells = <1>;
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};
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pcie: pcie@1a140000 {
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compatible = "mediatek,mt7623-pcie";
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device_type = "pci";
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reg = <0x1a140000 0x1000>, /* PCIe shared registers */
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<0x1a142000 0x1000>, /* Port0 registers */
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<0x1a143000 0x1000>, /* Port1 registers */
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<0x1a144000 0x1000>; /* Port2 registers */
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reg-names = "subsys", "port0", "port1", "port2";
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0xf800 0 0 0>;
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interrupt-map = <0x0000 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>,
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<0x0800 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>,
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<0x1000 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
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<&hifsys CLK_HIFSYS_PCIE0>,
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<&hifsys CLK_HIFSYS_PCIE1>,
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<&hifsys CLK_HIFSYS_PCIE2>;
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clock-names = "free_ck", "sys_ck0", "sys_ck1", "sys_ck2";
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resets = <&hifsys HIFSYS_PCIE0_RST>,
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<&hifsys HIFSYS_PCIE1_RST>,
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<&hifsys HIFSYS_PCIE2_RST>;
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reset-names = "pcie-rst0", "pcie-rst1", "pcie-rst2";
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phys = <&pcie0_port PHY_TYPE_PCIE>,
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<&pcie1_port PHY_TYPE_PCIE>,
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<&u3port1 PHY_TYPE_PCIE>;
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phy-names = "pcie-phy0", "pcie-phy1", "pcie-phy2";
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power-domains = <&scpsys MT7623_POWER_DOMAIN_HIF>;
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bus-range = <0x00 0xff>;
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status = "disabled";
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ranges = <0x81000000 0 0x1a160000 0x1a160000 0 0x00010000
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0x83000000 0 0x60000000 0x60000000 0 0x10000000>;
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pcie@0,0 {
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reg = <0x0000 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>;
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ranges;
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status = "disabled";
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};
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pcie@1,0 {
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reg = <0x0800 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;
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ranges;
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status = "disabled";
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};
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pcie@2,0 {
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reg = <0x1000 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
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ranges;
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status = "disabled";
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};
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};
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pcie0_phy: pcie-phy@1a149000 {
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compatible = "mediatek,generic-tphy-v1";
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reg = <0x1a149000 0x0700>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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status = "disabled";
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pcie0_port: pcie-phy@1a149900 {
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reg = <0x1a149900 0x0700>;
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clocks = <&clk26m>;
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clock-names = "ref";
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#phy-cells = <1>;
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status = "okay";
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};
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};
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pcie1_phy: pcie-phy@1a14a000 {
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compatible = "mediatek,generic-tphy-v1";
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reg = <0x1a14a000 0x0700>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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status = "disabled";
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pcie1_port: pcie-phy@1a14a900 {
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reg = <0x1a14a900 0x0700>;
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clocks = <&clk26m>;
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clock-names = "ref";
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#phy-cells = <1>;
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status = "okay";
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};
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};
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u3phy2: usb-phy@1a244000 {
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compatible = "mediatek,generic-tphy-v1";
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reg = <0x1a244000 0x0700>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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status = "disabled";
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u2port1: usb-phy@1a244800 {
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reg = <0x1a244800 0x0100>;
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clocks = <&topckgen CLK_TOP_USB_PHY48M>;
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clock-names = "ref";
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#phy-cells = <1>;
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status = "okay";
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};
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u3port1: usb-phy@1a244900 {
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reg = <0x1a244900 0x0700>;
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clocks = <&clk26m>;
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clock-names = "ref";
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#phy-cells = <1>;
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status = "okay";
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};
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};
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ethsys: syscon@1b000000 {
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compatible = "mediatek,mt7623-ethsys", "syscon";
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reg = <0x1b000000 0x1000>;
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@ -172,6 +172,13 @@
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};
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};
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pcie_default: pcie-default {
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mux {
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function = "pcie";
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groups = "pcie0_0_perst", "pcie1_0_perst";
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};
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};
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uart0_pins_a: uart0-default {
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mux {
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function = "uart";
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@ -201,6 +208,28 @@
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};
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};
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&pcie {
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pinctrl-names = "default";
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pinctrl-0 = <&pcie_default>;
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status = "okay";
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pcie@0,0 {
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status = "okay";
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};
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pcie@1,0 {
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status = "okay";
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};
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};
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&pcie0_phy {
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status = "okay";
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};
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&pcie1_phy {
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status = "okay";
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};
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&uart0 {
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pinctrl-names = "default";
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pinctrl-0 = <&uart0_pins_a>;
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