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Patch by David Adair, 27 Oct 2004:

Browse source 
Add missing 440GX SDRAM Controller reset
This commit is contained in:
wdenk 2005-04-03 20:55:38 +00:00
parent 3ec924a3cb
commit 6315349202
4 changed files with 412 additions and 371 deletions
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3
CHANGELOG
View file

@ -2,6 +2,9 @@
Changes for U-Boot 1.1.3:
======================================================================
* Patch by David Adair, 27 Oct 2004:
Add missing 440GX SDRAM Controller reset
* Patch by Steven Scholz, 25 Oct 2004:
Declare reset_cpu() in include/common.h instead locally

8
cpu/ppc4xx/spd_sdram.c
View file

@ -772,6 +772,14 @@ long int spd_sdram(void) {
*/
check_volt_type(dimm_populated, iic0_dimm_addr, num_dimm_banks);
#if defined(CONFIG_440_GX)
/*
* Soft-reset SDRAM controller.
*/
mtsdr(sdr_srst, SDR0_SRST_DMC);
mtsdr(sdr_srst, 0x00000000);
#endif
/*
* program 440GP SDRAM controller options (SDRAM0_CFG0)
*/

38
include/ppc440.h
View file

@ -893,6 +893,37 @@
#define SDR0_MFR_ECS_MASK 0x10000000
#define SDR0_MFR_ECS_INTERNAL 0x10000000
#define SDR0_SRST_BGO 0x80000000
#define SDR0_SRST_PLB 0x40000000
#define SDR0_SRST_EBC 0x20000000
#define SDR0_SRST_OPB 0x10000000
#define SDR0_SRST_UART0 0x08000000
#define SDR0_SRST_UART1 0x04000000
#define SDR0_SRST_IIC0 0x02000000
#define SDR0_SRST_IIC1 0x01000000
#define SDR0_SRST_GPIO 0x00800000
#define SDR0_SRST_GPT 0x00400000
#define SDR0_SRST_DMC 0x00200000
#define SDR0_SRST_PCI 0x00100000
#define SDR0_SRST_EMAC0 0x00080000
#define SDR0_SRST_EMAC1 0x00040000
#define SDR0_SRST_CPM 0x00020000
#define SDR0_SRST_IMU 0x00010000
#define SDR0_SRST_UIC01 0x00008000
#define SDR0_SRST_UICB2 0x00004000
#define SDR0_SRST_SRAM 0x00002000
#define SDR0_SRST_EBM 0x00001000
#define SDR0_SRST_BGI 0x00000800
#define SDR0_SRST_DMA 0x00000400
#define SDR0_SRST_DMAC 0x00000200
#define SDR0_SRST_MAL 0x00000100
#define SDR0_SRST_ZMII 0x00000080
#define SDR0_SRST_GPTR 0x00000040
#define SDR0_SRST_PPM 0x00000020
#define SDR0_SRST_EMAC2 0x00000010
#define SDR0_SRST_EMAC3 0x00000008
#define SDR0_SRST_RGMII 0x00000001
/*-----------------------------------------------------------------------------+
| Clocking
+-----------------------------------------------------------------------------*/
@ -1075,8 +1106,7 @@
#ifndef __ASSEMBLY__
typedef struct
{
typedef struct {
unsigned long pllFwdDivA;
unsigned long pllFwdDivB;
unsigned long pllFbkDiv;
@ -1092,7 +1122,7 @@ typedef struct
#endif /* _ASMLANGUAGE */
#define RESET_VECTOR 0xfffffffc
#define CACHELINE_MASK (CFG_CACHELINE_SIZE - 1) /* Address mask for cache
line aligned data. */
#define CACHELINE_MASK (CFG_CACHELINE_SIZE - 1) /* Address mask for */
/* cache line aligned data. */
#endif /* __PPC440_H__ */

4
net/net.c
View file

@ -506,8 +506,8 @@ restart:
thand_f *x;
#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)
# if defined(CFG_FAULT_ECHO_LINK_DOWN) &&
defined(CONFIG_STATUS_LED) &&
# if defined(CFG_FAULT_ECHO_LINK_DOWN) && \
defined(CONFIG_STATUS_LED) && \
defined(STATUS_LED_RED)
/*
* Echo the inverted link state to the fault LED.