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ARM: cache: implement a default weak flush_cache() function
Current many cpu use the same flush_cache() function, which just call the flush_dcache_range(). So implement a weak flush_cache() for all the cpus to use. In original weak flush_cache() in arch/arm/lib/cache.c, there has some code for ARM1136 & ARM926ejs. But in the arch/arm/cpu/arm1136/cpu.c and arch/arm/cpu/arm926ejs/cache.c, there implements a real flush_cache() function as well. That means the original code for ARM1136 & ARM926ejs in weak flush_cache() of arch/arm/lib/cache.c is totally useless. So in this patch remove such code in flush_cache() and only call flush_dcache_range(). Signed-off-by: Josh Wu <josh.wu@atmel.com>
This commit is contained in:
parent
387871a10e
commit
633b6ccedf
5 changed files with 5 additions and 60 deletions
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@ -110,11 +110,6 @@ void flush_dcache_range(unsigned long start, unsigned long stop)
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asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
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asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
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}
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}
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void flush_cache(unsigned long start, unsigned long size)
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{
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flush_dcache_range(start, start + size);
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}
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#else /* #ifndef CONFIG_SYS_DCACHE_OFF */
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#else /* #ifndef CONFIG_SYS_DCACHE_OFF */
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void invalidate_dcache_all(void)
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void invalidate_dcache_all(void)
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{
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{
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@ -123,10 +118,6 @@ void invalidate_dcache_all(void)
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void flush_dcache_all(void)
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void flush_dcache_all(void)
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{
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{
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}
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}
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void flush_cache(unsigned long start, unsigned long size)
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{
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}
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#endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
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#endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
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#if !defined(CONFIG_SYS_ICACHE_OFF) || !defined(CONFIG_SYS_DCACHE_OFF)
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#if !defined(CONFIG_SYS_ICACHE_OFF) || !defined(CONFIG_SYS_DCACHE_OFF)
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@ -69,11 +69,6 @@ void flush_dcache_range(unsigned long start, unsigned long stop)
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asm volatile("mcr p15, 0, %0, c7, c10, 4\n" : : "r"(0));
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asm volatile("mcr p15, 0, %0, c7, c10, 4\n" : : "r"(0));
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}
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}
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void flush_cache(unsigned long start, unsigned long size)
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{
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flush_dcache_range(start, start + size);
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}
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#else /* #ifndef CONFIG_SYS_DCACHE_OFF */
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#else /* #ifndef CONFIG_SYS_DCACHE_OFF */
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void invalidate_dcache_all(void)
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void invalidate_dcache_all(void)
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{
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{
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@ -82,10 +77,6 @@ void invalidate_dcache_all(void)
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void flush_dcache_all(void)
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void flush_dcache_all(void)
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{
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{
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}
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}
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void flush_cache(unsigned long start, unsigned long size)
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{
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}
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#endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
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#endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
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/*
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/*
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@ -286,15 +286,6 @@ void mmu_page_table_flush(unsigned long start, unsigned long stop)
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flush_dcache_range(start, stop);
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flush_dcache_range(start, stop);
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v7_inval_tlb();
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v7_inval_tlb();
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}
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}
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/*
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* Flush range from all levels of d-cache/unified-cache used:
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* Affects the range [start, start + size - 1]
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*/
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void flush_cache(unsigned long start, unsigned long size)
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{
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flush_dcache_range(start, start + size);
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}
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#else /* #ifndef CONFIG_SYS_DCACHE_OFF */
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#else /* #ifndef CONFIG_SYS_DCACHE_OFF */
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void invalidate_dcache_all(void)
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void invalidate_dcache_all(void)
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{
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{
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@ -308,10 +299,6 @@ void arm_init_before_mmu(void)
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{
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{
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}
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}
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void flush_cache(unsigned long start, unsigned long size)
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{
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}
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void mmu_page_table_flush(unsigned long start, unsigned long stop)
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void mmu_page_table_flush(unsigned long start, unsigned long stop)
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{
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{
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}
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}
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@ -253,11 +253,3 @@ void __weak enable_caches(void)
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icache_enable();
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icache_enable();
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dcache_enable();
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dcache_enable();
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}
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}
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/*
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* Flush range from all levels of d-cache/unified-cache
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*/
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void flush_cache(unsigned long start, unsigned long size)
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{
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flush_dcache_range(start, start + size);
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}
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@ -10,29 +10,13 @@
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#include <common.h>
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#include <common.h>
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#include <malloc.h>
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#include <malloc.h>
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/*
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* Flush range from all levels of d-cache/unified-cache.
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* Affects the range [start, start + size - 1].
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*/
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__weak void flush_cache(unsigned long start, unsigned long size)
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__weak void flush_cache(unsigned long start, unsigned long size)
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{
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{
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#if defined(CONFIG_CPU_ARM1136)
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flush_dcache_range(start, start + size);
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#if !defined(CONFIG_SYS_ICACHE_OFF)
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asm("mcr p15, 0, r1, c7, c5, 0"); /* invalidate I cache */
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#endif
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#if !defined(CONFIG_SYS_DCACHE_OFF)
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asm("mcr p15, 0, r1, c7, c14, 0"); /* Clean+invalidate D cache */
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#endif
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#endif /* CONFIG_CPU_ARM1136 */
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#ifdef CONFIG_CPU_ARM926EJS
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#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
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/* test and clean, page 2-23 of arm926ejs manual */
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asm("0: mrc p15, 0, r15, c7, c10, 3\n\t" "bne 0b\n" : : : "memory");
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/* disable write buffer as well (page 2-22) */
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asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
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#endif
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#endif /* CONFIG_CPU_ARM926EJS */
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return;
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}
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}
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/*
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/*
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