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* Patch by Andr Schwarz, 8 Dec 2003:

Browse source 
fixes for Davicom DM9102A Ethernet Chip (#define CONFIG_TULIP_FIX_DAVICOM):
  - TX and RX deskriptors must be quad-word aligned
  - does not work with only one TX deskriptor
  - standard reset method does not work

* Patch by Masami Komiya, 08 Dec 2003:
  add RTL8139 ethernet driver

* Patches by Ed Okerson, 07 Dec 2003:
  - fix ethernet for the AU1x00 processors in little-endian mode.
  - extend memsetup.S for the AU1x00 processors in BE and LE modes
This commit is contained in:
wdenk 2004-01-02 15:01:32 +00:00
parent d4ca31c40e
commit 63f3491242
7 changed files with 941 additions and 95 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

13
CHANGELOG
View file

@ -2,6 +2,19 @@
Changes since U-Boot 1.0.0:
======================================================================
* Patch by André Schwarz, 8 Dec 2003:
fixes for Davicom DM9102A Ethernet Chip (#define CONFIG_TULIP_FIX_DAVICOM):
- TX and RX deskriptors must be quad-word aligned
- does not work with only one TX deskriptor
- standard reset method does not work
* Patch by Masami Komiya, 08 Dec 2003:
add RTL8139 ethernet driver
* Patches by Ed Okerson, 07 Dec 2003:
- fix ethernet for the AU1x00 processors in little-endian mode.
- extend memsetup.S for the AU1x00 processors in BE and LE modes
* Minor code cleanup (coding style)
* Patch by Reinhard Meyer, 30 Dec 2003:

414
board/dbau1x00/memsetup.S
View file

@ -4,114 +4,358 @@
#include <version.h>
#include <asm/regdef.h>
#include <asm/au1x00.h>
#include <asm/mipsregs.h>
#define AU1500_SYS_ADDR 0xB1900000
#define sys_endian 0x0038
#define CP0_Config0 $16
#define MEM_1MS ((396000000/1000000) * 1000)
.text
.set noreorder
.set mips32
.globl memsetup
memsetup:
/* First setup pll:s to make serial work ok */
/* We have a 12 MHz crystal */
li t0, SYS_CPUPLL
li t1, 0x21 /* 396 MHz */
sw t1, 0(t0)
sync
/*
* Step 1) Establish CPU endian mode.
* Db1500-specific:
* Switch S1.1 Off(bit7 reads 1) is Little Endian
* Switch S1.1 On (bit7 reads 0) is Big Endian
*/
li t0, MEM_STCFG1
li t1, 0x00000080
sw t1, 0(t0)
li t0, MEM_STTIME1
li t1, 0x22080a20
sw t1, 0(t0)
li t0, MEM_STADDR1
li t1, 0x10c03f00
sw t1, 0(t0)
li t0, 0xAE000008
lw t1,0(t0)
andi t1,t1,0x80
beq zero,t1,big_endian
nop
little_endian:
/* Change Au1 core to little endian */
li t0, AU1500_SYS_ADDR
li t1, 1
sw t1, sys_endian(t0)
mfc0 t2, CP0_CONFIG
mtc0 t2, CP0_CONFIG
nop
nop
/* Big Endian is default so nothing to do but fall through */
big_endian:
/*
* Step 2) Establish Status Register
* (set BEV, clear ERL, clear EXL, clear IE)
*/
li t1, 0x00400000
mtc0 t1, CP0_STATUS
/*
* Step 3) Establish CP0 Config0
* (set OD, set K0=3)
*/
li t1, 0x00080003
mtc0 t1, CP0_CONFIG
/*
* Step 4) Disable Watchpoint facilities
*/
li t1, 0x00000000
mtc0 t1, CP0_WATCHLO
mtc0 t1, CP0_IWATCHLO
/*
* Step 5) Disable the performance counters
*/
mtc0 zero, CP0_PERFORMANCE
nop
/*
* Step 6) Establish EJTAG Debug register
*/
mtc0 zero, CP0_DEBUG
nop
/*
* Step 7) Establish Cause
* (set IV bit)
*/
li t1, 0x00800000
mtc0 t1, CP0_CAUSE
/* Establish Wired (and Random) */
mtc0 zero, CP0_WIRED
nop
/* First setup pll:s to make serial work ok */
/* We have a 12 MHz crystal */
li t0, SYS_CPUPLL
li t1, 0x21 /* 396 MHz */
sw t1, 0(t0)
sync
nop
nop
/* wait 1mS for clocks to settle */
li t1, MEM_1MS
1: add t1, -1
bne t1, zero, 1b
nop
/* Setup AUX PLL */
li t0, SYS_AUXPLL
li t1, 8 /* 96 MHz */
sw t1, 0(t0) /* aux pll */
sync
/* SDCS 0,1 SDRAM */
li t0, MEM_SDMODE0
li t1, 0x005522AA
sw t1, 0(t0)
li t0, MEM_SDMODE1
li t1, 0x005522AA
sw t1, 0(t0)
li t0, MEM_SDADDR0
li t1, 0x001003F8
sw t1, 0(t0)
li t0, MEM_SDADDR1
li t1, 0x001023F8
sw t1, 0(t0)
sync
li t0, MEM_SDREFCFG
li t1, 0x64000C24 /* Disable */
sw t1, 0(t0)
sync
li t0, MEM_SDPRECMD
sw zero, 0(t0)
sync
li t0, MEM_SDAUTOREF
sw zero, 0(t0)
sync
sw zero, 0(t0)
sync
li t0, MEM_SDREFCFG
li t1, 0x66000C24 /* Enable */
sw t1, 0(t0)
sync
li t0, MEM_SDWRMD0
li t1, 0x00000033
sw t1, 0(t0)
sync
li t0, MEM_SDWRMD1
li t1, 0x00000033
sw t1, 0(t0)
li t0, SYS_AUXPLL
li t1, 0x20 /* 96 MHz */
sw t1, 0(t0) /* aux pll */
sync
/* Static memory controller */
/* RCE0 AMD 29LV640M MirrorBit Flash */
li t0, MEM_STCFG0
li t1, 0x00000003
sw t1, 0(t0)
li t0, MEM_STCFG0
li t1, 0x00000013
sw t1, 0(t0)
li t0, MEM_STTIME0
li t1, 0x22080b20
sw t1, 0(t0)
li t0, MEM_STTIME0
li t1, 0x040181D7
sw t1, 0(t0)
li t0, MEM_STADDR0
li t1, 0x11E03F80
sw t1, 0(t0)
li t0, MEM_STADDR0
li t1, 0x11E03F80
sw t1, 0(t0)
/* RCE1 CPLD Board Logic */
li t0, MEM_STCFG1
li t1, 0x00000080
sw t1, 0(t0)
li t0, MEM_STCFG1
li t1, 0x00000080
sw t1, 0(t0)
li t0, MEM_STTIME1
li t1, 0x22080a20
sw t1, 0(t0)
li t0, MEM_STTIME1
li t1, 0x22080a20
sw t1, 0(t0)
li t0, MEM_STADDR1
li t1, 0x10c03f00
sw t1, 0(t0)
li t0, MEM_STADDR1
li t1, 0x10c03f00
sw t1, 0(t0)
/* RCE2 CPLD Board Logic */
li t0, MEM_STCFG2
li t1, 0x00000000
sw t1, 0(t0)
li t0, MEM_STTIME2
li t1, 0x00000000
sw t1, 0(t0)
li t0, MEM_STADDR2
li t1, 0x00000000
sw t1, 0(t0)
/* RCE3 PCMCIA 250ns */
li t0, MEM_STCFG3
li t1, 0x00000002
sw t1, 0(t0)
li t0, MEM_STCFG3
li t1, 0x00000002
sw t1, 0(t0)
li t0, MEM_STTIME3
li t1, 0x280E3E07
sw t1, 0(t0)
li t0, MEM_STADDR3
li t1, 0x10000000
sw t1, 0(t0)
sync
/* Set peripherals to a known state */
li t0, IC0_CFG0CLR
li t1, 0xFFFFFFFF
sw t1, 0(t0)
li t0, IC0_CFG0CLR
sw t1, 0(t0)
li t0, IC0_CFG1CLR
sw t1, 0(t0)
li t0, IC0_CFG2CLR
sw t1, 0(t0)
li t0, IC0_SRCSET
sw t1, 0(t0)
li t0, IC0_ASSIGNSET
sw t1, 0(t0)
li t0, IC0_WAKECLR
sw t1, 0(t0)
li t0, IC0_RISINGCLR
sw t1, 0(t0)
li t0, IC0_FALLINGCLR
sw t1, 0(t0)
li t0, IC0_TESTBIT
li t1, 0x00000000
sw t1, 0(t0)
sync
li t0, IC1_CFG0CLR
li t1, 0xFFFFFFFF
sw t1, 0(t0)
li t0, IC1_CFG0CLR
sw t1, 0(t0)
li t0, IC1_CFG1CLR
sw t1, 0(t0)
li t0, IC1_CFG2CLR
sw t1, 0(t0)
li t0, IC1_SRCSET
sw t1, 0(t0)
li t0, IC1_ASSIGNSET
sw t1, 0(t0)
li t0, IC1_WAKECLR
sw t1, 0(t0)
li t0, IC1_RISINGCLR
sw t1, 0(t0)
li t0, IC1_FALLINGCLR
sw t1, 0(t0)
li t0, IC1_TESTBIT
li t1, 0x00000000
sw t1, 0(t0)
sync
li t0, SYS_FREQCTRL0
li t1, 0x00000000
sw t1, 0(t0)
li t0, SYS_FREQCTRL1
li t1, 0x00000000
sw t1, 0(t0)
li t0, SYS_CLKSRC
li t1, 0x00000000
sw t1, 0(t0)
li t0, SYS_PININPUTEN
li t1, 0x00000000
sw t1, 0(t0)
sync
li t0, 0xB1100100
li t1, 0x00000000
sw t1, 0(t0)
li t0, 0xB1400100
li t1, 0x00000000
sw t1, 0(t0)
li t0, MEM_STTIME3
li t1, 0x280E3E07
sw t1, 0(t0)
li t0, SYS_WAKEMSK
li t1, 0x00000000
sw t1, 0(t0)
li t0, MEM_STADDR3
li t1, 0x10000000
sw t1, 0(t0)
li t0, SYS_WAKESRC
li t1, 0x00000000
sw t1, 0(t0)
/* wait 1mS before setup */
li t1, MEM_1MS
1: add t1, -1
bne t1, zero, 1b
nop
/* SDCS 0,1 SDRAM */
li t0, MEM_SDMODE0
li t1, 0x005522AA
sw t1, 0(t0)
li t0, MEM_SDMODE1
li t1, 0x005522AA
sw t1, 0(t0)
li t0, MEM_SDMODE2
li t1, 0x00000000
sw t1, 0(t0)
li t0, MEM_SDADDR0
li t1, 0x001003F8
sw t1, 0(t0)
li t0, MEM_SDADDR1
li t1, 0x001023F8
sw t1, 0(t0)
li t0, MEM_SDADDR2
li t1, 0x00000000
sw t1, 0(t0)
sync
li t0, MEM_SDREFCFG
li t1, 0x64000C24 /* Disable */
sw t1, 0(t0)
sync
li t0, MEM_SDPRECMD
sw zero, 0(t0)
sync
li t0, MEM_SDAUTOREF
sw zero, 0(t0)
sync
sw zero, 0(t0)
sync
li t0, MEM_SDREFCFG
li t1, 0x66000C24 /* Enable */
sw t1, 0(t0)
sync
li t0, MEM_SDWRMD0
li t1, 0x00000033
sw t1, 0(t0)
sync
li t0, MEM_SDWRMD1
li t1, 0x00000033
sw t1, 0(t0)
sync
/* wait 1mS after setup */
li t1, MEM_1MS
1: add t1, -1
bne t1, zero, 1b
nop
li t0, SYS_PINFUNC
li t1, 0x00008080
sw t1, 0(t0)
li t0, SYS_TRIOUTCLR
li t1, 0x00001FFF
sw t1, 0(t0)
li t0, SYS_OUTPUTCLR
li t1, 0x00008000
sw t1, 0(t0)
sync
j ra

9
cpu/mips/au1x00_eth.c
View file

@ -187,19 +187,24 @@ static int au1x00_init(struct eth_device* dev, bd_t * bd){
}
/* Put mac addr in little endian */
/* FIXME Check this for little endian mode */
#define ea eth_get_dev()->enetaddr
*mac_addr_high = (ea[5] << 8) | (ea[4] ) ;
*mac_addr_low = (ea[3] << 24) | (ea[2] << 16) |
(ea[1] << 8) | (ea[0] ) ;
#undef ea
*mac_mcast_low = 0;
*mac_mcast_high = 0;
/* Make sure the MAC buffer is in the correct endian mode */
#ifdef __LITTLE_ENDIAN
*mac_ctrl = MAC_FULL_DUPLEX;
udelay(1);
*mac_ctrl = MAC_FULL_DUPLEX|MAC_RX_ENABLE|MAC_TX_ENABLE;
#else
*mac_ctrl = MAC_BIG_ENDIAN|MAC_FULL_DUPLEX;
udelay(1);
*mac_ctrl = MAC_BIG_ENDIAN|MAC_FULL_DUPLEX|MAC_RX_ENABLE|MAC_TX_ENABLE;
#endif
return(1);
}

2
drivers/Makefile
View file

@ -36,7 +36,7 @@ OBJS = 3c589.o 5701rls.o ali512x.o \
ns16550.o ns8382x.o ns87308.o \
pci.o pci_auto.o pci_indirect.o \
pcnet.o plb2800_eth.o \
rtl8019.o \
rtl8019.o rtl8139.o \
s3c24x0_i2c.o sed13806.o serial.o \
serial_max3100.o \
smc91111.o smiLynxEM.o sym53c8xx.o \

55
drivers/dc2114x.c
View file

@ -98,6 +98,15 @@
#define POLL_DEMAND 1
#ifdef CONFIG_TULIP_FIX_DAVICOM
#define RESET_DM9102(dev) {\
unsigned long i;\
i=INL(dev, 0x0);\
udelay(1000);\
OUTL(dev, i | BMR_SWR, DE4X5_BMR);\
udelay(1000);\
}
#else
#define RESET_DE4X5(dev) {\
int i;\
i=INL(dev, DE4X5_BMR);\
@ -109,6 +118,7 @@
for (i=0;i<5;i++) {INL(dev, DE4X5_BMR); udelay(10000);}\
udelay(1000);\
}
#endif
#define START_DE4X5(dev) {\
s32 omr; \
@ -125,7 +135,11 @@
}
#define NUM_RX_DESC PKTBUFSRX
#define NUM_TX_DESC 1 /* Number of TX descriptors */
#ifndef CONFIG_TULIP_FIX_DAVICOM
#define NUM_TX_DESC 1 /* Number of TX descriptors */
#else
#define NUM_TX_DESC 4
#endif
#define RX_BUFF_SZ PKTSIZE_ALIGN
#define TOUT_LOOP 1000000
@ -133,7 +147,6 @@
#define SETUP_FRAME_LEN 192
#define ETH_ALEN 6
struct de4x5_desc {
volatile s32 status;
u32 des1;
@ -141,8 +154,8 @@ struct de4x5_desc {
u32 next;
};
static struct de4x5_desc rx_ring[NUM_RX_DESC]; /* RX descriptor ring */
static struct de4x5_desc tx_ring[NUM_TX_DESC]; /* TX descriptor ring */
static struct de4x5_desc rx_ring[NUM_RX_DESC] __attribute__ ((aligned(32))); /* RX descriptor ring */
static struct de4x5_desc tx_ring[NUM_TX_DESC] __attribute__ ((aligned(32))); /* TX descriptor ring */
static int rx_new; /* RX descriptor ring pointer */
static int tx_new; /* TX descriptor ring pointer */
@ -188,6 +201,9 @@ static void OUTL(struct eth_device* dev, int command, u_long addr)
static struct pci_device_id supported[] = {
{ PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TULIP_FAST },
{ PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21142 },
#ifdef CONFIG_TULIP_FIX_DAVICOM
{ PCI_VENDOR_ID_DAVICOM, PCI_DEVICE_ID_DAVICOM_DM9102A },
#endif
{ }
};
@ -211,10 +227,12 @@ int dc21x4x_initialize(bd_t *bis)
/* Get the chip configuration revision register. */
pci_read_config_dword(devbusfn, PCI_REVISION_ID, &cfrv);
#ifndef CONFIG_TULIP_FIX_DAVICOM
if ((cfrv & CFRV_RN) < DC2114x_BRK ) {
printf("Error: The chip is not DC21143.\n");
continue;
}
#endif
pci_read_config_word(devbusfn, PCI_COMMAND, &status);
status |=
@ -265,7 +283,12 @@ int dc21x4x_initialize(bd_t *bis)
dev = (struct eth_device*) malloc(sizeof *dev);
sprintf(dev->name, "dc21x4x#%d", card_number);
#ifdef CONFIG_TULIP_FIX_DAVICOM
sprintf(dev->name, "Davicom#%d", card_number);
#else
sprintf(dev->name, "dc21x4x#%d", card_number);
#endif
#ifdef CONFIG_TULIP_USE_IO
dev->iobase = pci_io_to_phys(devbusfn, iobase);
#else
@ -282,8 +305,9 @@ int dc21x4x_initialize(bd_t *bis)
udelay(10 * 1000);
read_hw_addr(dev, bis);
#ifndef CONFIG_TULIP_FIX_DAVICOM
read_hw_addr(dev, bis);
#endif
eth_register(dev);
card_number++;
@ -300,7 +324,11 @@ static int dc21x4x_init(struct eth_device* dev, bd_t* bis)
/* Ensure we're not sleeping. */
pci_write_config_byte(devbusfn, PCI_CFDA_PSM, WAKEUP);
#ifdef CONFIG_TULIP_FIX_DAVICOM
RESET_DM9102(dev);
#else
RESET_DE4X5(dev);
#endif
if ((INL(dev, DE4X5_STS) & (STS_TS | STS_RS)) != 0) {
printf("Error: Cannot reset ethernet controller.\n");
@ -317,14 +345,23 @@ static int dc21x4x_init(struct eth_device* dev, bd_t* bis)
rx_ring[i].status = cpu_to_le32(R_OWN);
rx_ring[i].des1 = cpu_to_le32(RX_BUFF_SZ);
rx_ring[i].buf = cpu_to_le32(phys_to_bus((u32) NetRxPackets[i]));
#ifdef CONFIG_TULIP_FIX_DAVICOM
rx_ring[i].next = cpu_to_le32(phys_to_bus((u32) &rx_ring[(i+1) % NUM_RX_DESC]));
#else
rx_ring[i].next = 0;
#endif
}
for (i=0; i < NUM_TX_DESC; i++) {
tx_ring[i].status = 0;
tx_ring[i].des1 = 0;
tx_ring[i].buf = 0;
#ifdef CONFIG_TULIP_FIX_DAVICOM
tx_ring[i].next = cpu_to_le32(phys_to_bus((u32) &tx_ring[(i+1) % NUM_TX_DESC]));
#else
tx_ring[i].next = 0;
#endif
}
rxRingSize = NUM_RX_DESC;
@ -383,12 +420,14 @@ static int dc21x4x_send(struct eth_device* dev, volatile void *packet, int lengt
printf("TX error status = 0x%08X\n",
le32_to_cpu(tx_ring[tx_new].status));
#endif
tx_ring[tx_new].status = 0x0;
goto Done;
}
status = length;
Done:
tx_new = (tx_new+1) % NUM_TX_DESC;
return status;
}
@ -485,6 +524,8 @@ static void send_setup_frame(struct eth_device* dev, bd_t *bis)
if (le32_to_cpu(tx_ring[tx_new].status) != 0x7FFFFFFF) {
printf("TX error status2 = 0x%08X\n", le32_to_cpu(tx_ring[tx_new].status));
}
tx_new = (tx_new+1) % NUM_TX_DESC;
Done:
return;
}

539
drivers/rtl8139.c Normal file
View file

@ -0,0 +1,539 @@
/*
* rtl8139.c : U-Boot driver for the RealTek RTL8139
*
* Masami Komiya (mkomiya@sonare.it)
*
* Most part is taken from rtl8139.c of etherboot
*
*/
/* rtl8139.c - etherboot driver for the Realtek 8139 chipset
ported from the linux driver written by Donald Becker
by Rainer Bawidamann (Rainer.Bawidamann@informatik.uni-ulm.de) 1999
This software may be used and distributed according to the terms
of the GNU Public License, incorporated herein by reference.
changes to the original driver:
- removed support for interrupts, switching to polling mode (yuck!)
- removed support for the 8129 chip (external MII)
*/
/*********************************************************************/
/* Revision History */
/*********************************************************************/
/*
28 Dec 2002 ken_yap@users.sourceforge.net (Ken Yap)
Put in virt_to_bus calls to allow Etherboot relocation.
06 Apr 2001 ken_yap@users.sourceforge.net (Ken Yap)
Following email from Hyun-Joon Cha, added a disable routine, otherwise
NIC remains live and can crash the kernel later.
4 Feb 2000 espenlaub@informatik.uni-ulm.de (Klaus Espenlaub)
Shuffled things around, removed the leftovers from the 8129 support
that was in the Linux driver and added a bit more 8139 definitions.
Moved the 8K receive buffer to a fixed, available address outside the
0x98000-0x9ffff range. This is a bit of a hack, but currently the only
way to make room for the Etherboot features that need substantial amounts
of code like the ANSI console support. Currently the buffer is just below
0x10000, so this even conforms to the tagged boot image specification,
which reserves the ranges 0x00000-0x10000 and 0x98000-0xA0000. My
interpretation of this "reserved" is that Etherboot may do whatever it
likes, as long as its environment is kept intact (like the BIOS
variables). Hopefully fixed rtl_poll() once and for all. The symptoms
were that if Etherboot was left at the boot menu for several minutes, the
first eth_poll failed. Seems like I am the only person who does this.
First of all I fixed the debugging code and then set out for a long bug
hunting session. It took me about a week full time work - poking around
various places in the driver, reading Don Becker's and Jeff Garzik's Linux
driver and even the FreeBSD driver (what a piece of crap!) - and
eventually spotted the nasty thing: the transmit routine was acknowledging
each and every interrupt pending, including the RxOverrun and RxFIFIOver
interrupts. This confused the RTL8139 thoroughly. It destroyed the
Rx ring contents by dumping the 2K FIFO contents right where we wanted to
get the next packet. Oh well, what fun.
18 Jan 2000 mdc@thinguin.org (Marty Connor)
Drastically simplified error handling. Basically, if any error
in transmission or reception occurs, the card is reset.
Also, pointed all transmit descriptors to the same buffer to
save buffer space. This should decrease driver size and avoid
corruption because of exceeding 32K during runtime.
28 Jul 1999 (Matthias Meixner - meixner@rbg.informatik.tu-darmstadt.de)
rtl_poll was quite broken: it used the RxOK interrupt flag instead
of the RxBufferEmpty flag which often resulted in very bad
transmission performace - below 1kBytes/s.
*/
#include <common.h>
#include <malloc.h>
#include <net.h>
#include <asm/io.h>
#include <pci.h>
#ifdef __MIPS__
static unsigned long mips_io_port_base = 0;
#endif
#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) && \
defined(CONFIG_RTL8139)
#define TICKS_PER_SEC CFG_HZ
#define TICKS_PER_MS (TICKS_PER_SEC/1000)
#define RTL_TIMEOUT (1*TICKS_PER_SEC)
#define ETH_FRAME_LEN 1514
#define ETH_ALEN 6
#define ETH_ZLEN 60
/* PCI Tuning Parameters
Threshold is bytes transferred to chip before transmission starts. */
#define TX_FIFO_THRESH 256 /* In bytes, rounded down to 32 byte units. */
#define RX_FIFO_THRESH 4 /* Rx buffer level before first PCI xfer. */
#define RX_DMA_BURST 4 /* Maximum PCI burst, '4' is 256 bytes */
#define TX_DMA_BURST 4 /* Calculate as 16<<val. */
#define NUM_TX_DESC 4 /* Number of Tx descriptor registers. */
#define TX_BUF_SIZE ETH_FRAME_LEN /* FCS is added by the chip */
#define RX_BUF_LEN_IDX 0 /* 0, 1, 2 is allowed - 8,16,32K rx buffer */
#define RX_BUF_LEN (8192 << RX_BUF_LEN_IDX)
#undef DEBUG_TX
#undef DEBUG_RX
#define currticks() get_timer(0)
#define bus_to_phys(a) pci_mem_to_phys((pci_dev_t)dev->priv, a)
#define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)dev->priv, a)
/* Symbolic offsets to registers. */
enum RTL8139_registers {
MAC0=0, /* Ethernet hardware address. */
MAR0=8, /* Multicast filter. */
TxStatus0=0x10, /* Transmit status (four 32bit registers). */
TxAddr0=0x20, /* Tx descriptors (also four 32bit). */
RxBuf=0x30, RxEarlyCnt=0x34, RxEarlyStatus=0x36,
ChipCmd=0x37, RxBufPtr=0x38, RxBufAddr=0x3A,
IntrMask=0x3C, IntrStatus=0x3E,
TxConfig=0x40, RxConfig=0x44,
Timer=0x48, /* general-purpose counter. */
RxMissed=0x4C, /* 24 bits valid, write clears. */
Cfg9346=0x50, Config0=0x51, Config1=0x52,
TimerIntrReg=0x54, /* intr if gp counter reaches this value */
MediaStatus=0x58,
Config3=0x59,
MultiIntr=0x5C,
RevisionID=0x5E, /* revision of the RTL8139 chip */
TxSummary=0x60,
MII_BMCR=0x62, MII_BMSR=0x64, NWayAdvert=0x66, NWayLPAR=0x68,
NWayExpansion=0x6A,
DisconnectCnt=0x6C, FalseCarrierCnt=0x6E,
NWayTestReg=0x70,
RxCnt=0x72, /* packet received counter */
CSCR=0x74, /* chip status and configuration register */
PhyParm1=0x78,TwisterParm=0x7c,PhyParm2=0x80, /* undocumented */
/* from 0x84 onwards are a number of power management/wakeup frame
* definitions we will probably never need to know about. */
};
enum ChipCmdBits {
CmdReset=0x10, CmdRxEnb=0x08, CmdTxEnb=0x04, RxBufEmpty=0x01, };
/* Interrupt register bits, using my own meaningful names. */
enum IntrStatusBits {
PCIErr=0x8000, PCSTimeout=0x4000, CableLenChange= 0x2000,
RxFIFOOver=0x40, RxUnderrun=0x20, RxOverflow=0x10,
TxErr=0x08, TxOK=0x04, RxErr=0x02, RxOK=0x01,
};
enum TxStatusBits {
TxHostOwns=0x2000, TxUnderrun=0x4000, TxStatOK=0x8000,
TxOutOfWindow=0x20000000, TxAborted=0x40000000,
TxCarrierLost=0x80000000,
};
enum RxStatusBits {
RxMulticast=0x8000, RxPhysical=0x4000, RxBroadcast=0x2000,
RxBadSymbol=0x0020, RxRunt=0x0010, RxTooLong=0x0008, RxCRCErr=0x0004,
RxBadAlign=0x0002, RxStatusOK=0x0001,
};
enum MediaStatusBits {
MSRTxFlowEnable=0x80, MSRRxFlowEnable=0x40, MSRSpeed10=0x08,
MSRLinkFail=0x04, MSRRxPauseFlag=0x02, MSRTxPauseFlag=0x01,
};
enum MIIBMCRBits {
BMCRReset=0x8000, BMCRSpeed100=0x2000, BMCRNWayEnable=0x1000,
BMCRRestartNWay=0x0200, BMCRDuplex=0x0100,
};
enum CSCRBits {
CSCR_LinkOKBit=0x0400, CSCR_LinkChangeBit=0x0800,
CSCR_LinkStatusBits=0x0f000, CSCR_LinkDownOffCmd=0x003c0,
CSCR_LinkDownCmd=0x0f3c0,
};
/* Bits in RxConfig. */
enum rx_mode_bits {
RxCfgWrap=0x80,
AcceptErr=0x20, AcceptRunt=0x10, AcceptBroadcast=0x08,
AcceptMulticast=0x04, AcceptMyPhys=0x02, AcceptAllPhys=0x01,
};
static int ioaddr;
static unsigned int cur_rx,cur_tx;
/* The RTL8139 can only transmit from a contiguous, aligned memory block. */
static unsigned char tx_buffer[TX_BUF_SIZE] __attribute__((aligned(4)));
static unsigned char rx_ring[RX_BUF_LEN+16] __attribute__((aligned(4)));
static int rtl8139_probe(struct eth_device *dev, bd_t *bis);
static int read_eeprom(int location, int addr_len);
static void rtl_reset(struct eth_device *dev);
static int rtl_transmit(struct eth_device *dev, volatile void *packet, int length);
static int rtl_poll(struct eth_device *dev);
static void rtl_disable(struct eth_device *dev);
static struct pci_device_id supported[] = {
{PCI_VENDOR_ID_REALTEK, PCI_DEVICE_ID_REALTEK_8139},
{}
};
int rtl8139_initialize(bd_t *bis)
{
pci_dev_t devno;
int card_number = 0;
struct eth_device *dev;
u32 iobase;
int idx=0;
while(1){
/* Find RTL8139 */
if ((devno = pci_find_devices(supported, idx++)) < 0)
break;
pci_read_config_dword(devno, PCI_BASE_ADDRESS_1, &iobase);
iobase &= ~0xf;
debug ("rtl8139: REALTEK RTL8139 @0x%x\n", iobase);
dev = (struct eth_device *)malloc(sizeof *dev);
sprintf (dev->name, "RTL8139#%d", card_number);
dev->priv = (void *) devno;
dev->iobase = (int)bus_to_phys(iobase);
dev->init = rtl8139_probe;
dev->halt = rtl_disable;
dev->send = rtl_transmit;
dev->recv = rtl_poll;
eth_register (dev);
card_number++;
pci_write_config_byte (devno, PCI_LATENCY_TIMER, 0x20);
udelay (10 * 1000);
}
return card_number;
}
static int rtl8139_probe(struct eth_device *dev, bd_t *bis)
{
int i;
int speed10, fullduplex;
int addr_len;
unsigned short *ap = (unsigned short *)dev->enetaddr;
ioaddr = dev->iobase;
/* Bring the chip out of low-power mode. */
outb(0x00, ioaddr + Config1);
addr_len = read_eeprom(0,8) == 0x8129 ? 8 : 6;
for (i = 0; i < 3; i++)
*ap++ = read_eeprom(i + 7, addr_len);
speed10 = inb(ioaddr + MediaStatus) & MSRSpeed10;
fullduplex = inw(ioaddr + MII_BMCR) & BMCRDuplex;
rtl_reset(dev);
if (inb(ioaddr + MediaStatus) & MSRLinkFail) {
printf("Cable not connected or other link failure\n");
return(0);
}
return 1;
}
/* Serial EEPROM section. */
/* EEPROM_Ctrl bits. */
#define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */
#define EE_CS 0x08 /* EEPROM chip select. */
#define EE_DATA_WRITE 0x02 /* EEPROM chip data in. */
#define EE_WRITE_0 0x00
#define EE_WRITE_1 0x02
#define EE_DATA_READ 0x01 /* EEPROM chip data out. */
#define EE_ENB (0x80 | EE_CS)
/*
Delay between EEPROM clock transitions.
No extra delay is needed with 33Mhz PCI, but 66Mhz may change this.
*/
#define eeprom_delay() inl(ee_addr)
/* The EEPROM commands include the alway-set leading bit. */
#define EE_WRITE_CMD (5)
#define EE_READ_CMD (6)
#define EE_ERASE_CMD (7)
static int read_eeprom(int location, int addr_len)
{
int i;
unsigned int retval = 0;
long ee_addr = ioaddr + Cfg9346;
int read_cmd = location | (EE_READ_CMD << addr_len);
outb(EE_ENB & ~EE_CS, ee_addr);
outb(EE_ENB, ee_addr);
eeprom_delay();
/* Shift the read command bits out. */
for (i = 4 + addr_len; i >= 0; i--) {
int dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
outb(EE_ENB | dataval, ee_addr);
eeprom_delay();
outb(EE_ENB | dataval | EE_SHIFT_CLK, ee_addr);
eeprom_delay();
}
outb(EE_ENB, ee_addr);
eeprom_delay();
for (i = 16; i > 0; i--) {
outb(EE_ENB | EE_SHIFT_CLK, ee_addr);
eeprom_delay();
retval = (retval << 1) | ((inb(ee_addr) & EE_DATA_READ) ? 1 : 0);
outb(EE_ENB, ee_addr);
eeprom_delay();
}
/* Terminate the EEPROM access. */
outb(~EE_CS, ee_addr);
eeprom_delay();
return retval;
}
static const unsigned int rtl8139_rx_config =
(RX_BUF_LEN_IDX << 11) |
(RX_FIFO_THRESH << 13) |
(RX_DMA_BURST << 8);
static void set_rx_mode(struct eth_device *dev) {
unsigned int mc_filter[2];
int rx_mode;
/* !IFF_PROMISC */
rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
mc_filter[1] = mc_filter[0] = 0xffffffff;
outl(rtl8139_rx_config | rx_mode, ioaddr + RxConfig);
outl(mc_filter[0], ioaddr + MAR0 + 0);
outl(mc_filter[1], ioaddr + MAR0 + 4);
}
static void rtl_reset(struct eth_device *dev)
{
int i;
outb(CmdReset, ioaddr + ChipCmd);
cur_rx = 0;
cur_tx = 0;
/* Give the chip 10ms to finish the reset. */
for (i=0; i<100; ++i){
if ((inb(ioaddr + ChipCmd) & CmdReset) == 0) break;
udelay (100); /* wait 100us */
}
for (i = 0; i < ETH_ALEN; i++)
outb(dev->enetaddr[i], ioaddr + MAC0 + i);
/* Must enable Tx/Rx before setting transfer thresholds! */
outb(CmdRxEnb | CmdTxEnb, ioaddr + ChipCmd);
outl((RX_FIFO_THRESH<<13) | (RX_BUF_LEN_IDX<<11) | (RX_DMA_BURST<<8),
ioaddr + RxConfig); /* accept no frames yet! */
outl((TX_DMA_BURST<<8)|0x03000000, ioaddr + TxConfig);
/* The Linux driver changes Config1 here to use a different LED pattern
* for half duplex or full/autodetect duplex (for full/autodetect, the
* outputs are TX/RX, Link10/100, FULL, while for half duplex it uses
* TX/RX, Link100, Link10). This is messy, because it doesn't match
* the inscription on the mounting bracket. It should not be changed
* from the configuration EEPROM default, because the card manufacturer
* should have set that to match the card. */
#ifdef DEBUG_RX
printf("rx ring address is %X\n",(unsigned long)rx_ring);
#endif
outl(phys_to_bus((int)rx_ring), ioaddr + RxBuf);
/* If we add multicast support, the MAR0 register would have to be
* initialized to 0xffffffffffffffff (two 32 bit accesses). Etherboot
* only needs broadcast (for ARP/RARP/BOOTP/DHCP) and unicast. */
outb(CmdRxEnb | CmdTxEnb, ioaddr + ChipCmd);
outl(rtl8139_rx_config, ioaddr + RxConfig);
/* Start the chip's Tx and Rx process. */
outl(0, ioaddr + RxMissed);
/* set_rx_mode */
set_rx_mode(dev);
/* Disable all known interrupts by setting the interrupt mask. */
outw(0, ioaddr + IntrMask);
}
static int rtl_transmit(struct eth_device *dev, volatile void *packet, int length)
{
unsigned int status, to;
unsigned long txstatus;
unsigned int len = length;
ioaddr = dev->iobase;
memcpy((char *)tx_buffer, (char *)packet, (int)length);
#ifdef DEBUG_TX
printf("sending %d bytes\n", len);
#endif
/* Note: RTL8139 doesn't auto-pad, send minimum payload (another 4
* bytes are sent automatically for the FCS, totalling to 64 bytes). */
while (len < ETH_ZLEN) {
tx_buffer[len++] = '\0';
}
outl(phys_to_bus((int)tx_buffer), ioaddr + TxAddr0 + cur_tx*4);
outl(((TX_FIFO_THRESH<<11) & 0x003f0000) | len,
ioaddr + TxStatus0 + cur_tx*4);
to = currticks() + RTL_TIMEOUT;
do {
status = inw(ioaddr + IntrStatus);
/* Only acknlowledge interrupt sources we can properly handle
* here - the RxOverflow/RxFIFOOver MUST be handled in the
* rtl_poll() function. */
outw(status & (TxOK | TxErr | PCIErr), ioaddr + IntrStatus);
if ((status & (TxOK | TxErr | PCIErr)) != 0) break;
} while (currticks() < to);
txstatus = inl(ioaddr + TxStatus0 + cur_tx*4);
if (status & TxOK) {
cur_tx = (cur_tx + 1) % NUM_TX_DESC;
#ifdef DEBUG_TX
printf("tx done (%d ticks), status %hX txstatus %X\n",
to-currticks(), status, txstatus);
#endif
return length;
} else {
#ifdef DEBUG_TX
printf("tx timeout/error (%d ticks), status %hX txstatus %X\n",
currticks()-to, status, txstatus);
#endif
rtl_reset(dev);
return 0;
}
}
static int rtl_poll(struct eth_device *dev)
{
unsigned int status;
unsigned int ring_offs;
unsigned int rx_size, rx_status;
int length=0;
ioaddr = dev->iobase;
if (inb(ioaddr + ChipCmd) & RxBufEmpty) {
return 0;
}
status = inw(ioaddr + IntrStatus);
/* See below for the rest of the interrupt acknowledges. */
outw(status & ~(RxFIFOOver | RxOverflow | RxOK), ioaddr + IntrStatus);
#ifdef DEBUG_RX
printf("rtl_poll: int %hX ", status);
#endif
ring_offs = cur_rx % RX_BUF_LEN;
rx_status = *(unsigned int*)KSEG1ADDR((rx_ring + ring_offs));
rx_size = rx_status >> 16;
rx_status &= 0xffff;
if ((rx_status & (RxBadSymbol|RxRunt|RxTooLong|RxCRCErr|RxBadAlign)) ||
(rx_size < ETH_ZLEN) || (rx_size > ETH_FRAME_LEN + 4)) {
printf("rx error %hX\n", rx_status);
rtl_reset(dev); /* this clears all interrupts still pending */
return 0;
}
/* Received a good packet */
length = rx_size - 4; /* no one cares about the FCS */
if (ring_offs+4+rx_size-4 > RX_BUF_LEN) {
int semi_count = RX_BUF_LEN - ring_offs - 4;
unsigned char rxdata[RX_BUF_LEN];
memcpy(rxdata, rx_ring + ring_offs + 4, semi_count);
memcpy(&(rxdata[semi_count]), rx_ring, rx_size-4-semi_count);
NetReceive(rxdata, length);
#ifdef DEBUG_RX
printf("rx packet %d+%d bytes", semi_count,rx_size-4-semi_count);
#endif
} else {
NetReceive(rx_ring + ring_offs + 4, length);
#ifdef DEBUG_RX
printf("rx packet %d bytes", rx_size-4);
#endif
}
cur_rx = (cur_rx + rx_size + 4 + 3) & ~3;
outw(cur_rx - 16, ioaddr + RxBufPtr);
/* See RTL8139 Programming Guide V0.1 for the official handling of
* Rx overflow situations. The document itself contains basically no
* usable information, except for a few exception handling rules. */
outw(status & (RxFIFOOver | RxOverflow | RxOK), ioaddr + IntrStatus);
return length;
}
static void rtl_disable(struct eth_device *dev)
{
int i;
/* reset the chip */
outb(CmdReset, ioaddr + ChipCmd);
/* Give the chip 10ms to finish the reset. */
for (i=0; i<100; ++i){
if ((inb(ioaddr + ChipCmd) & CmdReset) == 0) break;
udelay (100); /* wait 100us */
}
}
#endif /* CFG_CMD_NET && CONFIG_NET_MULTI && CONFIG_RTL8139 */

4
net/eth.c
View file

@ -47,6 +47,7 @@ extern int mpc5xxx_fec_initialize(bd_t*);
extern int skge_initialize(bd_t*);
extern int tsec_initialize(bd_t*);
extern int au1x00_enet_initialize(bd_t*);
extern int rtl8139_initialize(bd_t*);
static struct eth_device *eth_devices, *eth_current;
@ -154,6 +155,9 @@ int eth_initialize(bd_t *bis)
#if defined(CONFIG_AU1X00)
au1x00_enet_initialize(bis);
#endif
#if defined(CONFIG_RTL8139)
rtl8139_initialize(bis);
#endif
if (!eth_devices) {
puts ("No ethernet found.\n");