mirror of
https://github.com/Fishwaldo/u-boot.git
synced 2025-03-18 21:21:37 +00:00
Merge branch 'master' of git://git.denx.de/u-boot-uniphier
This commit is contained in:
commit
63f7af9a4c
33 changed files with 321 additions and 94 deletions
|
@ -32,4 +32,31 @@ config CMD_PINMON
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||||||
The boot mode pins are latched when the system reset is deasserted
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The boot mode pins are latched when the system reset is deasserted
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and determine which device the system should load a boot image from.
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and determine which device the system should load a boot image from.
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config SOC_INIT
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bool
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default SPL_BUILD
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config DRAM_INIT
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bool
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default SPL_BUILD
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choice
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prompt "DDR3 Frequency select"
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depends on DRAM_INIT
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config DDR_FREQ_1600
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bool "DDR3 1600"
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depends on MACH_PH1_PRO4 || MACH_PH1_LD4
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config DDR_FREQ_1333
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bool "DDR3 1333"
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depends on MACH_PH1_LD4 || MACH_PH1_SLD8
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endchoice
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config DDR_FREQ
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int
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default 1333 if DDR_FREQ_1333
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default 1600 if DDR_FREQ_1600
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endmenu
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endmenu
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@ -8,6 +8,7 @@ obj-$(CONFIG_SPL_BUILD) += spl.o
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obj-y += timer.o
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obj-y += timer.o
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obj-y += reset.o
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obj-y += reset.o
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obj-y += cache_uniphier.o
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obj-y += cache_uniphier.o
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obj-$(CONFIG_BOARD_POSTCLK_INIT) += board_postclk_init.o
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obj-y += dram_init.o
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obj-y += dram_init.o
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obj-$(CONFIG_DISPLAY_CPUINFO) += cpu_info.o
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obj-$(CONFIG_DISPLAY_CPUINFO) += cpu_info.o
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obj-$(CONFIG_BOARD_LATE_INIT) += board_late_init.o
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obj-$(CONFIG_BOARD_LATE_INIT) += board_late_init.o
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@ -5,11 +5,13 @@
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* SPDX-License-Identifier: GPL-2.0+
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* SPDX-License-Identifier: GPL-2.0+
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*/
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*/
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#include <common.h>
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#include <linux/compiler.h>
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#include <asm/arch/led.h>
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#include <asm/arch/led.h>
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#include <asm/arch/board.h>
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#include <asm/arch/board.h>
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void bcu_init(void);
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void __weak bcu_init(void)
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{
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};
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void sbc_init(void);
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void sbc_init(void);
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void sg_init(void);
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void sg_init(void);
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void pll_init(void);
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void pll_init(void);
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@ -18,12 +20,15 @@ void clkrst_init(void);
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int board_postclk_init(void)
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int board_postclk_init(void)
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{
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{
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#ifdef CONFIG_SOC_INIT
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bcu_init();
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bcu_init();
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sbc_init();
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sbc_init();
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sg_init();
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sg_init();
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uniphier_board_reset();
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pll_init();
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pll_init();
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uniphier_board_init();
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uniphier_board_init();
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@ -33,7 +38,7 @@ int board_postclk_init(void)
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clkrst_init();
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clkrst_init();
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led_write(B, 2, , );
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led_write(B, 2, , );
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#endif
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pin_init();
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pin_init();
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led_write(B, 3, , );
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led_write(B, 3, , );
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@ -16,7 +16,7 @@ int dram_init(void)
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DECLARE_GLOBAL_DATA_PTR;
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DECLARE_GLOBAL_DATA_PTR;
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gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
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gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
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#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
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#ifdef CONFIG_DRAM_INIT
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led_write(B, 4, , );
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led_write(B, 4, , );
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{
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{
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@ -5,7 +5,7 @@
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obj-$(CONFIG_DISPLAY_BOARDINFO) += board_info.o
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obj-$(CONFIG_DISPLAY_BOARDINFO) += board_info.o
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obj-y += platdevice.o
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obj-y += platdevice.o
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obj-y += boot-mode.o
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obj-y += boot-mode.o
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obj-$(CONFIG_BOARD_POSTCLK_INIT) += board_postclk_init.o bcu_init.o \
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obj-$(CONFIG_SOC_INIT) += bcu_init.o sbc_init.o sg_init.o pll_init.o \
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sbc_init.o sg_init.o pll_init.o clkrst_init.o pinctrl.o
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clkrst_init.o
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obj-$(CONFIG_SPL_BUILD) += pll_spectrum.o \
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obj-$(CONFIG_BOARD_POSTCLK_INIT) += pinctrl.o
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umc_init.o
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obj-$(CONFIG_DRAM_INIT) += pll_spectrum.o umc_init.o
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@ -13,3 +13,16 @@ SERIAL_DEVICE(0, 0x54006800, UART_MASTER_CLK)
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SERIAL_DEVICE(1, 0x54006900, UART_MASTER_CLK)
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SERIAL_DEVICE(1, 0x54006900, UART_MASTER_CLK)
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SERIAL_DEVICE(2, 0x54006a00, UART_MASTER_CLK)
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SERIAL_DEVICE(2, 0x54006a00, UART_MASTER_CLK)
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SERIAL_DEVICE(3, 0x54006b00, UART_MASTER_CLK)
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SERIAL_DEVICE(3, 0x54006b00, UART_MASTER_CLK)
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/* USB : TODO for Masahiro Yamada: move base address to Device Tree */
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struct uniphier_ehci_platform_data uniphier_ehci_platdata[] = {
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{
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.base = 0x5a800100,
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},
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{
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.base = 0x5a810100,
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},
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{
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.base = 0x5a820100,
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},
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};
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@ -149,10 +149,6 @@ int umc_init(void)
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CONFIG_SDRAM1_SIZE / 0x08000000);
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CONFIG_SDRAM1_SIZE / 0x08000000);
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}
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}
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#if CONFIG_DDR_FREQ != 1333 && CONFIG_DDR_FREQ != 1600
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#error Unsupported DDR Frequency.
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#endif
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#if (CONFIG_SDRAM0_SIZE == 0x08000000 || CONFIG_SDRAM0_SIZE == 0x10000000) && \
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#if (CONFIG_SDRAM0_SIZE == 0x08000000 || CONFIG_SDRAM0_SIZE == 0x10000000) && \
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(CONFIG_SDRAM1_SIZE == 0x08000000 || CONFIG_SDRAM1_SIZE == 0x10000000) && \
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(CONFIG_SDRAM1_SIZE == 0x08000000 || CONFIG_SDRAM1_SIZE == 0x10000000) && \
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CONFIG_DDR_NUM_CH0 == 1 && CONFIG_DDR_NUM_CH1 == 1
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CONFIG_DDR_NUM_CH0 == 1 && CONFIG_DDR_NUM_CH1 == 1
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@ -5,7 +5,6 @@
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obj-$(CONFIG_DISPLAY_BOARDINFO) += board_info.o
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obj-$(CONFIG_DISPLAY_BOARDINFO) += board_info.o
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obj-y += platdevice.o
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obj-y += platdevice.o
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obj-y += boot-mode.o
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obj-y += boot-mode.o
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obj-$(CONFIG_BOARD_POSTCLK_INIT) += board_postclk_init.o sbc_init.o \
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obj-$(CONFIG_SOC_INIT) += sbc_init.o sg_init.o pll_init.o clkrst_init.o
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sg_init.o pll_init.o clkrst_init.o pinctrl.o
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obj-$(CONFIG_BOARD_POSTCLK_INIT) += pinctrl.o
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obj-$(CONFIG_SPL_BUILD) += pll_spectrum.o \
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obj-$(CONFIG_DRAM_INIT) += pll_spectrum.o umc_init.o
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umc_init.o
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@ -1,39 +0,0 @@
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/*
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* Copyright (C) 2012-2014 Panasonic Corporation
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* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/arch/led.h>
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#include <asm/arch/board.h>
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void sbc_init(void);
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void sg_init(void);
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void pll_init(void);
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void pin_init(void);
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void clkrst_init(void);
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int board_postclk_init(void)
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{
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sbc_init();
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sg_init();
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pll_init();
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uniphier_board_init();
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led_write(B, 1, , );
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clkrst_init();
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led_write(B, 2, , );
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pin_init();
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led_write(B, 3, , );
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return 0;
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}
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@ -41,5 +41,12 @@ void pin_init(void)
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sg_set_pinsel(54, 0); /* NRYBY0 -> NRYBY0 */
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sg_set_pinsel(54, 0); /* NRYBY0 -> NRYBY0 */
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#endif
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#endif
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#ifdef CONFIG_USB_EHCI_UNIPHIER
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sg_set_pinsel(184, 0); /* USB2VBUS -> USB2VBUS */
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sg_set_pinsel(185, 0); /* USB2OD -> USB2OD */
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sg_set_pinsel(187, 0); /* USB3VBUS -> USB3VBUS */
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sg_set_pinsel(188, 0); /* USB3OD -> USB3OD */
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#endif
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writel(1, SG_LOADPINCTRL);
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writel(1, SG_LOADPINCTRL);
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}
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}
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|
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@ -13,3 +13,13 @@ SERIAL_DEVICE(0, 0x54006800, UART_MASTER_CLK)
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SERIAL_DEVICE(1, 0x54006900, UART_MASTER_CLK)
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SERIAL_DEVICE(1, 0x54006900, UART_MASTER_CLK)
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SERIAL_DEVICE(2, 0x54006a00, UART_MASTER_CLK)
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SERIAL_DEVICE(2, 0x54006a00, UART_MASTER_CLK)
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SERIAL_DEVICE(3, 0x54006b00, UART_MASTER_CLK)
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SERIAL_DEVICE(3, 0x54006b00, UART_MASTER_CLK)
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/* USB : TODO for Masahiro Yamada: move base address to Device Tree */
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struct uniphier_ehci_platform_data uniphier_ehci_platdata[] = {
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{
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.base = 0x5a800100,
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|
},
|
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|
{
|
||||||
|
.base = 0x5a810100,
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||||||
|
},
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||||||
|
};
|
||||||
|
|
|
@ -122,10 +122,6 @@ int umc_init(void)
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||||||
CONFIG_SDRAM1_SIZE / 0x08000000);
|
CONFIG_SDRAM1_SIZE / 0x08000000);
|
||||||
}
|
}
|
||||||
|
|
||||||
#if CONFIG_DDR_FREQ != 1600
|
|
||||||
#error Unsupported DDR frequency.
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if ((CONFIG_SDRAM0_SIZE == 0x20000000 && CONFIG_DDR_NUM_CH0 == 2) || \
|
#if ((CONFIG_SDRAM0_SIZE == 0x20000000 && CONFIG_DDR_NUM_CH0 == 2) || \
|
||||||
(CONFIG_SDRAM0_SIZE == 0x10000000 && CONFIG_DDR_NUM_CH0 == 1)) && \
|
(CONFIG_SDRAM0_SIZE == 0x10000000 && CONFIG_DDR_NUM_CH0 == 1)) && \
|
||||||
((CONFIG_SDRAM1_SIZE == 0x20000000 && CONFIG_DDR_NUM_CH1 == 2) || \
|
((CONFIG_SDRAM1_SIZE == 0x20000000 && CONFIG_DDR_NUM_CH1 == 2) || \
|
||||||
|
|
|
@ -5,7 +5,7 @@
|
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obj-$(CONFIG_DISPLAY_BOARDINFO) += board_info.o
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obj-$(CONFIG_DISPLAY_BOARDINFO) += board_info.o
|
||||||
obj-y += platdevice.o
|
obj-y += platdevice.o
|
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obj-y += boot-mode.o
|
obj-y += boot-mode.o
|
||||||
obj-$(CONFIG_BOARD_POSTCLK_INIT) += board_postclk_init.o bcu_init.o \
|
obj-$(CONFIG_SOC_INIT) += bcu_init.o sbc_init.o sg_init.o pll_init.o \
|
||||||
sbc_init.o sg_init.o pll_init.o clkrst_init.o pinctrl.o
|
clkrst_init.o
|
||||||
obj-$(CONFIG_SPL_BUILD) += pll_spectrum.o \
|
obj-$(CONFIG_BOARD_POSTCLK_INIT) += pinctrl.o
|
||||||
umc_init.o
|
obj-$(CONFIG_DRAM_INIT) += pll_spectrum.o umc_init.o
|
||||||
|
|
|
@ -1 +0,0 @@
|
||||||
#include "../ph1-ld4/board_postclk_init.c"
|
|
|
@ -13,3 +13,16 @@ SERIAL_DEVICE(0, 0x54006800, UART_MASTER_CLK)
|
||||||
SERIAL_DEVICE(1, 0x54006900, UART_MASTER_CLK)
|
SERIAL_DEVICE(1, 0x54006900, UART_MASTER_CLK)
|
||||||
SERIAL_DEVICE(2, 0x54006a00, UART_MASTER_CLK)
|
SERIAL_DEVICE(2, 0x54006a00, UART_MASTER_CLK)
|
||||||
SERIAL_DEVICE(3, 0x54006b00, UART_MASTER_CLK)
|
SERIAL_DEVICE(3, 0x54006b00, UART_MASTER_CLK)
|
||||||
|
|
||||||
|
/* USB : TODO for Masahiro Yamada: move base address to Device Tree */
|
||||||
|
struct uniphier_ehci_platform_data uniphier_ehci_platdata[] = {
|
||||||
|
{
|
||||||
|
.base = 0x5a800100,
|
||||||
|
},
|
||||||
|
{
|
||||||
|
.base = 0x5a810100,
|
||||||
|
},
|
||||||
|
{
|
||||||
|
.base = 0x5a820100,
|
||||||
|
},
|
||||||
|
};
|
||||||
|
|
|
@ -129,10 +129,6 @@ int umc_init(void)
|
||||||
CONFIG_SDRAM1_SIZE / 0x08000000);
|
CONFIG_SDRAM1_SIZE / 0x08000000);
|
||||||
}
|
}
|
||||||
|
|
||||||
#if CONFIG_DDR_FREQ != 1333
|
|
||||||
#error Unsupported DDR frequency.
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if (CONFIG_SDRAM0_SIZE == 0x08000000 || CONFIG_SDRAM0_SIZE == 0x10000000) && \
|
#if (CONFIG_SDRAM0_SIZE == 0x08000000 || CONFIG_SDRAM0_SIZE == 0x10000000) && \
|
||||||
(CONFIG_SDRAM1_SIZE == 0x08000000 || CONFIG_SDRAM1_SIZE == 0x10000000) && \
|
(CONFIG_SDRAM1_SIZE == 0x08000000 || CONFIG_SDRAM1_SIZE == 0x10000000) && \
|
||||||
CONFIG_DDR_NUM_CH0 == 1 && CONFIG_DDR_NUM_CH1 == 1
|
CONFIG_DDR_NUM_CH0 == 1 && CONFIG_DDR_NUM_CH1 == 1
|
||||||
|
|
|
@ -8,14 +8,11 @@
|
||||||
#include <common.h>
|
#include <common.h>
|
||||||
#include <asm/io.h>
|
#include <asm/io.h>
|
||||||
#include <asm/arch/sc-regs.h>
|
#include <asm/arch/sc-regs.h>
|
||||||
#include <asm/arch/board.h>
|
|
||||||
|
|
||||||
void reset_cpu(unsigned long ignored)
|
void reset_cpu(unsigned long ignored)
|
||||||
{
|
{
|
||||||
u32 tmp;
|
u32 tmp;
|
||||||
|
|
||||||
uniphier_board_reset();
|
|
||||||
|
|
||||||
writel(5, SC_IRQTIMSET); /* default value */
|
writel(5, SC_IRQTIMSET); /* default value */
|
||||||
|
|
||||||
tmp = readl(SC_SLFRSTSEL);
|
tmp = readl(SC_SLFRSTSEL);
|
||||||
|
|
33
arch/arm/include/asm/arch-uniphier/ehci-uniphier.h
Normal file
33
arch/arm/include/asm/arch-uniphier/ehci-uniphier.h
Normal file
|
@ -0,0 +1,33 @@
|
||||||
|
/*
|
||||||
|
* Copyright (C) 2014 Panasonic Corporation
|
||||||
|
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: GPL-2.0+
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __PLAT_UNIPHIER_EHCI_H
|
||||||
|
#define __PLAT_UNIPHIER_EHCI_H
|
||||||
|
|
||||||
|
#include <linux/types.h>
|
||||||
|
#include <asm/io.h>
|
||||||
|
#include "mio-regs.h"
|
||||||
|
|
||||||
|
struct uniphier_ehci_platform_data {
|
||||||
|
unsigned long base;
|
||||||
|
};
|
||||||
|
|
||||||
|
extern struct uniphier_ehci_platform_data uniphier_ehci_platdata[];
|
||||||
|
|
||||||
|
static inline void uniphier_ehci_reset(int index, int on)
|
||||||
|
{
|
||||||
|
u32 tmp;
|
||||||
|
|
||||||
|
tmp = readl(MIO_USB_RSTCTRL(index));
|
||||||
|
if (on)
|
||||||
|
tmp &= ~MIO_USB_RSTCTRL_XRST;
|
||||||
|
else
|
||||||
|
tmp |= MIO_USB_RSTCTRL_XRST;
|
||||||
|
writel(tmp, MIO_USB_RSTCTRL(index));
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif /* __PLAT_UNIPHIER_EHCI_H */
|
20
arch/arm/include/asm/arch-uniphier/mio-regs.h
Normal file
20
arch/arm/include/asm/arch-uniphier/mio-regs.h
Normal file
|
@ -0,0 +1,20 @@
|
||||||
|
/*
|
||||||
|
* UniPhier MIO (Media I/O) registers
|
||||||
|
*
|
||||||
|
* Copyright (C) 2014 Panasonic Corporation
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: GPL-2.0+
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef ARCH_MIO_REGS_H
|
||||||
|
#define ARCH_MIO_REGS_H
|
||||||
|
|
||||||
|
#define MIO_BASE 0x59810000
|
||||||
|
|
||||||
|
#define MIO_CLKCTRL(i) (MIO_BASE + 0x200 * (i) + 0x0020)
|
||||||
|
#define MIO_RSTCTRL(i) (MIO_BASE + 0x200 * (i) + 0x0110)
|
||||||
|
#define MIO_USB_RSTCTRL(i) (MIO_BASE + 0x200 * (i) + 0x0114)
|
||||||
|
|
||||||
|
#define MIO_USB_RSTCTRL_XRST (0x1 << 0)
|
||||||
|
|
||||||
|
#endif /* ARCH_MIO_REGS_H */
|
|
@ -21,4 +21,6 @@ U_BOOT_DEVICE(serial##n) = { \
|
||||||
.platdata = &serial_device##n \
|
.platdata = &serial_device##n \
|
||||||
};
|
};
|
||||||
|
|
||||||
|
#include <asm/arch/ehci-uniphier.h>
|
||||||
|
|
||||||
#endif /* ARCH_PLATDEVICE_H */
|
#endif /* ARCH_PLATDEVICE_H */
|
||||||
|
|
|
@ -88,7 +88,18 @@
|
||||||
#define SG_PINMON0_CLK_MODE_AXOSEL_20480KHZ (0x2 << 16)
|
#define SG_PINMON0_CLK_MODE_AXOSEL_20480KHZ (0x2 << 16)
|
||||||
#define SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A (0x3 << 16)
|
#define SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A (0x3 << 16)
|
||||||
|
|
||||||
#ifndef __ASSEMBLY__
|
#ifdef __ASSEMBLY__
|
||||||
|
|
||||||
|
.macro set_pinsel, n, value, ra, rd
|
||||||
|
ldr \ra, =SG_PINSEL_ADDR(\n)
|
||||||
|
ldr \rd, [\ra]
|
||||||
|
and \rd, \rd, #SG_PINSEL_MASK(\n)
|
||||||
|
orr \rd, \rd, #SG_PINSEL_MODE(\n, \value)
|
||||||
|
str \rd, [\ra]
|
||||||
|
.endm
|
||||||
|
|
||||||
|
#else
|
||||||
|
|
||||||
#include <linux/types.h>
|
#include <linux/types.h>
|
||||||
#include <asm/io.h>
|
#include <asm/io.h>
|
||||||
|
|
||||||
|
|
|
@ -8,4 +8,7 @@ CONFIG_SYS_NAND_DENALI_64BIT=y
|
||||||
CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8
|
CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8
|
||||||
CONFIG_DM_SERIAL=y
|
CONFIG_DM_SERIAL=y
|
||||||
CONFIG_UNIPHIER_SERIAL=y
|
CONFIG_UNIPHIER_SERIAL=y
|
||||||
|
CONFIG_USB=y
|
||||||
|
CONFIG_USB_EHCI_HCD=y
|
||||||
|
CONFIG_USB_STORAGE=y
|
||||||
S:CONFIG_SPL_NAND_DENALI=y
|
S:CONFIG_SPL_NAND_DENALI=y
|
||||||
|
|
|
@ -8,4 +8,7 @@ CONFIG_SYS_NAND_DENALI_64BIT=y
|
||||||
CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8
|
CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8
|
||||||
CONFIG_DM_SERIAL=y
|
CONFIG_DM_SERIAL=y
|
||||||
CONFIG_UNIPHIER_SERIAL=y
|
CONFIG_UNIPHIER_SERIAL=y
|
||||||
|
CONFIG_USB=y
|
||||||
|
CONFIG_USB_EHCI_HCD=y
|
||||||
|
CONFIG_USB_STORAGE=y
|
||||||
S:CONFIG_SPL_NAND_DENALI=y
|
S:CONFIG_SPL_NAND_DENALI=y
|
||||||
|
|
|
@ -8,4 +8,7 @@ CONFIG_SYS_NAND_DENALI_64BIT=y
|
||||||
CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8
|
CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8
|
||||||
CONFIG_DM_SERIAL=y
|
CONFIG_DM_SERIAL=y
|
||||||
CONFIG_UNIPHIER_SERIAL=y
|
CONFIG_UNIPHIER_SERIAL=y
|
||||||
|
CONFIG_USB=y
|
||||||
|
CONFIG_USB_EHCI_HCD=y
|
||||||
|
CONFIG_USB_STORAGE=y
|
||||||
S:CONFIG_SPL_NAND_DENALI=y
|
S:CONFIG_SPL_NAND_DENALI=y
|
||||||
|
|
|
@ -5,7 +5,7 @@
|
||||||
* SPDX-License-Identifier: GPL-2.0+
|
* SPDX-License-Identifier: GPL-2.0+
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#include <common.h>
|
#include <linux/serial_reg.h>
|
||||||
#include <asm/io.h>
|
#include <asm/io.h>
|
||||||
#include <asm/errno.h>
|
#include <asm/errno.h>
|
||||||
#include <dm/device.h>
|
#include <dm/device.h>
|
||||||
|
@ -37,17 +37,6 @@ struct uniphier_serial {
|
||||||
|
|
||||||
#define thr rbr
|
#define thr rbr
|
||||||
|
|
||||||
/*
|
|
||||||
* These are the definitions for the Line Control Register
|
|
||||||
*/
|
|
||||||
#define UART_LCR_WLS_8 0x03 /* 8 bit character length */
|
|
||||||
|
|
||||||
/*
|
|
||||||
* These are the definitions for the Line Status Register
|
|
||||||
*/
|
|
||||||
#define UART_LSR_DR 0x01 /* Data ready */
|
|
||||||
#define UART_LSR_THRE 0x20 /* Xmit holding register empty */
|
|
||||||
|
|
||||||
struct uniphier_serial_private_data {
|
struct uniphier_serial_private_data {
|
||||||
struct uniphier_serial __iomem *membase;
|
struct uniphier_serial __iomem *membase;
|
||||||
};
|
};
|
||||||
|
@ -62,7 +51,7 @@ static int uniphier_serial_setbrg(struct udevice *dev, int baudrate)
|
||||||
const unsigned int mode_x_div = 16;
|
const unsigned int mode_x_div = 16;
|
||||||
unsigned int divisor;
|
unsigned int divisor;
|
||||||
|
|
||||||
writeb(UART_LCR_WLS_8, &port->lcr);
|
writeb(UART_LCR_WLEN8, &port->lcr);
|
||||||
|
|
||||||
divisor = DIV_ROUND_CLOSEST(plat->uartclk, mode_x_div * baudrate);
|
divisor = DIV_ROUND_CLOSEST(plat->uartclk, mode_x_div * baudrate);
|
||||||
|
|
||||||
|
|
|
@ -0,0 +1,46 @@
|
||||||
|
config USB_ARCH_HAS_HCD
|
||||||
|
def_bool y
|
||||||
|
|
||||||
|
config USB
|
||||||
|
bool "Support for Host-side USB"
|
||||||
|
depends on USB_ARCH_HAS_HCD
|
||||||
|
---help---
|
||||||
|
Universal Serial Bus (USB) is a specification for a serial bus
|
||||||
|
subsystem which offers higher speeds and more features than the
|
||||||
|
traditional PC serial port. The bus supplies power to peripherals
|
||||||
|
and allows for hot swapping. Up to 127 USB peripherals can be
|
||||||
|
connected to a single USB host in a tree structure.
|
||||||
|
|
||||||
|
The USB host is the root of the tree, the peripherals are the
|
||||||
|
leaves and the inner nodes are special USB devices called hubs.
|
||||||
|
Most PCs now have USB host ports, used to connect peripherals
|
||||||
|
such as scanners, keyboards, mice, modems, cameras, disks,
|
||||||
|
flash memory, network links, and printers to the PC.
|
||||||
|
|
||||||
|
Say Y here if your computer has a host-side USB port and you want
|
||||||
|
to use USB devices. You then need to say Y to at least one of the
|
||||||
|
Host Controller Driver (HCD) options below. Choose a USB 1.1
|
||||||
|
controller, such as "UHCI HCD support" or "OHCI HCD support",
|
||||||
|
and "EHCI HCD (USB 2.0) support" except for older systems that
|
||||||
|
do not have USB 2.0 support. It doesn't normally hurt to select
|
||||||
|
them all if you are not certain.
|
||||||
|
|
||||||
|
If your system has a device-side USB port, used in the peripheral
|
||||||
|
side of the USB protocol, see the "USB Gadget" framework instead.
|
||||||
|
|
||||||
|
After choosing your HCD, then select drivers for the USB peripherals
|
||||||
|
you'll be using. You may want to check out the information provided
|
||||||
|
in <file:Documentation/usb/> and especially the links given in
|
||||||
|
<file:Documentation/usb/usb-help.txt>.
|
||||||
|
|
||||||
|
if USB
|
||||||
|
|
||||||
|
source "drivers/usb/host/Kconfig"
|
||||||
|
|
||||||
|
config USB_STORAGE
|
||||||
|
bool "USB Mass Storage support"
|
||||||
|
---help---
|
||||||
|
Say Y here if you want to connect USB mass storage devices to your
|
||||||
|
board's USB port.
|
||||||
|
|
||||||
|
endif
|
56
drivers/usb/host/Kconfig
Normal file
56
drivers/usb/host/Kconfig
Normal file
|
@ -0,0 +1,56 @@
|
||||||
|
#
|
||||||
|
# USB Host Controller Drivers
|
||||||
|
#
|
||||||
|
comment "USB Host Controller Drivers"
|
||||||
|
|
||||||
|
config USB_XHCI_HCD
|
||||||
|
bool "xHCI HCD (USB 3.0) support"
|
||||||
|
---help---
|
||||||
|
The eXtensible Host Controller Interface (xHCI) is standard for USB 3.0
|
||||||
|
"SuperSpeed" host controller hardware.
|
||||||
|
|
||||||
|
config USB_XHCI
|
||||||
|
bool
|
||||||
|
default USB_XHCI_HCD
|
||||||
|
---help---
|
||||||
|
TODO: rename after most boards switch to Kconfig
|
||||||
|
|
||||||
|
if USB_XHCI_HCD
|
||||||
|
|
||||||
|
endif
|
||||||
|
|
||||||
|
config USB_EHCI_HCD
|
||||||
|
bool "EHCI HCD (USB 2.0) support"
|
||||||
|
---help---
|
||||||
|
The Enhanced Host Controller Interface (EHCI) is standard for USB 2.0
|
||||||
|
"high speed" (480 Mbit/sec, 60 Mbyte/sec) host controller hardware.
|
||||||
|
If your USB host controller supports USB 2.0, you will likely want to
|
||||||
|
configure this Host Controller Driver.
|
||||||
|
|
||||||
|
EHCI controllers are packaged with "companion" host controllers (OHCI
|
||||||
|
or UHCI) to handle USB 1.1 devices connected to root hub ports. Ports
|
||||||
|
will connect to EHCI if the device is high speed, otherwise they
|
||||||
|
connect to a companion controller. If you configure EHCI, you should
|
||||||
|
probably configure the OHCI (for NEC and some other vendors) USB Host
|
||||||
|
Controller Driver or UHCI (for Via motherboards) Host Controller
|
||||||
|
Driver too.
|
||||||
|
|
||||||
|
You may want to read <file:Documentation/usb/ehci.txt>.
|
||||||
|
|
||||||
|
config USB_EHCI
|
||||||
|
bool
|
||||||
|
default USB_EHCI_HCD
|
||||||
|
---help---
|
||||||
|
TODO: rename after most boards switch to Kconfig
|
||||||
|
|
||||||
|
if USB_EHCI_HCD
|
||||||
|
|
||||||
|
config USB_EHCI_UNIPHIER
|
||||||
|
bool "Support for Panasonic UniPhier on-chip EHCI USB controller"
|
||||||
|
depends on ARCH_UNIPHIER
|
||||||
|
default y
|
||||||
|
---help---
|
||||||
|
Enables support for the on-chip EHCI controller on Panasonic
|
||||||
|
UniPhier SoCs.
|
||||||
|
|
||||||
|
endif
|
|
@ -37,6 +37,7 @@ obj-$(CONFIG_USB_EHCI_PCI) += ehci-pci.o
|
||||||
obj-$(CONFIG_USB_EHCI_SPEAR) += ehci-spear.o
|
obj-$(CONFIG_USB_EHCI_SPEAR) += ehci-spear.o
|
||||||
obj-$(CONFIG_USB_EHCI_SUNXI) += ehci-sunxi.o
|
obj-$(CONFIG_USB_EHCI_SUNXI) += ehci-sunxi.o
|
||||||
obj-$(CONFIG_USB_EHCI_TEGRA) += ehci-tegra.o
|
obj-$(CONFIG_USB_EHCI_TEGRA) += ehci-tegra.o
|
||||||
|
obj-$(CONFIG_USB_EHCI_UNIPHIER) += ehci-uniphier.o
|
||||||
obj-$(CONFIG_USB_EHCI_VCT) += ehci-vct.o
|
obj-$(CONFIG_USB_EHCI_VCT) += ehci-vct.o
|
||||||
obj-$(CONFIG_USB_EHCI_RMOBILE) += ehci-rmobile.o
|
obj-$(CONFIG_USB_EHCI_RMOBILE) += ehci-rmobile.o
|
||||||
obj-$(CONFIG_USB_EHCI_ZYNQ) += ehci-zynq.o
|
obj-$(CONFIG_USB_EHCI_ZYNQ) += ehci-zynq.o
|
||||||
|
|
39
drivers/usb/host/ehci-uniphier.c
Normal file
39
drivers/usb/host/ehci-uniphier.c
Normal file
|
@ -0,0 +1,39 @@
|
||||||
|
/*
|
||||||
|
* Copyright (C) 2014 Panasonic Corporation
|
||||||
|
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: GPL-2.0+
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <common.h>
|
||||||
|
#include <usb.h>
|
||||||
|
#include <asm/arch/ehci-uniphier.h>
|
||||||
|
#include "ehci.h"
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Create the appropriate control structures to manage
|
||||||
|
* a new EHCI host controller.
|
||||||
|
*/
|
||||||
|
int ehci_hcd_init(int index, enum usb_init_type init, struct ehci_hccr **hccr,
|
||||||
|
struct ehci_hcor **hcor)
|
||||||
|
{
|
||||||
|
struct ehci_hccr *cr;
|
||||||
|
struct ehci_hcor *or;
|
||||||
|
|
||||||
|
uniphier_ehci_reset(index, 0);
|
||||||
|
|
||||||
|
cr = (struct ehci_hccr *)(uniphier_ehci_platdata[index].base);
|
||||||
|
or = (void *)cr + HC_LENGTH(ehci_readl(&cr->cr_capbase));
|
||||||
|
|
||||||
|
*hccr = cr;
|
||||||
|
*hcor = or;
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
int ehci_hcd_stop(int index)
|
||||||
|
{
|
||||||
|
uniphier_ehci_reset(index, 1);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
|
@ -37,8 +37,6 @@
|
||||||
#define CONFIG_DDR_NUM_CH0 1
|
#define CONFIG_DDR_NUM_CH0 1
|
||||||
#define CONFIG_DDR_NUM_CH1 1
|
#define CONFIG_DDR_NUM_CH1 1
|
||||||
|
|
||||||
#define CONFIG_DDR_FREQ 1600
|
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Memory Size & Mapping
|
* Memory Size & Mapping
|
||||||
*/
|
*/
|
||||||
|
|
|
@ -37,8 +37,6 @@
|
||||||
#define CONFIG_DDR_NUM_CH0 2
|
#define CONFIG_DDR_NUM_CH0 2
|
||||||
#define CONFIG_DDR_NUM_CH1 2
|
#define CONFIG_DDR_NUM_CH1 2
|
||||||
|
|
||||||
#define CONFIG_DDR_FREQ 1600
|
|
||||||
|
|
||||||
#define CONFIG_UNIPHIER_SMP
|
#define CONFIG_UNIPHIER_SMP
|
||||||
|
|
||||||
/*
|
/*
|
||||||
|
|
|
@ -37,8 +37,6 @@
|
||||||
#define CONFIG_DDR_NUM_CH0 1
|
#define CONFIG_DDR_NUM_CH0 1
|
||||||
#define CONFIG_DDR_NUM_CH1 1
|
#define CONFIG_DDR_NUM_CH1 1
|
||||||
|
|
||||||
#define CONFIG_DDR_FREQ 1333
|
|
||||||
|
|
||||||
/* #define CONFIG_DDR_STANDARD */
|
/* #define CONFIG_DDR_STANDARD */
|
||||||
|
|
||||||
/*
|
/*
|
||||||
|
|
|
@ -43,7 +43,7 @@ are defined. Select only one of them."
|
||||||
#define CONFIG_SMC911X_BASE CONFIG_SUPPORT_CARD_ETHER_BASE
|
#define CONFIG_SMC911X_BASE CONFIG_SUPPORT_CARD_ETHER_BASE
|
||||||
#define CONFIG_SMC911X_32_BIT
|
#define CONFIG_SMC911X_32_BIT
|
||||||
|
|
||||||
#define CONFIG_SYS_MALLOC_F_LEN 0x7000
|
#define CONFIG_SYS_MALLOC_F_LEN 0x2000
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
/*-----------------------------------------------------------------------
|
||||||
* MMU and Cache Setting
|
* MMU and Cache Setting
|
||||||
|
@ -166,6 +166,13 @@ are defined. Select only one of them."
|
||||||
#define CONFIG_SYS_NAND_USE_FLASH_BBT
|
#define CONFIG_SYS_NAND_USE_FLASH_BBT
|
||||||
#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
|
#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
|
||||||
|
|
||||||
|
/* USB */
|
||||||
|
#define CONFIG_CMD_USB
|
||||||
|
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
|
||||||
|
#define CONFIG_CMD_FAT
|
||||||
|
#define CONFIG_FAT_WRITE
|
||||||
|
#define CONFIG_DOS_PARTITION
|
||||||
|
|
||||||
/* memtest works on */
|
/* memtest works on */
|
||||||
#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
|
#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
|
||||||
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x01000000)
|
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x01000000)
|
||||||
|
@ -241,9 +248,9 @@ are defined. Select only one of them."
|
||||||
|
|
||||||
#define CONFIG_SYS_TEXT_BASE 0x84000000
|
#define CONFIG_SYS_TEXT_BASE 0x84000000
|
||||||
|
|
||||||
#if defined(CONFIG_SPL_BUILD)
|
|
||||||
#define CONFIG_BOARD_POSTCLK_INIT
|
#define CONFIG_BOARD_POSTCLK_INIT
|
||||||
#else
|
|
||||||
|
#ifndef CONFIG_SPL_BUILD
|
||||||
#define CONFIG_SKIP_LOWLEVEL_INIT
|
#define CONFIG_SKIP_LOWLEVEL_INIT
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
|
Loading…
Add table
Reference in a new issue