Merge branch 'master' of git://www.denx.de/git/u-boot-mips

This commit is contained in:
Wolfgang Denk 2008-03-26 00:44:52 +01:00
commit 6525489323
19 changed files with 1060 additions and 457 deletions

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@ -2472,11 +2472,6 @@ cm4008_config : unconfig
cm41xx_config : unconfig cm41xx_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm920t cm41xx NULL ks8695 @$(MKCONFIG) $(@:_config=) arm arm920t cm41xx NULL ks8695
gth2_config : unconfig
@mkdir -p $(obj)include
@echo "#define CONFIG_GTH2 1" >$(obj)include/config.h
@$(MKCONFIG) -a gth2 mips mips gth2
######################################################################### #########################################################################
## S3C44B0 Systems ## S3C44B0 Systems
######################################################################### #########################################################################
@ -2679,6 +2674,11 @@ pb1000_config : unconfig
@echo "#define CONFIG_PB1000 1" >$(obj)include/config.h @echo "#define CONFIG_PB1000 1" >$(obj)include/config.h
@$(MKCONFIG) -a pb1x00 mips mips pb1x00 @$(MKCONFIG) -a pb1x00 mips mips pb1x00
gth2_config: unconfig
@mkdir -p $(obj)include
@echo "#define CONFIG_GTH2 1" >$(obj)include/config.h
@$(MKCONFIG) -a gth2 mips mips gth2
qemu_mips_config: unconfig qemu_mips_config: unconfig
@mkdir -p $(obj)include @mkdir -p $(obj)include
@echo "#define CONFIG_QEMU_MIPS 1" >$(obj)include/config.h @echo "#define CONFIG_QEMU_MIPS 1" >$(obj)include/config.h

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@ -26,9 +26,15 @@
#include <asm/addrspace.h> #include <asm/addrspace.h>
#include <asm/inca-ip.h> #include <asm/inca-ip.h>
#include <asm/io.h> #include <asm/io.h>
#include <asm/reboot.h>
extern uint incaip_get_cpuclk(void); extern uint incaip_get_cpuclk(void);
void _machine_restart(void)
{
*INCA_IP_WDT_RST_REQ = 0x3f;
}
static ulong max_sdram_size(void) static ulong max_sdram_size(void)
{ {
/* The only supported SDRAM data width is 16bit. /* The only supported SDRAM data width is 16bit.

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@ -276,6 +276,12 @@ __sdram_init:
.ent lowlevel_init .ent lowlevel_init
lowlevel_init: lowlevel_init:
/* Disable Watchdog.
*/
la t9, disable_incaip_wdt
jalr t9
nop
/* EBU, CGU and SDRAM Initialization. /* EBU, CGU and SDRAM Initialization.
*/ */
li a0, CPU_CLOCK_RATE li a0, CPU_CLOCK_RATE

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@ -29,6 +29,7 @@
#include <asm/io.h> #include <asm/io.h>
#include <asm/addrspace.h> #include <asm/addrspace.h>
#include <asm/cacheops.h> #include <asm/cacheops.h>
#include <asm/reboot.h>
#include "sconsole.h" #include "sconsole.h"
@ -52,6 +53,13 @@ extern int asc_serial_getc (void);
extern int asc_serial_tstc (void); extern int asc_serial_tstc (void);
extern void asc_serial_setbrg (void); extern void asc_serial_setbrg (void);
void _machine_restart(void)
{
void (*f)(void) = (void *) 0xbfc00000;
f();
}
static void sdram_timing_init (ulong size) static void sdram_timing_init (ulong size)
{ {
register uint pass; register uint pass;

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@ -12,10 +12,17 @@
#include <common.h> #include <common.h>
#include <command.h> #include <command.h>
#include <asm/addrspace.h> #include <asm/addrspace.h>
#include <asm/inca-ip.h>
#include <asm/io.h> #include <asm/io.h>
#include <asm/reboot.h>
#include <pci.h> #include <pci.h>
void _machine_restart(void)
{
void (*f)(void) = (void *) 0xbfc00000;
f();
}
#if defined(CONFIG_PCI) #if defined(CONFIG_PCI)
static struct pci_controller hose; static struct pci_controller hose;

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@ -1,5 +1,5 @@
/* /*
* Cache-handling routined for MIPS 4K CPUs * Cache-handling routined for MIPS CPUs
* *
* Copyright (c) 2003 Wolfgang Denk <wd@denx.de> * Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
* *
@ -24,15 +24,32 @@
#include <config.h> #include <config.h>
#include <version.h> #include <version.h>
#include <asm/asm.h>
#include <asm/regdef.h> #include <asm/regdef.h>
#include <asm/mipsregs.h> #include <asm/mipsregs.h>
#include <asm/addrspace.h> #include <asm/addrspace.h>
#include <asm/cacheops.h> #include <asm/cacheops.h>
/* 16KB is the maximum size of instruction and data caches on #define RA t8
* MIPS 4K.
*/ /*
#define MIPS_MAX_CACHE_SIZE 0x4000 * 16kB is the maximum size of instruction and data caches on MIPS 4K,
* 64kB is on 4KE, 24K, 5K, etc. Set bigger size for convenience.
*
* Note that the above size is the maximum size of primary cache. U-Boot
* doesn't have L2 cache support for now.
*/
#define MIPS_MAX_CACHE_SIZE 0x10000
#define INDEX_BASE KSEG0
.macro cache_op op addr
.set push
.set noreorder
.set mips3
cache \op, 0(\addr)
.set pop
.endm
/* /*
* cacheop macro to automate cache operations * cacheop macro to automate cache operations
@ -103,6 +120,77 @@
#define icacheop(kva, n, cacheSize, cacheLineSize, op) \ #define icacheop(kva, n, cacheSize, cacheLineSize, op) \
icacheopn(kva, n, cacheSize, cacheLineSize, 1, (op)) icacheopn(kva, n, cacheSize, cacheLineSize, 1, (op))
.macro f_fill64 dst, offset, val
LONG_S \val, (\offset + 0 * LONGSIZE)(\dst)
LONG_S \val, (\offset + 1 * LONGSIZE)(\dst)
LONG_S \val, (\offset + 2 * LONGSIZE)(\dst)
LONG_S \val, (\offset + 3 * LONGSIZE)(\dst)
LONG_S \val, (\offset + 4 * LONGSIZE)(\dst)
LONG_S \val, (\offset + 5 * LONGSIZE)(\dst)
LONG_S \val, (\offset + 6 * LONGSIZE)(\dst)
LONG_S \val, (\offset + 7 * LONGSIZE)(\dst)
#if LONGSIZE == 4
LONG_S \val, (\offset + 8 * LONGSIZE)(\dst)
LONG_S \val, (\offset + 9 * LONGSIZE)(\dst)
LONG_S \val, (\offset + 10 * LONGSIZE)(\dst)
LONG_S \val, (\offset + 11 * LONGSIZE)(\dst)
LONG_S \val, (\offset + 12 * LONGSIZE)(\dst)
LONG_S \val, (\offset + 13 * LONGSIZE)(\dst)
LONG_S \val, (\offset + 14 * LONGSIZE)(\dst)
LONG_S \val, (\offset + 15 * LONGSIZE)(\dst)
#endif
.endm
/*
* mips_init_icache(uint PRId, ulong icache_size, unchar icache_linesz)
*/
LEAF(mips_init_icache)
blez a1, 9f
mtc0 zero, CP0_TAGLO
/* clear tag to invalidate */
PTR_LI t0, INDEX_BASE
PTR_ADDU t1, t0, a1
1: cache_op Index_Store_Tag_I t0
PTR_ADDU t0, a2
bne t0, t1, 1b
/* fill once, so data field parity is correct */
PTR_LI t0, INDEX_BASE
2: cache_op Fill t0
PTR_ADDU t0, a2
bne t0, t1, 2b
/* invalidate again - prudent but not strictly neccessary */
PTR_LI t0, INDEX_BASE
1: cache_op Index_Store_Tag_I t0
PTR_ADDU t0, a2
bne t0, t1, 1b
9: jr ra
END(mips_init_icache)
/*
* mips_init_dcache(uint PRId, ulong dcache_size, unchar dcache_linesz)
*/
LEAF(mips_init_dcache)
blez a1, 9f
mtc0 zero, CP0_TAGLO
/* clear all tags */
PTR_LI t0, INDEX_BASE
PTR_ADDU t1, t0, a1
1: cache_op Index_Store_Tag_D t0
PTR_ADDU t0, a2
bne t0, t1, 1b
/* load from each line (in cached space) */
PTR_LI t0, INDEX_BASE
2: LONG_L zero, 0(t0)
PTR_ADDU t0, a2
bne t0, t1, 2b
/* clear all tags */
PTR_LI t0, INDEX_BASE
1: cache_op Index_Store_Tag_D t0
PTR_ADDU t0, a2
bne t0, t1, 1b
9: jr ra
END(mips_init_dcache)
/******************************************************************************* /*******************************************************************************
* *
* mips_cache_reset - low level initialisation of the primary caches * mips_cache_reset - low level initialisation of the primary caches
@ -119,10 +207,8 @@
* RETURNS: N/A * RETURNS: N/A
* *
*/ */
.globl mips_cache_reset NESTED(mips_cache_reset, 0, ra)
.ent mips_cache_reset move RA, ra
mips_cache_reset:
li t2, CFG_ICACHE_SIZE li t2, CFG_ICACHE_SIZE
li t3, CFG_DCACHE_SIZE li t3, CFG_DCACHE_SIZE
li t4, CFG_CACHELINE_SIZE li t4, CFG_CACHELINE_SIZE
@ -130,27 +216,14 @@ mips_cache_reset:
li v0, MIPS_MAX_CACHE_SIZE li v0, MIPS_MAX_CACHE_SIZE
/* Now clear that much memory starting from zero. /*
* Now clear that much memory starting from zero.
*/ */
PTR_LI a0, KSEG1
li a0, KSEG1 PTR_ADDU a1, a0, v0
addu a1, a0, v0 2: PTR_ADDIU a0, 64
2: f_fill64 a0, -64, zero
sw zero, 0(a0) bne a0, a1, 2b
sw zero, 4(a0)
sw zero, 8(a0)
sw zero, 12(a0)
sw zero, 16(a0)
sw zero, 20(a0)
sw zero, 24(a0)
sw zero, 28(a0)
addu a0, 32
bltu a0, a1, 2b
/* Set invalid tag.
*/
mtc0 zero, CP0_TAGLO
/* /*
* The caches are probably in an indeterminate state, * The caches are probably in an indeterminate state,
@ -158,48 +231,26 @@ mips_cache_reset:
* invalidate, load/fill, invalidate for each line. * invalidate, load/fill, invalidate for each line.
*/ */
/* Assume bottom of RAM will generate good parity for the cache. /*
* Assume bottom of RAM will generate good parity for the cache.
*/ */
li a0, K0BASE /*
move a2, t2 # icacheSize * Initialize the I-cache first,
move a3, t4 # icacheLineSize
move a1, a2
icacheopn(a0,a1,a2,a3,121,(Index_Store_Tag_I,Fill))
/* To support Orion/R4600, we initialise the data cache in 3 passes.
*/ */
move a1, t2
move a2, t4
bal mips_init_icache
/* 1: initialise dcache tags. /*
* then initialize D-cache.
*/ */
move a1, t3
move a2, t5
bal mips_init_dcache
li a0, K0BASE jr RA
move a2, t3 # dcacheSize END(mips_cache_reset)
move a3, t5 # dcacheLineSize
move a1, a2
icacheop(a0,a1,a2,a3,Index_Store_Tag_D)
/* 2: fill dcache.
*/
li a0, K0BASE
move a2, t3 # dcacheSize
move a3, t5 # dcacheLineSize
move a1, a2
icacheopn(a0,a1,a2,a3,1lw,(dummy))
/* 3: clear dcache tags.
*/
li a0, K0BASE
move a2, t3 # dcacheSize
move a3, t5 # dcacheLineSize
move a1, a2
icacheop(a0,a1,a2,a3,Index_Store_Tag_D)
j ra
.end mips_cache_reset
/******************************************************************************* /*******************************************************************************
* *
@ -208,15 +259,15 @@ mips_cache_reset:
* RETURNS: 0 - cache disabled; 1 - cache enabled * RETURNS: 0 - cache disabled; 1 - cache enabled
* *
*/ */
.globl dcache_status LEAF(dcache_status)
.ent dcache_status mfc0 t0, CP0_CONFIG
dcache_status: li t1, CONF_CM_UNCACHED
andi t0, t0, CONF_CM_CMASK
mfc0 v0, CP0_CONFIG move v0, zero
andi v0, v0, 1 beq t0, t1, 2f
j ra li v0, 1
2: jr ra
.end dcache_status END(dcache_status)
/******************************************************************************* /*******************************************************************************
* *
@ -225,19 +276,16 @@ dcache_status:
* RETURNS: N/A * RETURNS: N/A
* *
*/ */
.globl dcache_disable LEAF(dcache_disable)
.ent dcache_disable
dcache_disable:
mfc0 t0, CP0_CONFIG mfc0 t0, CP0_CONFIG
li t1, -8 li t1, -8
and t0, t0, t1 and t0, t0, t1
ori t0, t0, CONF_CM_UNCACHED ori t0, t0, CONF_CM_UNCACHED
mtc0 t0, CP0_CONFIG mtc0 t0, CP0_CONFIG
j ra j ra
END(dcache_disable)
.end dcache_disable #ifdef CFG_INIT_RAM_LOCK_MIPS
/******************************************************************************* /*******************************************************************************
* *
* mips_cache_lock - lock RAM area pointed to by a0 in cache. * mips_cache_lock - lock RAM area pointed to by a0 in cache.
@ -263,3 +311,4 @@ mips_cache_lock:
j ra j ra
.end mips_cache_lock .end mips_cache_lock
#endif /* CFG_INIT_RAM_LOCK_MIPS */

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@ -23,24 +23,45 @@
#include <common.h> #include <common.h>
#include <command.h> #include <command.h>
#include <asm/inca-ip.h>
#include <asm/mipsregs.h> #include <asm/mipsregs.h>
#include <asm/cacheops.h>
#include <asm/reboot.h>
#define cache_op(op,addr) \
__asm__ __volatile__( \
" .set push \n" \
" .set noreorder \n" \
" .set mips3\n\t \n" \
" cache %0, %1 \n" \
" .set pop \n" \
: \
: "i" (op), "R" (*(unsigned char *)(addr)))
void __attribute__((weak)) _machine_restart(void)
{
}
int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{ {
#if defined(CONFIG_INCA_IP) _machine_restart();
*INCA_IP_WDT_RST_REQ = 0x3f;
#elif defined(CONFIG_PURPLE) || defined(CONFIG_TB0229)
void (*f)(void) = (void *) 0xbfc00000;
f();
#endif
fprintf(stderr, "*** reset failed ***\n"); fprintf(stderr, "*** reset failed ***\n");
return 0; return 0;
} }
void flush_cache(ulong start_addr, ulong size) void flush_cache(ulong start_addr, ulong size)
{ {
unsigned long lsize = CFG_CACHELINE_SIZE;
unsigned long addr = start_addr & ~(lsize - 1);
unsigned long aend = (start_addr + size - 1) & ~(lsize - 1);
while (1) {
cache_op(Hit_Writeback_Inv_D, start_addr);
cache_op(Hit_Invalidate_I, start_addr);
if (addr == aend)
break;
addr += lsize;
}
} }
void write_one_tlb(int index, u32 pagemask, u32 hi, u32 low0, u32 low1) void write_one_tlb(int index, u32 pagemask, u32 hi, u32 low0, u32 low1)

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@ -27,6 +27,30 @@
#include <asm/regdef.h> #include <asm/regdef.h>
#include <asm/mipsregs.h> #include <asm/mipsregs.h>
/*
* For the moment disable interrupts, mark the kernel mode and
* set ST0_KX so that the CPU does not spit fire when using
* 64-bit addresses.
*/
.macro setup_c0_status set clr
.set push
mfc0 t0, CP0_STATUS
or t0, ST0_CU0 | \set | 0x1f | \clr
xor t0, 0x1f | \clr
mtc0 t0, CP0_STATUS
.set noreorder
sll zero, 3 # ehb
.set pop
.endm
.macro setup_c0_status_reset
#ifdef CONFIG_64BIT
setup_c0_status ST0_KX 0
#else
setup_c0_status 0 0
#endif
.endm
#define RVECENT(f,n) \ #define RVECENT(f,n) \
b f; nop b f; nop
#define XVECENT(f,bev) \ #define XVECENT(f,bev) \
@ -211,19 +235,11 @@ reset:
mtc0 zero, CP0_WATCHLO mtc0 zero, CP0_WATCHLO
mtc0 zero, CP0_WATCHHI mtc0 zero, CP0_WATCHHI
/* STATUS register */ /* WP(Watch Pending), SW0/1 should be cleared. */
#ifdef CONFIG_TB0229
li k0, ST0_CU0
#else
mfc0 k0, CP0_STATUS
#endif
li k1, ~ST0_IE
and k0, k1
mtc0 k0, CP0_STATUS
/* CAUSE register */
mtc0 zero, CP0_CAUSE mtc0 zero, CP0_CAUSE
setup_c0_status_reset
/* Init Timer */ /* Init Timer */
mtc0 zero, CP0_COUNT mtc0 zero, CP0_COUNT
mtc0 zero, CP0_COMPARE mtc0 zero, CP0_COMPARE
@ -240,14 +256,6 @@ reset:
1: 1:
lw gp, 0(ra) lw gp, 0(ra)
#ifdef CONFIG_INCA_IP
/* Disable INCA-IP Watchdog.
*/
la t9, disable_incaip_wdt
jalr t9
nop
#endif
/* Initialize any external memory. /* Initialize any external memory.
*/ */
la t9, lowlevel_init la t9, lowlevel_init
@ -267,10 +275,12 @@ reset:
/* Set up temporary stack. /* Set up temporary stack.
*/ */
#ifdef CFG_INIT_RAM_LOCK_MIPS
li a0, CFG_INIT_SP_OFFSET li a0, CFG_INIT_SP_OFFSET
la t9, mips_cache_lock la t9, mips_cache_lock
jalr t9 jalr t9
nop nop
#endif
li t0, CFG_SDRAM_BASE + CFG_INIT_SP_OFFSET li t0, CFG_SDRAM_BASE + CFG_INIT_SP_OFFSET
la sp, 0(t0) la sp, 0(t0)

409
include/asm-mips/asm.h Normal file
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@ -0,0 +1,409 @@
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1995, 1996, 1997, 1999, 2001 by Ralf Baechle
* Copyright (C) 1999 by Silicon Graphics, Inc.
* Copyright (C) 2001 MIPS Technologies, Inc.
* Copyright (C) 2002 Maciej W. Rozycki
*
* Some useful macros for MIPS assembler code
*
* Some of the routines below contain useless nops that will be optimized
* away by gas in -O mode. These nops are however required to fill delay
* slots in noreorder mode.
*/
#ifndef __ASM_ASM_H
#define __ASM_ASM_H
#include <asm/sgidefs.h>
#ifndef CAT
#ifdef __STDC__
#define __CAT(str1, str2) str1##str2
#else
#define __CAT(str1, str2) str1/**/str2
#endif
#define CAT(str1, str2) __CAT(str1, str2)
#endif
/*
* PIC specific declarations
* Not used for the kernel but here seems to be the right place.
*/
#ifdef __PIC__
#define CPRESTORE(register) \
.cprestore register
#define CPADD(register) \
.cpadd register
#define CPLOAD(register) \
.cpload register
#else
#define CPRESTORE(register)
#define CPADD(register)
#define CPLOAD(register)
#endif
/*
* LEAF - declare leaf routine
*/
#define LEAF(symbol) \
.globl symbol; \
.align 2; \
.type symbol, @function; \
.ent symbol, 0; \
symbol: .frame sp, 0, ra
/*
* NESTED - declare nested routine entry point
*/
#define NESTED(symbol, framesize, rpc) \
.globl symbol; \
.align 2; \
.type symbol, @function; \
.ent symbol, 0; \
symbol: .frame sp, framesize, rpc
/*
* END - mark end of function
*/
#define END(function) \
.end function; \
.size function, .-function
/*
* EXPORT - export definition of symbol
*/
#define EXPORT(symbol) \
.globl symbol; \
symbol:
/*
* FEXPORT - export definition of a function symbol
*/
#define FEXPORT(symbol) \
.globl symbol; \
.type symbol, @function; \
symbol:
/*
* ABS - export absolute symbol
*/
#define ABS(symbol,value) \
.globl symbol; \
symbol = value
#define PANIC(msg) \
.set push; \
.set reorder; \
PTR_LA a0, 8f; \
jal panic; \
9: b 9b; \
.set pop; \
TEXT(msg)
/*
* Print formatted string
*/
#ifdef CONFIG_PRINTK
#define PRINT(string) \
.set push; \
.set reorder; \
PTR_LA a0, 8f; \
jal printk; \
.set pop; \
TEXT(string)
#else
#define PRINT(string)
#endif
#define TEXT(msg) \
.pushsection .data; \
8: .asciiz msg; \
.popsection;
/*
* Build text tables
*/
#define TTABLE(string) \
.pushsection .text; \
.word 1f; \
.popsection \
.pushsection .data; \
1: .asciiz string; \
.popsection
/*
* MIPS IV pref instruction.
* Use with .set noreorder only!
*
* MIPS IV implementations are free to treat this as a nop. The R5000
* is one of them. So we should have an option not to use this instruction.
*/
#ifdef CONFIG_CPU_HAS_PREFETCH
#define PREF(hint,addr) \
.set push; \
.set mips4; \
pref hint, addr; \
.set pop
#define PREFX(hint,addr) \
.set push; \
.set mips4; \
prefx hint, addr; \
.set pop
#else /* !CONFIG_CPU_HAS_PREFETCH */
#define PREF(hint, addr)
#define PREFX(hint, addr)
#endif /* !CONFIG_CPU_HAS_PREFETCH */
/*
* MIPS ISA IV/V movn/movz instructions and equivalents for older CPUs.
*/
#if (_MIPS_ISA == _MIPS_ISA_MIPS1)
#define MOVN(rd, rs, rt) \
.set push; \
.set reorder; \
beqz rt, 9f; \
move rd, rs; \
.set pop; \
9:
#define MOVZ(rd, rs, rt) \
.set push; \
.set reorder; \
bnez rt, 9f; \
move rd, rs; \
.set pop; \
9:
#endif /* _MIPS_ISA == _MIPS_ISA_MIPS1 */
#if (_MIPS_ISA == _MIPS_ISA_MIPS2) || (_MIPS_ISA == _MIPS_ISA_MIPS3)
#define MOVN(rd, rs, rt) \
.set push; \
.set noreorder; \
bnezl rt, 9f; \
move rd, rs; \
.set pop; \
9:
#define MOVZ(rd, rs, rt) \
.set push; \
.set noreorder; \
beqzl rt, 9f; \
move rd, rs; \
.set pop; \
9:
#endif /* (_MIPS_ISA == _MIPS_ISA_MIPS2) || (_MIPS_ISA == _MIPS_ISA_MIPS3) */
#if (_MIPS_ISA == _MIPS_ISA_MIPS4 ) || (_MIPS_ISA == _MIPS_ISA_MIPS5) || \
(_MIPS_ISA == _MIPS_ISA_MIPS32) || (_MIPS_ISA == _MIPS_ISA_MIPS64)
#define MOVN(rd, rs, rt) \
movn rd, rs, rt
#define MOVZ(rd, rs, rt) \
movz rd, rs, rt
#endif /* MIPS IV, MIPS V, MIPS32 or MIPS64 */
/*
* Stack alignment
*/
#if (_MIPS_SIM == _MIPS_SIM_ABI32)
#define ALSZ 7
#define ALMASK ~7
#endif
#if (_MIPS_SIM == _MIPS_SIM_NABI32) || (_MIPS_SIM == _MIPS_SIM_ABI64)
#define ALSZ 15
#define ALMASK ~15
#endif
/*
* Macros to handle different pointer/register sizes for 32/64-bit code
*/
/*
* Size of a register
*/
#ifdef __mips64
#define SZREG 8
#else
#define SZREG 4
#endif
/*
* Use the following macros in assemblercode to load/store registers,
* pointers etc.
*/
#if (_MIPS_SIM == _MIPS_SIM_ABI32)
#define REG_S sw
#define REG_L lw
#define REG_SUBU subu
#define REG_ADDU addu
#endif
#if (_MIPS_SIM == _MIPS_SIM_NABI32) || (_MIPS_SIM == _MIPS_SIM_ABI64)
#define REG_S sd
#define REG_L ld
#define REG_SUBU dsubu
#define REG_ADDU daddu
#endif
/*
* How to add/sub/load/store/shift C int variables.
*/
#if (_MIPS_SZINT == 32)
#define INT_ADD add
#define INT_ADDU addu
#define INT_ADDI addi
#define INT_ADDIU addiu
#define INT_SUB sub
#define INT_SUBU subu
#define INT_L lw
#define INT_S sw
#define INT_SLL sll
#define INT_SLLV sllv
#define INT_SRL srl
#define INT_SRLV srlv
#define INT_SRA sra
#define INT_SRAV srav
#endif
#if (_MIPS_SZINT == 64)
#define INT_ADD dadd
#define INT_ADDU daddu
#define INT_ADDI daddi
#define INT_ADDIU daddiu
#define INT_SUB dsub
#define INT_SUBU dsubu
#define INT_L ld
#define INT_S sd
#define INT_SLL dsll
#define INT_SLLV dsllv
#define INT_SRL dsrl
#define INT_SRLV dsrlv
#define INT_SRA dsra
#define INT_SRAV dsrav
#endif
/*
* How to add/sub/load/store/shift C long variables.
*/
#if (_MIPS_SZLONG == 32)
#define LONG_ADD add
#define LONG_ADDU addu
#define LONG_ADDI addi
#define LONG_ADDIU addiu
#define LONG_SUB sub
#define LONG_SUBU subu
#define LONG_L lw
#define LONG_S sw
#define LONG_SLL sll
#define LONG_SLLV sllv
#define LONG_SRL srl
#define LONG_SRLV srlv
#define LONG_SRA sra
#define LONG_SRAV srav
#define LONG .word
#define LONGSIZE 4
#define LONGMASK 3
#define LONGLOG 2
#endif
#if (_MIPS_SZLONG == 64)
#define LONG_ADD dadd
#define LONG_ADDU daddu
#define LONG_ADDI daddi
#define LONG_ADDIU daddiu
#define LONG_SUB dsub
#define LONG_SUBU dsubu
#define LONG_L ld
#define LONG_S sd
#define LONG_SLL dsll
#define LONG_SLLV dsllv
#define LONG_SRL dsrl
#define LONG_SRLV dsrlv
#define LONG_SRA dsra
#define LONG_SRAV dsrav
#define LONG .dword
#define LONGSIZE 8
#define LONGMASK 7
#define LONGLOG 3
#endif
/*
* How to add/sub/load/store/shift pointers.
*/
#if (_MIPS_SZPTR == 32)
#define PTR_ADD add
#define PTR_ADDU addu
#define PTR_ADDI addi
#define PTR_ADDIU addiu
#define PTR_SUB sub
#define PTR_SUBU subu
#define PTR_L lw
#define PTR_S sw
#define PTR_LA la
#define PTR_LI li
#define PTR_SLL sll
#define PTR_SLLV sllv
#define PTR_SRL srl
#define PTR_SRLV srlv
#define PTR_SRA sra
#define PTR_SRAV srav
#define PTR_SCALESHIFT 2
#define PTR .word
#define PTRSIZE 4
#define PTRLOG 2
#endif
#if (_MIPS_SZPTR == 64)
#define PTR_ADD dadd
#define PTR_ADDU daddu
#define PTR_ADDI daddi
#define PTR_ADDIU daddiu
#define PTR_SUB dsub
#define PTR_SUBU dsubu
#define PTR_L ld
#define PTR_S sd
#define PTR_LA dla
#define PTR_LI dli
#define PTR_SLL dsll
#define PTR_SLLV dsllv
#define PTR_SRL dsrl
#define PTR_SRLV dsrlv
#define PTR_SRA dsra
#define PTR_SRAV dsrav
#define PTR_SCALESHIFT 3
#define PTR .dword
#define PTRSIZE 8
#define PTRLOG 3
#endif
/*
* Some cp0 registers were extended to 64bit for MIPS III.
*/
#if (_MIPS_SIM == _MIPS_SIM_ABI32)
#define MFC0 mfc0
#define MTC0 mtc0
#endif
#if (_MIPS_SIM == _MIPS_SIM_NABI32) || (_MIPS_SIM == _MIPS_SIM_ABI64)
#define MFC0 dmfc0
#define MTC0 dmtc0
#endif
#define SSNOP sll zero, zero, 1
#ifdef CONFIG_SGI_IP28
/* Inhibit speculative stores to volatile (e.g.DMA) or invalid addresses. */
#include <asm/cacheops.h>
#define R10KCBARRIER(addr) cache Cache_Barrier, addr;
#else
#define R10KCBARRIER(addr)
#endif
#endif /* __ASM_ASM_H */

View file

@ -1,18 +1,62 @@
/* $Id: byteorder.h,v 1.8 1998/11/02 09:29:32 ralf Exp $ /*
*
* This file is subject to the terms and conditions of the GNU General Public * This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive * License. See the file "COPYING" in the main directory of this archive
* for more details. * for more details.
* *
* Copyright (C) by Ralf Baechle * Copyright (C) 1996, 99, 2003 by Ralf Baechle
*/ */
#ifndef _MIPS_BYTEORDER_H #ifndef _ASM_BYTEORDER_H
#define _MIPS_BYTEORDER_H #define _ASM_BYTEORDER_H
#include <asm/types.h> #include <asm/types.h>
#ifdef __GNUC__ #ifdef __GNUC__
#ifdef CONFIG_CPU_MIPSR2
static __inline__ __attribute_const__ __u16 ___arch__swab16(__u16 x)
{
__asm__(
" wsbh %0, %1 \n"
: "=r" (x)
: "r" (x));
return x;
}
#define __arch__swab16(x) ___arch__swab16(x)
static __inline__ __attribute_const__ __u32 ___arch__swab32(__u32 x)
{
__asm__(
" wsbh %0, %1 \n"
" rotr %0, %0, 16 \n"
: "=r" (x)
: "r" (x));
return x;
}
#define __arch__swab32(x) ___arch__swab32(x)
#ifdef CONFIG_CPU_MIPS64_R2
static __inline__ __attribute_const__ __u64 ___arch__swab64(__u64 x)
{
__asm__(
" dsbh %0, %1 \n"
" dshd %0, %0 \n"
" drotr %0, %0, 32 \n"
: "=r" (x)
: "r" (x));
return x;
}
#define __arch__swab64(x) ___arch__swab64(x)
#endif /* CONFIG_CPU_MIPS64_R2 */
#endif /* CONFIG_CPU_MIPSR2 */
#if !defined(__STRICT_ANSI__) || defined(__KERNEL__) #if !defined(__STRICT_ANSI__) || defined(__KERNEL__)
# define __BYTEORDER_HAS_U64__ # define __BYTEORDER_HAS_U64__
# define __SWAB_64_THRU_32__ # define __SWAB_64_THRU_32__
@ -20,12 +64,12 @@
#endif /* __GNUC__ */ #endif /* __GNUC__ */
#if defined (__MIPSEB__) #if defined(__MIPSEB__)
# include <linux/byteorder/big_endian.h> # include <linux/byteorder/big_endian.h>
#elif defined (__MIPSEL__) #elif defined(__MIPSEL__)
# include <linux/byteorder/little_endian.h> # include <linux/byteorder/little_endian.h>
#else #else
# error "MIPS, but neither __MIPSEB__, nor __MIPSEL__???" # error "MIPS, but neither __MIPSEB__, nor __MIPSEL__???"
#endif #endif
#endif /* _MIPS_BYTEORDER_H */ #endif /* _ASM_BYTEORDER_H */

View file

@ -1,10 +1,12 @@
/* /*
* cachectl.h -- defines for MIPS cache control system calls * This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
* *
* Copyright (C) 1994, 1995, 1996 by Ralf Baechle * Copyright (C) 1994, 1995, 1996 by Ralf Baechle
*/ */
#ifndef __ASM_MIPS_CACHECTL #ifndef _ASM_CACHECTL
#define __ASM_MIPS_CACHECTL #define _ASM_CACHECTL
/* /*
* Options for cacheflush system call * Options for cacheflush system call
@ -21,4 +23,4 @@
#define CACHEABLE 0 /* make pages cacheable */ #define CACHEABLE 0 /* make pages cacheable */
#define UNCACHEABLE 1 /* make pages uncacheable */ #define UNCACHEABLE 1 /* make pages uncacheable */
#endif /* __ASM_MIPS_CACHECTL */ #endif /* _ASM_CACHECTL */

View file

@ -5,43 +5,81 @@
* License. See the file "COPYING" in the main directory of this archive * License. See the file "COPYING" in the main directory of this archive
* for more details. * for more details.
* *
* (C) Copyright 1996, 1997 by Ralf Baechle * (C) Copyright 1996, 97, 99, 2002, 03 Ralf Baechle
* (C) Copyright 1999 Silicon Graphics, Inc.
*/ */
#ifndef __ASM_MIPS_CACHEOPS_H #ifndef __ASM_CACHEOPS_H
#define __ASM_MIPS_CACHEOPS_H #define __ASM_CACHEOPS_H
/* /*
* Cache Operations * Cache Operations available on all MIPS processors with R4000-style caches
*/ */
#define Index_Invalidate_I 0x00 #define Index_Invalidate_I 0x00
#define Index_Writeback_Inv_D 0x01 #define Index_Writeback_Inv_D 0x01
#define Index_Invalidate_SI 0x02
#define Index_Writeback_Inv_SD 0x03
#define Index_Load_Tag_I 0x04 #define Index_Load_Tag_I 0x04
#define Index_Load_Tag_D 0x05 #define Index_Load_Tag_D 0x05
#define Index_Load_Tag_SI 0x06
#define Index_Load_Tag_SD 0x07
#define Index_Store_Tag_I 0x08 #define Index_Store_Tag_I 0x08
#define Index_Store_Tag_D 0x09 #define Index_Store_Tag_D 0x09
#define Index_Store_Tag_SI 0x0A #if defined(CONFIG_CPU_LOONGSON2)
#define Index_Store_Tag_SD 0x0B #define Hit_Invalidate_I 0x00
#define Create_Dirty_Excl_D 0x0d #else
#define Create_Dirty_Excl_SD 0x0f
#define Hit_Invalidate_I 0x10 #define Hit_Invalidate_I 0x10
#endif
#define Hit_Invalidate_D 0x11 #define Hit_Invalidate_D 0x11
#define Hit_Invalidate_SI 0x12
#define Hit_Invalidate_SD 0x13
#define Fill 0x14
#define Hit_Writeback_Inv_D 0x15 #define Hit_Writeback_Inv_D 0x15
/* 0x16 is unused */
#define Hit_Writeback_Inv_SD 0x17 /*
* R4000-specific cacheops
*/
#define Create_Dirty_Excl_D 0x0d
#define Fill 0x14
#define Hit_Writeback_I 0x18 #define Hit_Writeback_I 0x18
#define Hit_Writeback_D 0x19 #define Hit_Writeback_D 0x19
/* 0x1a is unused */
/*
* R4000SC and R4400SC-specific cacheops
*/
#define Index_Invalidate_SI 0x02
#define Index_Writeback_Inv_SD 0x03
#define Index_Load_Tag_SI 0x06
#define Index_Load_Tag_SD 0x07
#define Index_Store_Tag_SI 0x0A
#define Index_Store_Tag_SD 0x0B
#define Create_Dirty_Excl_SD 0x0f
#define Hit_Invalidate_SI 0x12
#define Hit_Invalidate_SD 0x13
#define Hit_Writeback_Inv_SD 0x17
#define Hit_Writeback_SD 0x1b #define Hit_Writeback_SD 0x1b
/* 0x1c is unused */
/* 0x1e is unused */
#define Hit_Set_Virtual_SI 0x1e #define Hit_Set_Virtual_SI 0x1e
#define Hit_Set_Virtual_SD 0x1f #define Hit_Set_Virtual_SD 0x1f
#endif /* __ASM_MIPS_CACHEOPS_H */ /*
* R5000-specific cacheops
*/
#define R5K_Page_Invalidate_S 0x17
/*
* RM7000-specific cacheops
*/
#define Page_Invalidate_T 0x16
/*
* R10000-specific cacheops
*
* Cacheops 0x02, 0x06, 0x0a, 0x0c-0x0e, 0x16, 0x1a and 0x1e are unused.
* Most of the _S cacheops are identical to the R4000SC _SD cacheops.
*/
#define Index_Writeback_Inv_S 0x03
#define Index_Load_Tag_S 0x07
#define Index_Store_Tag_S 0x0B
#define Hit_Invalidate_S 0x13
#define Cache_Barrier 0x14
#define Hit_Writeback_Inv_S 0x17
#define Index_Load_Data_I 0x18
#define Index_Load_Data_D 0x19
#define Index_Load_Data_S 0x1b
#define Index_Store_Data_I 0x1c
#define Index_Store_Data_D 0x1d
#define Index_Store_Data_S 0x1f
#endif /* __ASM_CACHEOPS_H */

View file

@ -1,16 +1,15 @@
/* /*
* Various ISA level dependant constants. * Various ISA level dependent constants.
* Most of the following constants reflect the different layout * Most of the following constants reflect the different layout
* of Coprocessor 0 registers. * of Coprocessor 0 registers.
* *
* Copyright (c) 1998 Harald Koerfgen * Copyright (c) 1998 Harald Koerfgen
*/ */
#include <linux/config.h>
#ifndef __ASM_ISADEP_H #ifndef __ASM_ISADEP_H
#define __ASM_ISADEP_H #define __ASM_ISADEP_H
#if defined(CONFIG_CPU_R3000) #if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
/* /*
* R2000 or R3000 * R2000 or R3000
*/ */

View file

@ -4,9 +4,9 @@
* for more details. * for more details.
* *
* Copyright (C) 1994 Waldorf GMBH * Copyright (C) 1994 Waldorf GMBH
* Copyright (C) 1995, 1996, 1997, 1998, 1999, 2001 Ralf Baechle * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2001, 2002, 2003 Ralf Baechle
* Copyright (C) 1996 Paul M. Antoine * Copyright (C) 1996 Paul M. Antoine
* Copyright (C) 1999 Silicon Graphics, Inc. * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
*/ */
#ifndef _ASM_PROCESSOR_H #ifndef _ASM_PROCESSOR_H
#define _ASM_PROCESSOR_H #define _ASM_PROCESSOR_H
@ -15,92 +15,26 @@
#include <asm/isadep.h> #include <asm/isadep.h>
/*
* Default implementation of macro that returns current
* instruction pointer ("program counter").
*/
#define current_text_addr() ({ __label__ _l; _l: &&_l;})
#if !defined (_LANGUAGE_ASSEMBLY)
#if 0
#include <linux/threads.h>
#endif
#include <asm/cachectl.h> #include <asm/cachectl.h>
#include <asm/mipsregs.h> #include <asm/mipsregs.h>
#include <asm/reg.h> #include <asm/reg.h>
#include <asm/system.h> #include <asm/system.h>
struct mips_cpuinfo { /*
unsigned long udelay_val; * Return current * instruction pointer ("program counter").
unsigned long *pgd_quick; */
unsigned long *pte_quick; #define current_text_addr() ({ __label__ _l; _l: &&_l;})
unsigned long pgtable_cache_sz;
};
/* /*
* System setup and hardware flags.. * System setup and hardware flags..
* XXX: Should go into mips_cpuinfo.
*/ */
extern void (*cpu_wait)(void); /* only available on R4[26]00 and R3081 */ extern void (*cpu_wait)(void);
extern void r3081_wait(void);
extern void r4k_wait(void);
extern char cyclecounter_available; /* only available from R4000 upwards. */
extern struct mips_cpuinfo boot_cpu_data;
extern unsigned int vced_count, vcei_count; extern unsigned int vced_count, vcei_count;
#ifdef CONFIG_SMP
extern struct mips_cpuinfo cpu_data[];
#define current_cpu_data cpu_data[smp_processor_id()]
#else
#define cpu_data &boot_cpu_data
#define current_cpu_data boot_cpu_data
#endif
/*
* Bus types (default is ISA, but people can check others with these..)
* MCA_bus hardcoded to 0 for now.
*
* This needs to be extended since MIPS systems are being delivered with
* numerous different types of bus systems.
*/
extern int EISA_bus;
#define MCA_bus 0
#define MCA_bus__is_a_macro /* for versions in ksyms.c */
/*
* MIPS has no problems with write protection
*/
#define wp_works_ok 1
#define wp_works_ok__is_a_macro /* for versions in ksyms.c */
/* Lazy FPU handling on uni-processor */
extern struct task_struct *last_task_used_math;
/*
* User space process size: 2GB. This is hardcoded into a few places,
* so don't change it unless you know what you are doing. TASK_SIZE
* for a 64 bit kernel expandable to 8192EB, of which the current MIPS
* implementations will "only" be able to use 1TB ...
*/
#define TASK_SIZE (0x7fff8000UL)
/* This decides where the kernel will search for a free chunk of vm
* space during mmap's.
*/
#define TASK_UNMAPPED_BASE (TASK_SIZE / 3)
/*
* Size of io_bitmap in longwords: 32 is ports 0-0x3ff.
*/
#define IO_BITMAP_SIZE 32
#define NUM_FPU_REGS 32 #define NUM_FPU_REGS 32
struct mips_fpu_hard_struct { typedef __u64 fpureg_t;
double fp_regs[NUM_FPU_REGS];
unsigned int control;
};
/* /*
* It would be nice to add some more fields for emulator statistics, but there * It would be nice to add some more fields for emulator statistics, but there
@ -108,25 +42,29 @@ struct mips_fpu_hard_struct {
* be recalculated by hand. So the additional information will be private to * be recalculated by hand. So the additional information will be private to
* the FPU emulator for now. See asm-mips/fpu_emulator.h. * the FPU emulator for now. See asm-mips/fpu_emulator.h.
*/ */
typedef u64 fpureg_t;
struct mips_fpu_soft_struct { struct mips_fpu_struct {
fpureg_t regs[NUM_FPU_REGS]; fpureg_t fpr[NUM_FPU_REGS];
unsigned int sr; unsigned int fcr31;
}; };
union mips_fpu_union { #define NUM_DSP_REGS 6
struct mips_fpu_hard_struct hard;
struct mips_fpu_soft_struct soft;
};
#define INIT_FPU { \ typedef __u32 dspreg_t;
{{0,},} \
} struct mips_dsp_state {
dspreg_t dspr[NUM_DSP_REGS];
unsigned int dspcontrol;
};
typedef struct { typedef struct {
unsigned long seg; unsigned long seg;
} mm_segment_t; } mm_segment_t;
#define ARCH_MIN_TASKALIGN 8
struct mips_abi;
/* /*
* If you change thread_struct remember to change the #defines below too! * If you change thread_struct remember to change the #defines below too!
*/ */
@ -140,131 +78,36 @@ struct thread_struct {
unsigned long cp0_status; unsigned long cp0_status;
/* Saved fpu/fpu emulator stuff. */ /* Saved fpu/fpu emulator stuff. */
union mips_fpu_union fpu; struct mips_fpu_struct fpu;
#ifdef CONFIG_MIPS_MT_FPAFF
/* Emulated instruction count */
unsigned long emulated_fp;
/* Saved per-thread scheduler affinity mask */
cpumask_t user_cpus_allowed;
#endif /* CONFIG_MIPS_MT_FPAFF */
/* Saved state of the DSP ASE, if available. */
struct mips_dsp_state dsp;
/* Other stuff associated with the thread. */ /* Other stuff associated with the thread. */
unsigned long cp0_badvaddr; /* Last user fault */ unsigned long cp0_badvaddr; /* Last user fault */
unsigned long cp0_baduaddr; /* Last kernel fault accessing USEG */ unsigned long cp0_baduaddr; /* Last kernel fault accessing USEG */
unsigned long error_code; unsigned long error_code;
unsigned long trap_no; unsigned long trap_no;
#define MF_FIXADE 1 /* Fix address errors in software */
#define MF_LOGADE 2 /* Log address errors to syslog */
unsigned long mflags;
mm_segment_t current_ds;
unsigned long irix_trampoline; /* Wheee... */ unsigned long irix_trampoline; /* Wheee... */
unsigned long irix_oldctx; unsigned long irix_oldctx;
struct mips_abi *abi;
/*
* These are really only needed if the full FPU emulator is configured.
* Would be made conditional on MIPS_FPU_EMULATOR if it weren't for the
* fact that having offset.h rebuilt differently for different config
* options would be asking for trouble.
*
* Saved EPC during delay-slot emulation (see math-emu/cp1emu.c)
*/
unsigned long dsemul_epc;
/*
* Pointer to instruction used to induce address error
*/
unsigned long dsemul_aerpc;
}; };
#endif /* !defined (_LANGUAGE_ASSEMBLY) */ struct task_struct;
#define INIT_THREAD { \
/* \
* saved main processor registers \
*/ \
0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, \
/* \
* saved cp0 stuff \
*/ \
0, \
/* \
* saved fpu/fpu emulator stuff \
*/ \
INIT_FPU, \
/* \
* Other stuff associated with the process \
*/ \
0, 0, 0, 0, \
/* \
* For now the default is to fix address errors \
*/ \
MF_FIXADE, { 0 }, 0, 0, \
/* \
* dsemul_epc and dsemul_aerpc should never be used uninitialized, \
* but... \
*/ \
0 ,0 \
}
#ifdef __KERNEL__
#define KERNEL_STACK_SIZE 8192
#if !defined (_LANGUAGE_ASSEMBLY)
/* Free all resources held by a thread. */ /* Free all resources held by a thread. */
#define release_thread(thread) do { } while(0) #define release_thread(thread) do { } while(0)
extern int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags); /* Prepare to copy thread state - unlazy all lazy status */
#define prepare_to_copy(tsk) do { } while (0)
/* Copy and release all segment info associated with a VM */ #define cpu_relax() barrier()
#define copy_segments(p, mm) do { } while(0)
#define release_segments(mm) do { } while(0)
/*
* Return saved PC of a blocked thread.
*/
extern inline unsigned long thread_saved_pc(struct thread_struct *t)
{
extern void ret_from_fork(void);
/* New born processes are a special case */
if (t->reg31 == (unsigned long) ret_from_fork)
return t->reg31;
return ((unsigned long *)t->reg29)[10];
}
/*
* Do necessary setup to start up a newly executed thread.
*/
#define start_thread(regs, new_pc, new_sp) do { \
/* New thread looses kernel privileges. */ \
regs->cp0_status = (regs->cp0_status & ~(ST0_CU0|ST0_KSU)) | KU_USER;\
regs->cp0_epc = new_pc; \
regs->regs[29] = new_sp; \
current->thread.current_ds = USER_DS; \
} while (0)
unsigned long get_wchan(struct task_struct *p);
#define __PT_REG(reg) ((long)&((struct pt_regs *)0)->reg - sizeof(struct pt_regs))
#define __KSTK_TOS(tsk) ((unsigned long)(tsk) + KERNEL_STACK_SIZE - 32)
#define KSTK_EIP(tsk) (*(unsigned long *)(__KSTK_TOS(tsk) + __PT_REG(cp0_epc)))
#define KSTK_ESP(tsk) (*(unsigned long *)(__KSTK_TOS(tsk) + __PT_REG(regs[29])))
/* Allocation and freeing of basic task resources. */
/*
* NOTE! The task struct and the stack go together
*/
#define THREAD_SIZE (2*PAGE_SIZE)
#define alloc_task_struct() \
((struct task_struct *) __get_free_pages(GFP_KERNEL,1))
#define free_task_struct(p) free_pages((unsigned long)(p),1)
#define get_task_struct(tsk) atomic_inc(&virt_to_page(tsk)->count)
#define init_task (init_task_union.task)
#define init_stack (init_task_union.stack)
#define cpu_relax() do { } while (0)
#endif /* !defined (_LANGUAGE_ASSEMBLY) */
#endif /* __KERNEL__ */
/* /*
* Return_address is a replacement for __builtin_return_address(count) * Return_address is a replacement for __builtin_return_address(count)
@ -280,4 +123,20 @@ unsigned long get_wchan(struct task_struct *p);
*/ */
#define return_address() ({__asm__ __volatile__("":::"$31");__builtin_return_address(0);}) #define return_address() ({__asm__ __volatile__("":::"$31");__builtin_return_address(0);})
#ifdef CONFIG_CPU_HAS_PREFETCH
#define ARCH_HAS_PREFETCH
static inline void prefetch(const void *addr)
{
__asm__ __volatile__(
" .set mips4 \n"
" pref %0, (%1) \n"
" .set mips0 \n"
:
: "i" (Pref_Load), "r" (addr));
}
#endif
#endif /* _ASM_PROCESSOR_H */ #endif /* _ASM_PROCESSOR_H */

View file

@ -3,17 +3,12 @@
* License. See the file "COPYING" in the main directory of this archive * License. See the file "COPYING" in the main directory of this archive
* for more details. * for more details.
* *
* Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2000 by Ralf Baechle * Copyright (C) 1994, 95, 96, 97, 98, 99, 2000 by Ralf Baechle
* * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
* Machine dependent structs and defines to help the user use
* the ptrace system call.
*/ */
#ifndef _ASM_PTRACE_H #ifndef _ASM_PTRACE_H
#define _ASM_PTRACE_H #define _ASM_PTRACE_H
#include <asm/isadep.h>
#include <linux/types.h>
/* 0 - 31 are integer registers, 32 - 63 are fp registers. */ /* 0 - 31 are integer registers, 32 - 63 are fp registers. */
#define FPR_BASE 32 #define FPR_BASE 32
#define PC 64 #define PC 64
@ -23,63 +18,69 @@
#define MMLO 68 #define MMLO 68
#define FPC_CSR 69 #define FPC_CSR 69
#define FPC_EIR 70 #define FPC_EIR 70
#define DSP_BASE 71 /* 3 more hi / lo register pairs */
#define DSP_CONTROL 77
#define ACX 78
#ifndef _LANGUAGE_ASSEMBLY
/* /*
* This struct defines the way the registers are stored on the stack during a * This struct defines the way the registers are stored on the stack during a
* system call/exception. As usual the registers k0/k1 aren't being saved. * system call/exception. As usual the registers k0/k1 aren't being saved.
*/ */
struct pt_regs { struct pt_regs {
#ifdef CONFIG_32BIT
/* Pad bytes for argument save space on the stack. */ /* Pad bytes for argument save space on the stack. */
unsigned long pad0[6]; unsigned long pad0[6];
#endif
/* Saved main processor registers. */ /* Saved main processor registers. */
unsigned long regs[32]; unsigned long regs[32];
/* Other saved registers. */ /* Saved special registers. */
unsigned long lo;
unsigned long hi;
/*
* saved cp0 registers
*/
unsigned long cp0_epc;
unsigned long cp0_badvaddr;
unsigned long cp0_status; unsigned long cp0_status;
unsigned long hi;
unsigned long lo;
#ifdef CONFIG_CPU_HAS_SMARTMIPS
unsigned long acx;
#endif
unsigned long cp0_badvaddr;
unsigned long cp0_cause; unsigned long cp0_cause;
}; unsigned long cp0_epc;
#ifdef CONFIG_MIPS_MT_SMTC
#endif /* !(_LANGUAGE_ASSEMBLY) */ unsigned long cp0_tcstatus;
#endif /* CONFIG_MIPS_MT_SMTC */
} __attribute__ ((aligned (8)));
/* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */ /* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */
/* #define PTRACE_GETREGS 12 */ #define PTRACE_GETREGS 12
/* #define PTRACE_SETREGS 13 */ #define PTRACE_SETREGS 13
/* #define PTRACE_GETFPREGS 14 */ #define PTRACE_GETFPREGS 14
/* #define PTRACE_SETFPREGS 15 */ #define PTRACE_SETFPREGS 15
/* #define PTRACE_GETFPXREGS 18 */ /* #define PTRACE_GETFPXREGS 18 */
/* #define PTRACE_SETFPXREGS 19 */ /* #define PTRACE_SETFPXREGS 19 */
#define PTRACE_SETOPTIONS 21 #define PTRACE_OLDSETOPTIONS 21
/* options set using PTRACE_SETOPTIONS */ #define PTRACE_GET_THREAD_AREA 25
#define PTRACE_O_TRACESYSGOOD 0x00000001 #define PTRACE_SET_THREAD_AREA 26
#if 0 /* def _LANGUAGE_ASSEMBLY */ /* Calls to trace a 64bit program from a 32bit program. */
#include <asm/offset.h> #define PTRACE_PEEKTEXT_3264 0xc0
#endif #define PTRACE_PEEKDATA_3264 0xc1
#define PTRACE_POKETEXT_3264 0xc2
#define PTRACE_POKEDATA_3264 0xc3
#define PTRACE_GET_THREAD_AREA_3264 0xc4
#ifdef __KERNEL__ #ifdef __KERNEL__
#ifndef _LANGUAGE_ASSEMBLY #include <asm/isadep.h>
/* /*
* Does the process account for user or for system time? * Does the process account for user or for system time?
*/ */
#define user_mode(regs) (((regs)->cp0_status & KU_MASK) == KU_USER) #define user_mode(regs) (((regs)->cp0_status & KU_MASK) == KU_USER)
#define instruction_pointer(regs) ((regs)->cp0_epc) #define instruction_pointer(regs) ((regs)->cp0_epc)
#define profile_pc(regs) instruction_pointer(regs)
extern void show_regs(struct pt_regs *);
#endif /* !(_LANGUAGE_ASSEMBLY) */
#endif #endif

14
include/asm-mips/reboot.h Normal file
View file

@ -0,0 +1,14 @@
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1997, 1999, 2001, 06 by Ralf Baechle
* Copyright (C) 2001 MIPS Technologies, Inc.
*/
#ifndef _ASM_REBOOT_H
#define _ASM_REBOOT_H
extern void _machine_restart(void);
#endif /* _ASM_REBOOT_H */

View file

@ -7,48 +7,50 @@
* for more details. * for more details.
* *
* Copyright (C) 1995, 1999 by Ralf Baechle * Copyright (C) 1995, 1999 by Ralf Baechle
* Copyright (C) 1995, 1999 Silicon Graphics
*/ */
#ifndef __ASM_MIPS_REG_H #ifndef __ASM_MIPS_REG_H
#define __ASM_MIPS_REG_H #define __ASM_MIPS_REG_H
/* #if defined(CONFIG_32BIT) || defined(WANT_COMPAT_REG_H)
* This defines/structures correspond to the register layout on stack -
* if the order here is changed, it needs to be updated in #define EF_R0 6
* include/asm-mips/stackframe.h #define EF_R1 7
*/ #define EF_R2 8
#define EF_REG0 6 #define EF_R3 9
#define EF_REG1 7 #define EF_R4 10
#define EF_REG2 8 #define EF_R5 11
#define EF_REG3 9 #define EF_R6 12
#define EF_REG4 10 #define EF_R7 13
#define EF_REG5 11 #define EF_R8 14
#define EF_REG6 12 #define EF_R9 15
#define EF_REG7 13 #define EF_R10 16
#define EF_REG8 14 #define EF_R11 17
#define EF_REG9 15 #define EF_R12 18
#define EF_REG10 16 #define EF_R13 19
#define EF_REG11 17 #define EF_R14 20
#define EF_REG12 18 #define EF_R15 21
#define EF_REG13 19 #define EF_R16 22
#define EF_REG14 20 #define EF_R17 23
#define EF_REG15 21 #define EF_R18 24
#define EF_REG16 22 #define EF_R19 25
#define EF_REG17 23 #define EF_R20 26
#define EF_REG18 24 #define EF_R21 27
#define EF_REG19 25 #define EF_R22 28
#define EF_REG20 26 #define EF_R23 29
#define EF_REG21 27 #define EF_R24 30
#define EF_REG22 28 #define EF_R25 31
#define EF_REG23 29
#define EF_REG24 30
#define EF_REG25 31
/* /*
* k0/k1 unsaved * k0/k1 unsaved
*/ */
#define EF_REG28 34 #define EF_R26 32
#define EF_REG29 35 #define EF_R27 33
#define EF_REG30 36
#define EF_REG31 37 #define EF_R28 34
#define EF_R29 35
#define EF_R30 36
#define EF_R31 37
/* /*
* Saved special registers * Saved special registers
@ -59,8 +61,66 @@
#define EF_CP0_EPC 40 #define EF_CP0_EPC 40
#define EF_CP0_BADVADDR 41 #define EF_CP0_BADVADDR 41
#define EF_CP0_STATUS 42 #define EF_CP0_STATUS 42
#define EF_CP0_CAUSE 44 #define EF_CP0_CAUSE 43
#define EF_UNUSED0 44
#define EF_SIZE 180 /* size in bytes */ #define EF_SIZE 180
#endif
#ifdef CONFIG_64BIT
#define EF_R0 0
#define EF_R1 1
#define EF_R2 2
#define EF_R3 3
#define EF_R4 4
#define EF_R5 5
#define EF_R6 6
#define EF_R7 7
#define EF_R8 8
#define EF_R9 9
#define EF_R10 10
#define EF_R11 11
#define EF_R12 12
#define EF_R13 13
#define EF_R14 14
#define EF_R15 15
#define EF_R16 16
#define EF_R17 17
#define EF_R18 18
#define EF_R19 19
#define EF_R20 20
#define EF_R21 21
#define EF_R22 22
#define EF_R23 23
#define EF_R24 24
#define EF_R25 25
/*
* k0/k1 unsaved
*/
#define EF_R26 26
#define EF_R27 27
#define EF_R28 28
#define EF_R29 29
#define EF_R30 30
#define EF_R31 31
/*
* Saved special registers
*/
#define EF_LO 32
#define EF_HI 33
#define EF_CP0_EPC 34
#define EF_CP0_BADVADDR 35
#define EF_CP0_STATUS 36
#define EF_CP0_CAUSE 37
#define EF_SIZE 304 /* size in bytes */
#endif /* CONFIG_64BIT */
#endif /* __ASM_MIPS_REG_H */ #endif /* __ASM_MIPS_REG_H */

View file

@ -1,52 +1,100 @@
/* /*
* include/asm-mips/regdefs.h
*
* This file is subject to the terms and conditions of the GNU General Public * This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive * License. See the file "COPYING" in the main directory of this archive
* for more details. * for more details.
* *
* Copyright (C) 1994, 1995 by Ralf Baechle * Copyright (C) 1985 MIPS Computer Systems, Inc.
* Copyright (C) 1994, 95, 99, 2003 by Ralf Baechle
* Copyright (C) 1990 - 1992, 1999 Silicon Graphics, Inc.
*/ */
#ifndef _ASM_REGDEF_H
#define _ASM_REGDEF_H
#ifndef __ASM_MIPS_REGDEF_H #include <asm/sgidefs.h>
#define __ASM_MIPS_REGDEF_H
#if _MIPS_SIM == _MIPS_SIM_ABI32
/* /*
* Symbolic register names for 32 bit ABI * Symbolic register names for 32 bit ABI
*/ */
#define zero $0 /* wired zero */ #define zero $0 /* wired zero */
#define AT $1 /* assembler temp - uppercase because of ".set at" */ #define AT $1 /* assembler temp - uppercase because of ".set at" */
#define v0 $2 /* return value */ #define v0 $2 /* return value */
#define v1 $3 #define v1 $3
#define a0 $4 /* argument registers */ #define a0 $4 /* argument registers */
#define a1 $5 #define a1 $5
#define a2 $6 #define a2 $6
#define a3 $7 #define a3 $7
#define t0 $8 /* caller saved */ #define t0 $8 /* caller saved */
#define t1 $9 #define t1 $9
#define t2 $10 #define t2 $10
#define t3 $11 #define t3 $11
#define t4 $12 #define t4 $12
#define t5 $13 #define t5 $13
#define t6 $14 #define t6 $14
#define t7 $15 #define t7 $15
#define s0 $16 /* callee saved */ #define s0 $16 /* callee saved */
#define s1 $17 #define s1 $17
#define s2 $18 #define s2 $18
#define s3 $19 #define s3 $19
#define s4 $20 #define s4 $20
#define s5 $21 #define s5 $21
#define s6 $22 #define s6 $22
#define s7 $23 #define s7 $23
#define t8 $24 /* caller saved */ #define t8 $24 /* caller saved */
#define t9 $25 #define t9 $25
#define jp $25 /* PIC jump register */ #define jp $25 /* PIC jump register */
#define k0 $26 /* kernel scratch */ #define k0 $26 /* kernel scratch */
#define k1 $27 #define k1 $27
#define gp $28 /* global pointer */ #define gp $28 /* global pointer */
#define sp $29 /* stack pointer */ #define sp $29 /* stack pointer */
#define fp $30 /* frame pointer */ #define fp $30 /* frame pointer */
#define s8 $30 /* same like fp! */ #define s8 $30 /* same like fp! */
#define ra $31 /* return address */ #define ra $31 /* return address */
#endif /* __ASM_MIPS_REGDEF_H */ #endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */
#if _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32
#define zero $0 /* wired zero */
#define AT $at /* assembler temp - uppercase because of ".set at" */
#define v0 $2 /* return value - caller saved */
#define v1 $3
#define a0 $4 /* argument registers */
#define a1 $5
#define a2 $6
#define a3 $7
#define a4 $8 /* arg reg 64 bit; caller saved in 32 bit */
#define ta0 $8
#define a5 $9
#define ta1 $9
#define a6 $10
#define ta2 $10
#define a7 $11
#define ta3 $11
#define t0 $12 /* caller saved */
#define t1 $13
#define t2 $14
#define t3 $15
#define s0 $16 /* callee saved */
#define s1 $17
#define s2 $18
#define s3 $19
#define s4 $20
#define s5 $21
#define s6 $22
#define s7 $23
#define t8 $24 /* caller saved */
#define t9 $25 /* callee address for PIC/temp */
#define jp $25 /* PIC jump register */
#define k0 $26 /* kernel temporary */
#define k1 $27
#define gp $28 /* global pointer - caller saved for PIC */
#define sp $29 /* stack pointer */
#define fp $30 /* frame pointer */
#define s8 $30 /* callee saved */
#define ra $31 /* return address */
#endif /* _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32 */
#endif /* _ASM_REGDEF_H */

View file

@ -1,5 +1,4 @@
/* $Id: types.h,v 1.3 1999/08/18 23:37:50 ralf Exp $ /*
*
* This file is subject to the terms and conditions of the GNU General Public * This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive * License. See the file "COPYING" in the main directory of this archive
* for more details. * for more details.
@ -10,6 +9,8 @@
#ifndef _ASM_TYPES_H #ifndef _ASM_TYPES_H
#define _ASM_TYPES_H #define _ASM_TYPES_H
#ifndef __ASSEMBLY__
typedef unsigned short umode_t; typedef unsigned short umode_t;
/* /*
@ -40,11 +41,17 @@ __extension__ typedef unsigned long long __u64;
#endif #endif
#endif /* __ASSEMBLY__ */
/* /*
* These aren't exported outside the kernel to avoid name space clashes * These aren't exported outside the kernel to avoid name space clashes
*/ */
#ifdef __KERNEL__ #ifdef __KERNEL__
#define BITS_PER_LONG _MIPS_SZLONG
#ifndef __ASSEMBLY__
typedef __signed char s8; typedef __signed char s8;
typedef unsigned char u8; typedef unsigned char u8;
@ -68,9 +75,24 @@ typedef unsigned long long u64;
#endif #endif
#define BITS_PER_LONG _MIPS_SZLONG #if (defined(CONFIG_HIGHMEM) && defined(CONFIG_64BIT_PHYS_ADDR)) \
|| defined(CONFIG_64BIT)
typedef u64 dma_addr_t;
#else
typedef u32 dma_addr_t;
#endif
typedef u64 dma64_addr_t;
typedef unsigned long dma_addr_t; /*
* Don't use phys_t. You've been warned.
*/
#ifdef CONFIG_64BIT_PHYS_ADDR
typedef unsigned long long phys_t;
#else
typedef unsigned long phys_t;
#endif
#endif /* __ASSEMBLY__ */
#endif /* __KERNEL__ */ #endif /* __KERNEL__ */