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Merge branch 'rmobile' of git://git.denx.de/u-boot-sh

Browse source
This commit is contained in:
Tom Rini 2015-06-01 07:16:36 -04:00
commit 656ae05273
8 changed files with 323 additions and 50 deletions
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22
arch/arm/cpu/armv7/rmobile/Kconfig
View file

@ -50,6 +50,28 @@ config RMOBILE_EXTRAM_BOOT
depends on TARGET_ALT || TARGET_KOELSCH || TARGET_LAGER || TARGET_PORTER || TARGET_SILK
default n
choice
prompt "Qos setting primary"
depends on TARGET_ALT || TARGET_GOSE || TARGET_KOELSCH || TARGET_LAGER
default QOS_PRI_NORMAL
config QOS_PRI_NORMAL
bool "Non primary"
help
Select normal mode for QoS setting.
config QOS_PRI_MEDIA
bool "Media primary"
help
Select multimedia primary mode for QoS setting.
config QOS_PRI_GFX
bool "GFX primary"
help
Select GFX(graphics) primary mode for QoS setting.
endchoice
source "board/atmark-techno/armadillo-800eva/Kconfig"
source "board/renesas/gose/Kconfig"
source "board/renesas/koelsch/Kconfig"

4
arch/arm/include/asm/arch-rmobile/r8a7794.h
View file

@ -32,4 +32,8 @@
#define CONFIG_SYS_SH_SDHI2_BASE 0xEE160000
#define CONFIG_SYS_SH_SDHI_NR_CHANNEL 3
#define R8A7794_CUT_ES2 2
#define IS_R8A7794_ES2() \
(rmobile_get_cpu_rev_integer() == R8A7794_CUT_ES2)
#endif /* __ASM_ARCH_R8A7794_H */

9
board/renesas/alt/Kconfig
View file

@ -9,4 +9,13 @@ config SYS_VENDOR
config SYS_CONFIG_NAME
default "alt"
config R8A7794_ETHERNET_B
bool "Use ethernet B function"
depends on TARGET_ALT
default n
help
ALT board can use default ethernet and etnernet B function.
This config set pin function of ethenet B. You also needt to change
DIP switch of board in order to use this function.
endif

17
board/renesas/alt/alt.c
View file

@ -1,7 +1,7 @@
/*
* board/renesas/alt/alt.c
*
* Copyright (C) 2014 Renesas Electronics Corporation
* Copyright (C) 2014, 2015 Renesas Electronics Corporation
*
* SPDX-License-Identifier: GPL-2.0
*/
@ -94,6 +94,20 @@ int board_init(void)
r8a7794_pinmux_init();
/* Ether Enable */
#if defined(CONFIG_R8A7794_ETHERNET_B)
gpio_request(GPIO_FN_ETH_CRS_DV_B, NULL);
gpio_request(GPIO_FN_ETH_RX_ER_B, NULL);
gpio_request(GPIO_FN_ETH_RXD0_B, NULL);
gpio_request(GPIO_FN_ETH_RXD1_B, NULL);
gpio_request(GPIO_FN_ETH_LINK_B, NULL);
gpio_request(GPIO_FN_ETH_REFCLK_B, NULL);
gpio_request(GPIO_FN_ETH_MDIO_B, NULL);
gpio_request(GPIO_FN_ETH_TXD1_B, NULL);
gpio_request(GPIO_FN_ETH_TX_EN_B, NULL);
gpio_request(GPIO_FN_ETH_MAGIC_B, NULL);
gpio_request(GPIO_FN_ETH_TXD0_B, NULL);
gpio_request(GPIO_FN_ETH_MDC_B, NULL);
#else
gpio_request(GPIO_FN_ETH_CRS_DV, NULL);
gpio_request(GPIO_FN_ETH_RX_ER, NULL);
gpio_request(GPIO_FN_ETH_RXD0, NULL);
@ -106,6 +120,7 @@ int board_init(void)
gpio_request(GPIO_FN_ETH_MAGIC, NULL);
gpio_request(GPIO_FN_ETH_TXD0, NULL);
gpio_request(GPIO_FN_ETH_MDC, NULL);
#endif
gpio_request(GPIO_FN_IRQ8, NULL);
/* PHY reset */

76
board/renesas/alt/qos.c
View file

@ -14,7 +14,7 @@
#include <asm/arch/rmobile.h>
#if defined(CONFIG_RMOBILE_EXTRAM_BOOT)
/* QoS version 0.11 */
/* QoS version 0.311 for ES1 and version 0.321 for ES2 */
enum {
DBSC3_00, DBSC3_01, DBSC3_02, DBSC3_03, DBSC3_04,
@ -62,6 +62,24 @@ static u32 dbsc3_0_w_qos_addr[DBSC3_NR] = {
[DBSC3_15] = DBSC3_0_QOS_W15_BASE,
};
#if defined(CONFIG_QOS_PRI_MEDIA)
#define is_qos_pri_media() 1
#else
#define is_qos_pri_media() 0
#endif
#if defined(CONFIG_QOS_PRI_NORMAL)
#define is_qos_pri_normal() 1
#else
#define is_qos_pri_normal() 0
#endif
#if defined(CONFIG_QOS_PRI_GFX)
#define is_qos_pri_gfx() 1
#else
#define is_qos_pri_gfx() 0
#endif
void qos_init(void)
{
int i;
@ -77,30 +95,57 @@ void qos_init(void)
/* S3C -QoS */
s3c = (struct rcar_s3c *)S3C_BASE;
writel(0x1F0D0B0A, &s3c->s3crorr);
writel(0x1F0D0B09, &s3c->s3cworr);
if (is_qos_pri_media()) {
writel(0x1F0B0604, &s3c->s3crorr);
writel(0x1F0E0705, &s3c->s3cworr);
} else if (is_qos_pri_normal()) {
writel(0x1F0B0908, &s3c->s3crorr);
writel(0x1F0E0A08, &s3c->s3cworr);
} else if (is_qos_pri_media()) {
writel(0x1F0B0B0B, &s3c->s3crorr);
writel(0x1F0E0C0C, &s3c->s3cworr);
}
/* QoS Control Registers */
s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI0_BASE;
writel(0x00890089, &s3c_qos->s3cqos0);
writel(0x20960010, &s3c_qos->s3cqos1);
writel(0x20302030, &s3c_qos->s3cqos2);
writel(0x20AA2200, &s3c_qos->s3cqos3);
if (is_qos_pri_media())
writel(0x20AA2300, &s3c_qos->s3cqos3);
else if (is_qos_pri_normal())
writel(0x20AA2200, &s3c_qos->s3cqos3);
else if (is_qos_pri_media())
writel(0x20AA2100, &s3c_qos->s3cqos3);
writel(0x00002032, &s3c_qos->s3cqos4);
writel(0x20960010, &s3c_qos->s3cqos5);
writel(0x20302030, &s3c_qos->s3cqos6);
writel(0x20AA2200, &s3c_qos->s3cqos7);
if (is_qos_pri_media())
writel(0x20AA2300, &s3c_qos->s3cqos7);
else if (is_qos_pri_normal())
writel(0x20AA2200, &s3c_qos->s3cqos7);
else if (is_qos_pri_gfx())
writel(0x20AA2100, &s3c_qos->s3cqos7);
writel(0x00002032, &s3c_qos->s3cqos8);
s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI1_BASE;
writel(0x00890089, &s3c_qos->s3cqos0);
writel(0x20960010, &s3c_qos->s3cqos1);
writel(0x20302030, &s3c_qos->s3cqos2);
writel(0x20AA2200, &s3c_qos->s3cqos3);
if (is_qos_pri_media())
writel(0x20AA2300, &s3c_qos->s3cqos3);
else if (is_qos_pri_normal())
writel(0x20AA2200, &s3c_qos->s3cqos3);
else if (is_qos_pri_gfx())
writel(0x20AA2100, &s3c_qos->s3cqos3);
writel(0x00002032, &s3c_qos->s3cqos4);
writel(0x20960010, &s3c_qos->s3cqos5);
writel(0x20302030, &s3c_qos->s3cqos6);
writel(0x20AA2200, &s3c_qos->s3cqos7);
if (is_qos_pri_media())
writel(0x20AA2300, &s3c_qos->s3cqos7);
else if (is_qos_pri_media())
writel(0x20AA2200, &s3c_qos->s3cqos7);
else if (is_qos_pri_media())
writel(0x20AA2100, &s3c_qos->s3cqos7);
writel(0x00002032, &s3c_qos->s3cqos8);
s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_MXI_BASE;
@ -115,7 +160,7 @@ void qos_init(void)
writel(0x00002032, &s3c_qos->s3cqos8);
s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_AXI_BASE;
writel(0x00820082, &s3c_qos->s3cqos0);
writel(0x00820092, &s3c_qos->s3cqos0);
writel(0x20960020, &s3c_qos->s3cqos1);
writel(0x20302030, &s3c_qos->s3cqos2);
writel(0x20AA20FA, &s3c_qos->s3cqos3);
@ -157,8 +202,13 @@ void qos_init(void)
}
/* CCI-400 -QoS */
writel(0x20000800, CCI_400_MAXOT_1);
writel(0x20000800, CCI_400_MAXOT_2);
if (IS_R8A7794_ES2()) {
writel(0x20001000, CCI_400_MAXOT_1);
writel(0x20001000, CCI_400_MAXOT_2);
} else {
writel(0x20000800, CCI_400_MAXOT_1);
writel(0x20000800, CCI_400_MAXOT_2);
}
writel(0x0000000C, CCI_400_QOSCNTL_1);
writel(0x0000000C, CCI_400_QOSCNTL_2);
@ -166,7 +216,7 @@ void qos_init(void)
/* Transaction Control (MXI) */
mxi = (struct rcar_mxi *)MXI_BASE;
writel(0x00000013, &mxi->mxrtcr);
writel(0x00000013, &mxi->mxwtcr);
writel(0x00000016, &mxi->mxwtcr);
writel(0x00780080, &mxi->mxsaar0);
writel(0x02000800, &mxi->mxsaar1);
@ -449,7 +499,7 @@ void qos_init(void)
/* QoS Register (RT-AXI) */
axi_qos = (struct rcar_axi_qos *)RT_AXI_SHX_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002053, &axi_qos->qosctset0);
writel(0x00002096, &axi_qos->qosctset1);
writel(0x00002030, &axi_qos->qosctset2);

72
board/renesas/gose/qos.c
View file

@ -14,7 +14,7 @@
#include <asm/arch/rmobile.h>
#if defined(CONFIG_RMOBILE_EXTRAM_BOOT)
/* QoS version 0.20 */
/* QoS version 0.311 */
enum {
DBSC3_00, DBSC3_01, DBSC3_02, DBSC3_03, DBSC3_04,
DBSC3_05, DBSC3_06, DBSC3_07, DBSC3_08, DBSC3_09,
@ -61,6 +61,24 @@ static u32 dbsc3_0_w_qos_addr[DBSC3_NR] = {
[DBSC3_15] = DBSC3_0_QOS_W15_BASE,
};
#if defined(CONFIG_QOS_PRI_MEDIA)
#define is_qos_pri_media() 1
#else
#define is_qos_pri_media() 0
#endif
#if defined(CONFIG_QOS_PRI_NORMAL)
#define is_qos_pri_normal() 1
#else
#define is_qos_pri_normal() 0
#endif
#if defined(CONFIG_QOS_PRI_GFX)
#define is_qos_pri_gfx() 1
#else
#define is_qos_pri_gfx() 0
#endif
void qos_init(void)
{
int i;
@ -77,34 +95,62 @@ void qos_init(void)
/* S3C -QoS */
s3c = (struct rcar_s3c *)S3C_BASE;
writel(0x00000000, &s3c->s3cadsplcr);
writel(0x1F0B0908, &s3c->s3crorr);
writel(0x1F0C0A08, &s3c->s3cworr);
if (is_qos_pri_media()) {
writel(0x1F0B0604, &s3c->s3crorr);
writel(0x1F0E0705, &s3c->s3cworr);
} else if (is_qos_pri_normal()) {
writel(0x1F0B0908, &s3c->s3crorr);
writel(0x1F0C0A08, &s3c->s3cworr);
} else if (is_qos_pri_gfx()) {
writel(0x1F0B0B0B, &s3c->s3crorr);
writel(0x1F0E0C0C, &s3c->s3cworr);
}
/* QoS Control Registers */
s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI0_BASE;
writel(0x00890089, &s3c_qos->s3cqos0);
writel(0x20960010, &s3c_qos->s3cqos1);
writel(0x20302030, &s3c_qos->s3cqos2);
writel(0x20AA2200, &s3c_qos->s3cqos3);
if (is_qos_pri_media())
writel(0x20AA2300, &s3c_qos->s3cqos3);
else if (is_qos_pri_normal())
writel(0x20AA2200, &s3c_qos->s3cqos3);
else if (is_qos_pri_gfx())
writel(0x20AA2100, &s3c_qos->s3cqos3);
writel(0x00002032, &s3c_qos->s3cqos4);
writel(0x20960010, &s3c_qos->s3cqos5);
writel(0x20302030, &s3c_qos->s3cqos6);
writel(0x20AA2200, &s3c_qos->s3cqos7);
if (is_qos_pri_media())
writel(0x20AA2300, &s3c_qos->s3cqos7);
else if (is_qos_pri_normal())
writel(0x20AA2200, &s3c_qos->s3cqos7);
else if (is_qos_pri_gfx())
writel(0x20AA2100, &s3c_qos->s3cqos7);
writel(0x00002032, &s3c_qos->s3cqos8);
s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI1_BASE;
writel(0x00890089, &s3c_qos->s3cqos0);
writel(0x20960010, &s3c_qos->s3cqos1);
writel(0x20302030, &s3c_qos->s3cqos2);
writel(0x20AA2200, &s3c_qos->s3cqos3);
if (is_qos_pri_media())
writel(0x20AA2300, &s3c_qos->s3cqos3);
else if (is_qos_pri_normal())
writel(0x20AA2200, &s3c_qos->s3cqos3);
else if (is_qos_pri_gfx())
writel(0x20AA2100, &s3c_qos->s3cqos3);
writel(0x00002032, &s3c_qos->s3cqos4);
writel(0x20960010, &s3c_qos->s3cqos5);
writel(0x20302030, &s3c_qos->s3cqos6);
writel(0x20AA2200, &s3c_qos->s3cqos7);
if (is_qos_pri_media())
writel(0x20AA2300, &s3c_qos->s3cqos7);
else if (is_qos_pri_normal())
writel(0x20AA2200, &s3c_qos->s3cqos7);
else if (is_qos_pri_gfx())
writel(0x20AA2100, &s3c_qos->s3cqos7);
writel(0x00002032, &s3c_qos->s3cqos4);
writel(0x00002032, &s3c_qos->s3cqos8);
s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_MXI_BASE;
writel(0x00820082, &s3c_qos->s3cqos0);
writel(0x00820092, &s3c_qos->s3cqos0);
writel(0x20960020, &s3c_qos->s3cqos1);
writel(0x20302030, &s3c_qos->s3cqos2);
writel(0x20AA20DC, &s3c_qos->s3cqos3);
@ -115,7 +161,7 @@ void qos_init(void)
writel(0x00002032, &s3c_qos->s3cqos8);
s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_AXI_BASE;
writel(0x00820082, &s3c_qos->s3cqos0);
writel(0x00820092, &s3c_qos->s3cqos0);
writel(0x20960020, &s3c_qos->s3cqos1);
writel(0x20302030, &s3c_qos->s3cqos2);
writel(0x20AA20FA, &s3c_qos->s3cqos3);
@ -166,11 +212,13 @@ void qos_init(void)
/* Transaction Control (MXI) */
mxi = (struct rcar_mxi *)MXI_BASE;
writel(0x00000013, &mxi->mxrtcr);
writel(0x00000013, &mxi->mxwtcr);
writel(0x00000016, &mxi->mxwtcr);
writel(0x00200000, &mxi->mxs3cracr);
writel(0x00200000, &mxi->mxs3cwacr);
writel(0x00200000, &mxi->mxaxiracr);
writel(0x00200000, &mxi->mxaxiwacr);
writel(0x00780080, &mxi->mxsaar0);
writel(0x02000800, &mxi->mxsaar1);
/* QoS Control (MXI) */
mxi_qos = (struct rcar_mxi_qos *)MXI_QOS_BASE;
@ -554,7 +602,7 @@ void qos_init(void)
/* QoS Register (RT-AXI) */
axi_qos = (struct rcar_axi_qos *)RT_AXI_SHX_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002053, &axi_qos->qosctset0);
writel(0x00002096, &axi_qos->qosctset1);
writel(0x00002030, &axi_qos->qosctset2);

104
board/renesas/koelsch/qos.c
View file

@ -13,7 +13,7 @@
#include <asm/io.h>
#include <asm/arch/rmobile.h>
/* QoS version 0.240 for ES1 and version 0.334 for ES2 */
/* QoS version 0.240 for ES1 and version 0.411 for ES2 */
#if defined(CONFIG_RMOBILE_EXTRAM_BOOT)
enum {
DBSC3_00, DBSC3_01, DBSC3_02, DBSC3_03, DBSC3_04,
@ -99,6 +99,24 @@ static u32 dbsc3_1_w_qos_addr[DBSC3_NR] = {
[DBSC3_15] = DBSC3_1_QOS_W15_BASE,
};
#if defined(CONFIG_QOS_PRI_MEDIA)
#define is_qos_pri_media() 1
#else
#define is_qos_pri_media() 0
#endif
#if defined(CONFIG_QOS_PRI_NORMAL)
#define is_qos_pri_normal() 1
#else
#define is_qos_pri_normal() 0
#endif
#if defined(CONFIG_QOS_PRI_GFX)
#define is_qos_pri_gfx() 1
#else
#define is_qos_pri_gfx() 0
#endif
void qos_init(void)
{
int i;
@ -124,8 +142,17 @@ void qos_init(void)
/* writel(0x00DF1B0C, &s3c->s3cadsplcr); */
/* Ssplit All mode */
/* writel(0x00FF1B0C, &s3c->s3cadsplcr); */
writel(0x1F0B0908, &s3c->s3crorr);
writel(0x1F0C0A08, &s3c->s3cworr);
if (is_qos_pri_media()) {
writel(0x1F0B0604, &s3c->s3crorr);
writel(0x1F0E0705, &s3c->s3cworr);
} else if (is_qos_pri_normal()) {
writel(0x1F0B0908, &s3c->s3crorr);
writel(0x1F0E0A08, &s3c->s3cworr);
} else if (is_qos_pri_gfx()) {
writel(0x1F0B0B0B, &s3c->s3crorr);
writel(0x1F0E0C0C, &s3c->s3cworr);
}
} else {
writel(0x00FF1B1D, &s3c->s3cadsplcr);
writel(0x1F0D0C0C, &s3c->s3crorr);
@ -136,26 +163,67 @@ void qos_init(void)
writel(0x00890089, &s3c_qos->s3cqos0);
writel(0x20960010, &s3c_qos->s3cqos1);
writel(0x20302030, &s3c_qos->s3cqos2);
writel(0x20AA2200, &s3c_qos->s3cqos3);
if (IS_R8A7791_ES2()) {
if (is_qos_pri_media())
writel(0x20AA2300, &s3c_qos->s3cqos3);
else if (is_qos_pri_normal())
writel(0x20AA2200, &s3c_qos->s3cqos3);
else if (is_qos_pri_gfx())
writel(0x20AA2100, &s3c_qos->s3cqos3);
} else {
writel(0x20AA2200, &s3c_qos->s3cqos3);
}
writel(0x00002032, &s3c_qos->s3cqos4);
writel(0x20960010, &s3c_qos->s3cqos5);
writel(0x20302030, &s3c_qos->s3cqos6);
writel(0x20AA2200, &s3c_qos->s3cqos7);
if (IS_R8A7791_ES2()) {
if (is_qos_pri_media())
writel(0x20AA2300, &s3c_qos->s3cqos7);
else if (is_qos_pri_normal())
writel(0x20AA2200, &s3c_qos->s3cqos7);
else if (is_qos_pri_gfx())
writel(0x20AA2100, &s3c_qos->s3cqos7);
} else {
writel(0x20AA2200, &s3c_qos->s3cqos7);
}
writel(0x00002032, &s3c_qos->s3cqos8);
s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI1_BASE;
writel(0x00890089, &s3c_qos->s3cqos0);
writel(0x20960010, &s3c_qos->s3cqos1);
writel(0x20302030, &s3c_qos->s3cqos2);
writel(0x20AA2200, &s3c_qos->s3cqos3);
if (IS_R8A7791_ES2()) {
if (is_qos_pri_media())
writel(0x20AA2300, &s3c_qos->s3cqos3);
else if (is_qos_pri_normal())
writel(0x20AA2200, &s3c_qos->s3cqos3);
else if (is_qos_pri_gfx())
writel(0x20AA2100, &s3c_qos->s3cqos3);
} else {
writel(0x20AA2200, &s3c_qos->s3cqos3);
}
writel(0x00002032, &s3c_qos->s3cqos4);
writel(0x20960010, &s3c_qos->s3cqos5);
writel(0x20302030, &s3c_qos->s3cqos6);
writel(0x20AA2200, &s3c_qos->s3cqos7);
if (IS_R8A7791_ES2()) {
if (is_qos_pri_media())
writel(0x20AA2300, &s3c_qos->s3cqos7);
else if (is_qos_pri_normal())
writel(0x20AA2200, &s3c_qos->s3cqos7);
else if (is_qos_pri_gfx())
writel(0x20AA2100, &s3c_qos->s3cqos7);
} else {
writel(0x20AA2200, &s3c_qos->s3cqos7);
}
writel(0x00002032, &s3c_qos->s3cqos8);
s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_MXI_BASE;
writel(0x00820082, &s3c_qos->s3cqos0);
if (IS_R8A7791_ES2())
writel(0x80928092, &s3c_qos->s3cqos0);
else
writel(0x00820082, &s3c_qos->s3cqos0);
writel(0x20960020, &s3c_qos->s3cqos1);
writel(0x20302030, &s3c_qos->s3cqos2);
writel(0x20AA20DC, &s3c_qos->s3cqos3);
@ -166,7 +234,10 @@ void qos_init(void)
writel(0x00002032, &s3c_qos->s3cqos8);
s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_AXI_BASE;
writel(0x00820082, &s3c_qos->s3cqos0);
if (IS_R8A7791_ES2())
writel(0x80928092, &s3c_qos->s3cqos0);
else
writel(0x00820082, &s3c_qos->s3cqos0);
writel(0x20960020, &s3c_qos->s3cqos1);
writel(0x20302030, &s3c_qos->s3cqos2);
writel(0x20AA20FA, &s3c_qos->s3cqos3);
@ -245,9 +316,15 @@ void qos_init(void)
/* MXI -QoS */
/* Transaction Control (MXI) */
mxi = (struct rcar_mxi *)MXI_BASE;
mxi = (struct rcar_mxi *)XI_BASE;
writel(0x00000013, &mxi->mxrtcr);
writel(0x00000013, &mxi->mxwtcr);
if (IS_R8A7791_ES2()) {
writel(0x00000016, &mxi->mxwtcr);
writel(0x00780080, &mxi->mxsaar0);
writel(0x02000800, &mxi->mxsaar1);
} else {
writel(0x00000013, &mxi->mxwtcr);
}
/* QoS Control (MXI) */
mxi_qos = (struct rcar_mxi_qos *)MXI_QOS_BASE;
@ -632,7 +709,10 @@ void qos_init(void)
/* QoS Register (RT-AXI) */
axi_qos = (struct rcar_axi_qos *)RT_AXI_SHX_BASE;
writel(0x00000000, &axi_qos->qosconf);
if (IS_R8A7791_ES2())
writel(0x00000001, &axi_qos->qosconf);
else
writel(0x00000000, &axi_qos->qosconf);
writel(0x00002053, &axi_qos->qosctset0);
writel(0x00002096, &axi_qos->qosctset1);
writel(0x00002030, &axi_qos->qosctset2);

69
board/renesas/lager/qos.c
View file

@ -12,7 +12,7 @@
#include <asm/io.h>
#include <asm/arch/rmobile.h>
/* QoS version 0.955 for ES1 and version 0.963 for ES2 */
/* QoS version 0.955 for ES1 and version 0.973 for ES2 */
#if defined(CONFIG_RMOBILE_EXTRAM_BOOT)
enum {
DBSC3_00, DBSC3_01, DBSC3_02, DBSC3_03, DBSC3_04,
@ -1133,6 +1133,24 @@ static void qos_init_es1(void)
writel(0x00000000, &axi_qos->qosqon);
}
#if defined(CONFIG_QOS_PRI_MEDIA)
#define is_qos_pri_media() 1
#else
#define is_qos_pri_media() 0
#endif
#if defined(CONFIG_QOS_PRI_NORMAL)
#define is_qos_pri_normal() 1
#else
#define is_qos_pri_normal() 0
#endif
#if defined(CONFIG_QOS_PRI_GFX)
#define is_qos_pri_gfx() 1
#else
#define is_qos_pri_gfx() 0
#endif
/* QoS version 0.963 for ES2 */
static void qos_init_es2(void)
{
@ -1150,30 +1168,57 @@ static void qos_init_es2(void)
/* S3C -QoS */
s3c = (struct rcar_s3c *)S3C_BASE;
writel(0x80000000, &s3c->s3cadsplcr);
writel(0x1F060504, &s3c->s3crorr);
writel(0x1F060503, &s3c->s3cworr);
if (is_qos_pri_media()) {
writel(0x1F060302, &s3c->s3crorr);
writel(0x07070302, &s3c->s3cworr);
} else if (is_qos_pri_normal()) {
writel(0x1F060504, &s3c->s3crorr);
writel(0x07070503, &s3c->s3cworr);
} else if (is_qos_pri_gfx()) {
writel(0x1F060606, &s3c->s3crorr);
writel(0x07070606, &s3c->s3cworr);
}
/* QoS Control Registers */
s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI0_BASE;
writel(0x00890089, &s3c_qos->s3cqos0);
writel(0x20960010, &s3c_qos->s3cqos1);
writel(0x20302030, &s3c_qos->s3cqos2);
writel(0x20AA2200, &s3c_qos->s3cqos3);
if (is_qos_pri_media())
writel(0x20AA2300, &s3c_qos->s3cqos3);
else if (is_qos_pri_normal())
writel(0x20AA2200, &s3c_qos->s3cqos3);
else if (is_qos_pri_gfx())
writel(0x20AA2100, &s3c_qos->s3cqos3);
writel(0x00002032, &s3c_qos->s3cqos4);
writel(0x20960010, &s3c_qos->s3cqos5);
writel(0x20302030, &s3c_qos->s3cqos6);
writel(0x20AA2200, &s3c_qos->s3cqos7);
if (is_qos_pri_media())
writel(0x20AA2300, &s3c_qos->s3cqos7);
else if (is_qos_pri_normal())
writel(0x20AA2200, &s3c_qos->s3cqos7);
else if (is_qos_pri_gfx())
writel(0x20AA2100, &s3c_qos->s3cqos7);
writel(0x00002032, &s3c_qos->s3cqos8);
s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI1_BASE;
writel(0x00890089, &s3c_qos->s3cqos0);
writel(0x20960010, &s3c_qos->s3cqos1);
writel(0x20302030, &s3c_qos->s3cqos2);
writel(0x20AA2200, &s3c_qos->s3cqos3);
if (is_qos_pri_media())
writel(0x20AA2300, &s3c_qos->s3cqos3);
else if (is_qos_pri_normal())
writel(0x20AA2200, &s3c_qos->s3cqos3);
else if (is_qos_pri_gfx())
writel(0x20AA2100, &s3c_qos->s3cqos3);
writel(0x00002032, &s3c_qos->s3cqos4);
writel(0x20960010, &s3c_qos->s3cqos5);
writel(0x20302030, &s3c_qos->s3cqos6);
writel(0x20AA2200, &s3c_qos->s3cqos7);
if (is_qos_pri_media())
writel(0x20AA2300, &s3c_qos->s3cqos7);
else if (is_qos_pri_normal())
writel(0x20AA2200, &s3c_qos->s3cqos7);
else if (is_qos_pri_gfx())
writel(0x20AA2100, &s3c_qos->s3cqos7);
writel(0x00002032, &s3c_qos->s3cqos8);
s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_MXI_BASE;
@ -1188,7 +1233,7 @@ static void qos_init_es2(void)
writel(0x00002032, &s3c_qos->s3cqos8);
s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_AXI_BASE;
writel(0x00820082, &s3c_qos->s3cqos0);
writel(0x00828092, &s3c_qos->s3cqos0);
writel(0x20960020, &s3c_qos->s3cqos1);
writel(0x20302030, &s3c_qos->s3cqos2);
writel(0x20AA20FA, &s3c_qos->s3cqos3);
@ -1198,7 +1243,7 @@ static void qos_init_es2(void)
writel(0x20AA20FA, &s3c_qos->s3cqos7);
writel(0x00002032, &s3c_qos->s3cqos8);
writel(0x00200808, &s3c->s3carcr11);
writel(0x00310808, &s3c->s3carcr11);
/* DBSC -QoS */
/* DBSC0 - Read */
@ -1235,7 +1280,7 @@ static void qos_init_es2(void)
/* Transaction Control (MXI) */
mxi = (struct rcar_mxi *)MXI_BASE;
writel(0x00000013, &mxi->mxrtcr);
writel(0x00000013, &mxi->mxwtcr);
writel(0x00000016, &mxi->mxwtcr);
writel(0x00B800C0, &mxi->mxsaar0);
writel(0x02000800, &mxi->mxsaar1);
@ -1622,7 +1667,7 @@ static void qos_init_es2(void)
/* QoS Register (RT-AXI) */
axi_qos = (struct rcar_axi_qos *)RT_AXI_SHX_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002053, &axi_qos->qosctset0);
writel(0x00002096, &axi_qos->qosctset1);
writel(0x00002030, &axi_qos->qosctset2);