mirror of
https://github.com/Fishwaldo/u-boot.git
synced 2025-03-18 13:11:31 +00:00
Merge branch 'rmobile' of git://git.denx.de/u-boot-sh
This commit is contained in:
commit
656ae05273
8 changed files with 323 additions and 50 deletions
|
@ -50,6 +50,28 @@ config RMOBILE_EXTRAM_BOOT
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depends on TARGET_ALT || TARGET_KOELSCH || TARGET_LAGER || TARGET_PORTER || TARGET_SILK
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default n
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choice
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prompt "Qos setting primary"
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depends on TARGET_ALT || TARGET_GOSE || TARGET_KOELSCH || TARGET_LAGER
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default QOS_PRI_NORMAL
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config QOS_PRI_NORMAL
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bool "Non primary"
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help
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Select normal mode for QoS setting.
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config QOS_PRI_MEDIA
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bool "Media primary"
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help
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Select multimedia primary mode for QoS setting.
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config QOS_PRI_GFX
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bool "GFX primary"
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help
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Select GFX(graphics) primary mode for QoS setting.
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endchoice
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source "board/atmark-techno/armadillo-800eva/Kconfig"
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source "board/renesas/gose/Kconfig"
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source "board/renesas/koelsch/Kconfig"
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@ -32,4 +32,8 @@
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#define CONFIG_SYS_SH_SDHI2_BASE 0xEE160000
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#define CONFIG_SYS_SH_SDHI_NR_CHANNEL 3
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#define R8A7794_CUT_ES2 2
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#define IS_R8A7794_ES2() \
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(rmobile_get_cpu_rev_integer() == R8A7794_CUT_ES2)
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#endif /* __ASM_ARCH_R8A7794_H */
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@ -9,4 +9,13 @@ config SYS_VENDOR
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config SYS_CONFIG_NAME
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default "alt"
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config R8A7794_ETHERNET_B
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bool "Use ethernet B function"
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depends on TARGET_ALT
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default n
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help
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ALT board can use default ethernet and etnernet B function.
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This config set pin function of ethenet B. You also needt to change
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DIP switch of board in order to use this function.
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endif
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@ -1,7 +1,7 @@
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/*
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* board/renesas/alt/alt.c
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*
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* Copyright (C) 2014 Renesas Electronics Corporation
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* Copyright (C) 2014, 2015 Renesas Electronics Corporation
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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@ -94,6 +94,20 @@ int board_init(void)
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r8a7794_pinmux_init();
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/* Ether Enable */
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#if defined(CONFIG_R8A7794_ETHERNET_B)
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gpio_request(GPIO_FN_ETH_CRS_DV_B, NULL);
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gpio_request(GPIO_FN_ETH_RX_ER_B, NULL);
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gpio_request(GPIO_FN_ETH_RXD0_B, NULL);
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gpio_request(GPIO_FN_ETH_RXD1_B, NULL);
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gpio_request(GPIO_FN_ETH_LINK_B, NULL);
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gpio_request(GPIO_FN_ETH_REFCLK_B, NULL);
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gpio_request(GPIO_FN_ETH_MDIO_B, NULL);
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gpio_request(GPIO_FN_ETH_TXD1_B, NULL);
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gpio_request(GPIO_FN_ETH_TX_EN_B, NULL);
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gpio_request(GPIO_FN_ETH_MAGIC_B, NULL);
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gpio_request(GPIO_FN_ETH_TXD0_B, NULL);
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gpio_request(GPIO_FN_ETH_MDC_B, NULL);
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#else
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gpio_request(GPIO_FN_ETH_CRS_DV, NULL);
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gpio_request(GPIO_FN_ETH_RX_ER, NULL);
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gpio_request(GPIO_FN_ETH_RXD0, NULL);
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@ -106,6 +120,7 @@ int board_init(void)
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gpio_request(GPIO_FN_ETH_MAGIC, NULL);
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gpio_request(GPIO_FN_ETH_TXD0, NULL);
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gpio_request(GPIO_FN_ETH_MDC, NULL);
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#endif
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gpio_request(GPIO_FN_IRQ8, NULL);
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/* PHY reset */
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@ -14,7 +14,7 @@
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#include <asm/arch/rmobile.h>
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#if defined(CONFIG_RMOBILE_EXTRAM_BOOT)
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/* QoS version 0.11 */
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/* QoS version 0.311 for ES1 and version 0.321 for ES2 */
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enum {
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DBSC3_00, DBSC3_01, DBSC3_02, DBSC3_03, DBSC3_04,
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@ -62,6 +62,24 @@ static u32 dbsc3_0_w_qos_addr[DBSC3_NR] = {
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[DBSC3_15] = DBSC3_0_QOS_W15_BASE,
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};
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#if defined(CONFIG_QOS_PRI_MEDIA)
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#define is_qos_pri_media() 1
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#else
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#define is_qos_pri_media() 0
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#endif
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#if defined(CONFIG_QOS_PRI_NORMAL)
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#define is_qos_pri_normal() 1
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#else
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#define is_qos_pri_normal() 0
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#endif
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#if defined(CONFIG_QOS_PRI_GFX)
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#define is_qos_pri_gfx() 1
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#else
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#define is_qos_pri_gfx() 0
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#endif
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void qos_init(void)
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{
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int i;
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@ -77,30 +95,57 @@ void qos_init(void)
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/* S3C -QoS */
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s3c = (struct rcar_s3c *)S3C_BASE;
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writel(0x1F0D0B0A, &s3c->s3crorr);
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writel(0x1F0D0B09, &s3c->s3cworr);
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if (is_qos_pri_media()) {
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writel(0x1F0B0604, &s3c->s3crorr);
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writel(0x1F0E0705, &s3c->s3cworr);
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} else if (is_qos_pri_normal()) {
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writel(0x1F0B0908, &s3c->s3crorr);
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writel(0x1F0E0A08, &s3c->s3cworr);
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} else if (is_qos_pri_media()) {
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writel(0x1F0B0B0B, &s3c->s3crorr);
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writel(0x1F0E0C0C, &s3c->s3cworr);
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}
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/* QoS Control Registers */
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s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI0_BASE;
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writel(0x00890089, &s3c_qos->s3cqos0);
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writel(0x20960010, &s3c_qos->s3cqos1);
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writel(0x20302030, &s3c_qos->s3cqos2);
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writel(0x20AA2200, &s3c_qos->s3cqos3);
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if (is_qos_pri_media())
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writel(0x20AA2300, &s3c_qos->s3cqos3);
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else if (is_qos_pri_normal())
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writel(0x20AA2200, &s3c_qos->s3cqos3);
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else if (is_qos_pri_media())
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writel(0x20AA2100, &s3c_qos->s3cqos3);
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writel(0x00002032, &s3c_qos->s3cqos4);
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writel(0x20960010, &s3c_qos->s3cqos5);
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writel(0x20302030, &s3c_qos->s3cqos6);
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writel(0x20AA2200, &s3c_qos->s3cqos7);
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if (is_qos_pri_media())
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writel(0x20AA2300, &s3c_qos->s3cqos7);
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else if (is_qos_pri_normal())
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writel(0x20AA2200, &s3c_qos->s3cqos7);
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else if (is_qos_pri_gfx())
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writel(0x20AA2100, &s3c_qos->s3cqos7);
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writel(0x00002032, &s3c_qos->s3cqos8);
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s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI1_BASE;
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writel(0x00890089, &s3c_qos->s3cqos0);
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writel(0x20960010, &s3c_qos->s3cqos1);
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writel(0x20302030, &s3c_qos->s3cqos2);
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writel(0x20AA2200, &s3c_qos->s3cqos3);
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if (is_qos_pri_media())
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writel(0x20AA2300, &s3c_qos->s3cqos3);
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else if (is_qos_pri_normal())
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writel(0x20AA2200, &s3c_qos->s3cqos3);
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else if (is_qos_pri_gfx())
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writel(0x20AA2100, &s3c_qos->s3cqos3);
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writel(0x00002032, &s3c_qos->s3cqos4);
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writel(0x20960010, &s3c_qos->s3cqos5);
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writel(0x20302030, &s3c_qos->s3cqos6);
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writel(0x20AA2200, &s3c_qos->s3cqos7);
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if (is_qos_pri_media())
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writel(0x20AA2300, &s3c_qos->s3cqos7);
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else if (is_qos_pri_media())
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writel(0x20AA2200, &s3c_qos->s3cqos7);
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else if (is_qos_pri_media())
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writel(0x20AA2100, &s3c_qos->s3cqos7);
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writel(0x00002032, &s3c_qos->s3cqos8);
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s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_MXI_BASE;
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@ -115,7 +160,7 @@ void qos_init(void)
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writel(0x00002032, &s3c_qos->s3cqos8);
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s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_AXI_BASE;
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writel(0x00820082, &s3c_qos->s3cqos0);
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writel(0x00820092, &s3c_qos->s3cqos0);
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writel(0x20960020, &s3c_qos->s3cqos1);
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writel(0x20302030, &s3c_qos->s3cqos2);
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writel(0x20AA20FA, &s3c_qos->s3cqos3);
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@ -157,8 +202,13 @@ void qos_init(void)
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}
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/* CCI-400 -QoS */
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writel(0x20000800, CCI_400_MAXOT_1);
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writel(0x20000800, CCI_400_MAXOT_2);
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if (IS_R8A7794_ES2()) {
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writel(0x20001000, CCI_400_MAXOT_1);
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writel(0x20001000, CCI_400_MAXOT_2);
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} else {
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writel(0x20000800, CCI_400_MAXOT_1);
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writel(0x20000800, CCI_400_MAXOT_2);
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}
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writel(0x0000000C, CCI_400_QOSCNTL_1);
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writel(0x0000000C, CCI_400_QOSCNTL_2);
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@ -166,7 +216,7 @@ void qos_init(void)
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/* Transaction Control (MXI) */
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mxi = (struct rcar_mxi *)MXI_BASE;
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writel(0x00000013, &mxi->mxrtcr);
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writel(0x00000013, &mxi->mxwtcr);
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writel(0x00000016, &mxi->mxwtcr);
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writel(0x00780080, &mxi->mxsaar0);
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writel(0x02000800, &mxi->mxsaar1);
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@ -449,7 +499,7 @@ void qos_init(void)
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/* QoS Register (RT-AXI) */
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axi_qos = (struct rcar_axi_qos *)RT_AXI_SHX_BASE;
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writel(0x00000000, &axi_qos->qosconf);
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writel(0x00000001, &axi_qos->qosconf);
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writel(0x00002053, &axi_qos->qosctset0);
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writel(0x00002096, &axi_qos->qosctset1);
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writel(0x00002030, &axi_qos->qosctset2);
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|
|
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@ -14,7 +14,7 @@
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#include <asm/arch/rmobile.h>
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|
||||
#if defined(CONFIG_RMOBILE_EXTRAM_BOOT)
|
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/* QoS version 0.20 */
|
||||
/* QoS version 0.311 */
|
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enum {
|
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DBSC3_00, DBSC3_01, DBSC3_02, DBSC3_03, DBSC3_04,
|
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DBSC3_05, DBSC3_06, DBSC3_07, DBSC3_08, DBSC3_09,
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||||
|
@ -61,6 +61,24 @@ static u32 dbsc3_0_w_qos_addr[DBSC3_NR] = {
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[DBSC3_15] = DBSC3_0_QOS_W15_BASE,
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};
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|
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#if defined(CONFIG_QOS_PRI_MEDIA)
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#define is_qos_pri_media() 1
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#else
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#define is_qos_pri_media() 0
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#endif
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|
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#if defined(CONFIG_QOS_PRI_NORMAL)
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#define is_qos_pri_normal() 1
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#else
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#define is_qos_pri_normal() 0
|
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#endif
|
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|
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#if defined(CONFIG_QOS_PRI_GFX)
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#define is_qos_pri_gfx() 1
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#else
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#define is_qos_pri_gfx() 0
|
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#endif
|
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|
||||
void qos_init(void)
|
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{
|
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int i;
|
||||
|
@ -77,34 +95,62 @@ void qos_init(void)
|
|||
/* S3C -QoS */
|
||||
s3c = (struct rcar_s3c *)S3C_BASE;
|
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writel(0x00000000, &s3c->s3cadsplcr);
|
||||
writel(0x1F0B0908, &s3c->s3crorr);
|
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writel(0x1F0C0A08, &s3c->s3cworr);
|
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|
||||
if (is_qos_pri_media()) {
|
||||
writel(0x1F0B0604, &s3c->s3crorr);
|
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writel(0x1F0E0705, &s3c->s3cworr);
|
||||
} else if (is_qos_pri_normal()) {
|
||||
writel(0x1F0B0908, &s3c->s3crorr);
|
||||
writel(0x1F0C0A08, &s3c->s3cworr);
|
||||
} else if (is_qos_pri_gfx()) {
|
||||
writel(0x1F0B0B0B, &s3c->s3crorr);
|
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writel(0x1F0E0C0C, &s3c->s3cworr);
|
||||
}
|
||||
/* QoS Control Registers */
|
||||
s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI0_BASE;
|
||||
writel(0x00890089, &s3c_qos->s3cqos0);
|
||||
writel(0x20960010, &s3c_qos->s3cqos1);
|
||||
writel(0x20302030, &s3c_qos->s3cqos2);
|
||||
writel(0x20AA2200, &s3c_qos->s3cqos3);
|
||||
if (is_qos_pri_media())
|
||||
writel(0x20AA2300, &s3c_qos->s3cqos3);
|
||||
else if (is_qos_pri_normal())
|
||||
writel(0x20AA2200, &s3c_qos->s3cqos3);
|
||||
else if (is_qos_pri_gfx())
|
||||
writel(0x20AA2100, &s3c_qos->s3cqos3);
|
||||
writel(0x00002032, &s3c_qos->s3cqos4);
|
||||
writel(0x20960010, &s3c_qos->s3cqos5);
|
||||
writel(0x20302030, &s3c_qos->s3cqos6);
|
||||
writel(0x20AA2200, &s3c_qos->s3cqos7);
|
||||
if (is_qos_pri_media())
|
||||
writel(0x20AA2300, &s3c_qos->s3cqos7);
|
||||
else if (is_qos_pri_normal())
|
||||
writel(0x20AA2200, &s3c_qos->s3cqos7);
|
||||
else if (is_qos_pri_gfx())
|
||||
writel(0x20AA2100, &s3c_qos->s3cqos7);
|
||||
writel(0x00002032, &s3c_qos->s3cqos8);
|
||||
|
||||
s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI1_BASE;
|
||||
writel(0x00890089, &s3c_qos->s3cqos0);
|
||||
writel(0x20960010, &s3c_qos->s3cqos1);
|
||||
writel(0x20302030, &s3c_qos->s3cqos2);
|
||||
writel(0x20AA2200, &s3c_qos->s3cqos3);
|
||||
if (is_qos_pri_media())
|
||||
writel(0x20AA2300, &s3c_qos->s3cqos3);
|
||||
else if (is_qos_pri_normal())
|
||||
writel(0x20AA2200, &s3c_qos->s3cqos3);
|
||||
else if (is_qos_pri_gfx())
|
||||
writel(0x20AA2100, &s3c_qos->s3cqos3);
|
||||
writel(0x00002032, &s3c_qos->s3cqos4);
|
||||
writel(0x20960010, &s3c_qos->s3cqos5);
|
||||
writel(0x20302030, &s3c_qos->s3cqos6);
|
||||
writel(0x20AA2200, &s3c_qos->s3cqos7);
|
||||
if (is_qos_pri_media())
|
||||
writel(0x20AA2300, &s3c_qos->s3cqos7);
|
||||
else if (is_qos_pri_normal())
|
||||
writel(0x20AA2200, &s3c_qos->s3cqos7);
|
||||
else if (is_qos_pri_gfx())
|
||||
writel(0x20AA2100, &s3c_qos->s3cqos7);
|
||||
writel(0x00002032, &s3c_qos->s3cqos4);
|
||||
writel(0x00002032, &s3c_qos->s3cqos8);
|
||||
|
||||
s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_MXI_BASE;
|
||||
writel(0x00820082, &s3c_qos->s3cqos0);
|
||||
writel(0x00820092, &s3c_qos->s3cqos0);
|
||||
writel(0x20960020, &s3c_qos->s3cqos1);
|
||||
writel(0x20302030, &s3c_qos->s3cqos2);
|
||||
writel(0x20AA20DC, &s3c_qos->s3cqos3);
|
||||
|
@ -115,7 +161,7 @@ void qos_init(void)
|
|||
writel(0x00002032, &s3c_qos->s3cqos8);
|
||||
|
||||
s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_AXI_BASE;
|
||||
writel(0x00820082, &s3c_qos->s3cqos0);
|
||||
writel(0x00820092, &s3c_qos->s3cqos0);
|
||||
writel(0x20960020, &s3c_qos->s3cqos1);
|
||||
writel(0x20302030, &s3c_qos->s3cqos2);
|
||||
writel(0x20AA20FA, &s3c_qos->s3cqos3);
|
||||
|
@ -166,11 +212,13 @@ void qos_init(void)
|
|||
/* Transaction Control (MXI) */
|
||||
mxi = (struct rcar_mxi *)MXI_BASE;
|
||||
writel(0x00000013, &mxi->mxrtcr);
|
||||
writel(0x00000013, &mxi->mxwtcr);
|
||||
writel(0x00000016, &mxi->mxwtcr);
|
||||
writel(0x00200000, &mxi->mxs3cracr);
|
||||
writel(0x00200000, &mxi->mxs3cwacr);
|
||||
writel(0x00200000, &mxi->mxaxiracr);
|
||||
writel(0x00200000, &mxi->mxaxiwacr);
|
||||
writel(0x00780080, &mxi->mxsaar0);
|
||||
writel(0x02000800, &mxi->mxsaar1);
|
||||
|
||||
/* QoS Control (MXI) */
|
||||
mxi_qos = (struct rcar_mxi_qos *)MXI_QOS_BASE;
|
||||
|
@ -554,7 +602,7 @@ void qos_init(void)
|
|||
|
||||
/* QoS Register (RT-AXI) */
|
||||
axi_qos = (struct rcar_axi_qos *)RT_AXI_SHX_BASE;
|
||||
writel(0x00000000, &axi_qos->qosconf);
|
||||
writel(0x00000001, &axi_qos->qosconf);
|
||||
writel(0x00002053, &axi_qos->qosctset0);
|
||||
writel(0x00002096, &axi_qos->qosctset1);
|
||||
writel(0x00002030, &axi_qos->qosctset2);
|
||||
|
|
|
@ -13,7 +13,7 @@
|
|||
#include <asm/io.h>
|
||||
#include <asm/arch/rmobile.h>
|
||||
|
||||
/* QoS version 0.240 for ES1 and version 0.334 for ES2 */
|
||||
/* QoS version 0.240 for ES1 and version 0.411 for ES2 */
|
||||
#if defined(CONFIG_RMOBILE_EXTRAM_BOOT)
|
||||
enum {
|
||||
DBSC3_00, DBSC3_01, DBSC3_02, DBSC3_03, DBSC3_04,
|
||||
|
@ -99,6 +99,24 @@ static u32 dbsc3_1_w_qos_addr[DBSC3_NR] = {
|
|||
[DBSC3_15] = DBSC3_1_QOS_W15_BASE,
|
||||
};
|
||||
|
||||
#if defined(CONFIG_QOS_PRI_MEDIA)
|
||||
#define is_qos_pri_media() 1
|
||||
#else
|
||||
#define is_qos_pri_media() 0
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_QOS_PRI_NORMAL)
|
||||
#define is_qos_pri_normal() 1
|
||||
#else
|
||||
#define is_qos_pri_normal() 0
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_QOS_PRI_GFX)
|
||||
#define is_qos_pri_gfx() 1
|
||||
#else
|
||||
#define is_qos_pri_gfx() 0
|
||||
#endif
|
||||
|
||||
void qos_init(void)
|
||||
{
|
||||
int i;
|
||||
|
@ -124,8 +142,17 @@ void qos_init(void)
|
|||
/* writel(0x00DF1B0C, &s3c->s3cadsplcr); */
|
||||
/* Ssplit All mode */
|
||||
/* writel(0x00FF1B0C, &s3c->s3cadsplcr); */
|
||||
writel(0x1F0B0908, &s3c->s3crorr);
|
||||
writel(0x1F0C0A08, &s3c->s3cworr);
|
||||
|
||||
if (is_qos_pri_media()) {
|
||||
writel(0x1F0B0604, &s3c->s3crorr);
|
||||
writel(0x1F0E0705, &s3c->s3cworr);
|
||||
} else if (is_qos_pri_normal()) {
|
||||
writel(0x1F0B0908, &s3c->s3crorr);
|
||||
writel(0x1F0E0A08, &s3c->s3cworr);
|
||||
} else if (is_qos_pri_gfx()) {
|
||||
writel(0x1F0B0B0B, &s3c->s3crorr);
|
||||
writel(0x1F0E0C0C, &s3c->s3cworr);
|
||||
}
|
||||
} else {
|
||||
writel(0x00FF1B1D, &s3c->s3cadsplcr);
|
||||
writel(0x1F0D0C0C, &s3c->s3crorr);
|
||||
|
@ -136,26 +163,67 @@ void qos_init(void)
|
|||
writel(0x00890089, &s3c_qos->s3cqos0);
|
||||
writel(0x20960010, &s3c_qos->s3cqos1);
|
||||
writel(0x20302030, &s3c_qos->s3cqos2);
|
||||
writel(0x20AA2200, &s3c_qos->s3cqos3);
|
||||
|
||||
if (IS_R8A7791_ES2()) {
|
||||
if (is_qos_pri_media())
|
||||
writel(0x20AA2300, &s3c_qos->s3cqos3);
|
||||
else if (is_qos_pri_normal())
|
||||
writel(0x20AA2200, &s3c_qos->s3cqos3);
|
||||
else if (is_qos_pri_gfx())
|
||||
writel(0x20AA2100, &s3c_qos->s3cqos3);
|
||||
} else {
|
||||
writel(0x20AA2200, &s3c_qos->s3cqos3);
|
||||
}
|
||||
writel(0x00002032, &s3c_qos->s3cqos4);
|
||||
writel(0x20960010, &s3c_qos->s3cqos5);
|
||||
writel(0x20302030, &s3c_qos->s3cqos6);
|
||||
writel(0x20AA2200, &s3c_qos->s3cqos7);
|
||||
|
||||
if (IS_R8A7791_ES2()) {
|
||||
if (is_qos_pri_media())
|
||||
writel(0x20AA2300, &s3c_qos->s3cqos7);
|
||||
else if (is_qos_pri_normal())
|
||||
writel(0x20AA2200, &s3c_qos->s3cqos7);
|
||||
else if (is_qos_pri_gfx())
|
||||
writel(0x20AA2100, &s3c_qos->s3cqos7);
|
||||
} else {
|
||||
writel(0x20AA2200, &s3c_qos->s3cqos7);
|
||||
}
|
||||
writel(0x00002032, &s3c_qos->s3cqos8);
|
||||
|
||||
s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI1_BASE;
|
||||
writel(0x00890089, &s3c_qos->s3cqos0);
|
||||
writel(0x20960010, &s3c_qos->s3cqos1);
|
||||
writel(0x20302030, &s3c_qos->s3cqos2);
|
||||
writel(0x20AA2200, &s3c_qos->s3cqos3);
|
||||
if (IS_R8A7791_ES2()) {
|
||||
if (is_qos_pri_media())
|
||||
writel(0x20AA2300, &s3c_qos->s3cqos3);
|
||||
else if (is_qos_pri_normal())
|
||||
writel(0x20AA2200, &s3c_qos->s3cqos3);
|
||||
else if (is_qos_pri_gfx())
|
||||
writel(0x20AA2100, &s3c_qos->s3cqos3);
|
||||
} else {
|
||||
writel(0x20AA2200, &s3c_qos->s3cqos3);
|
||||
}
|
||||
writel(0x00002032, &s3c_qos->s3cqos4);
|
||||
writel(0x20960010, &s3c_qos->s3cqos5);
|
||||
writel(0x20302030, &s3c_qos->s3cqos6);
|
||||
writel(0x20AA2200, &s3c_qos->s3cqos7);
|
||||
if (IS_R8A7791_ES2()) {
|
||||
if (is_qos_pri_media())
|
||||
writel(0x20AA2300, &s3c_qos->s3cqos7);
|
||||
else if (is_qos_pri_normal())
|
||||
writel(0x20AA2200, &s3c_qos->s3cqos7);
|
||||
else if (is_qos_pri_gfx())
|
||||
writel(0x20AA2100, &s3c_qos->s3cqos7);
|
||||
} else {
|
||||
writel(0x20AA2200, &s3c_qos->s3cqos7);
|
||||
}
|
||||
writel(0x00002032, &s3c_qos->s3cqos8);
|
||||
|
||||
s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_MXI_BASE;
|
||||
writel(0x00820082, &s3c_qos->s3cqos0);
|
||||
if (IS_R8A7791_ES2())
|
||||
writel(0x80928092, &s3c_qos->s3cqos0);
|
||||
else
|
||||
writel(0x00820082, &s3c_qos->s3cqos0);
|
||||
writel(0x20960020, &s3c_qos->s3cqos1);
|
||||
writel(0x20302030, &s3c_qos->s3cqos2);
|
||||
writel(0x20AA20DC, &s3c_qos->s3cqos3);
|
||||
|
@ -166,7 +234,10 @@ void qos_init(void)
|
|||
writel(0x00002032, &s3c_qos->s3cqos8);
|
||||
|
||||
s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_AXI_BASE;
|
||||
writel(0x00820082, &s3c_qos->s3cqos0);
|
||||
if (IS_R8A7791_ES2())
|
||||
writel(0x80928092, &s3c_qos->s3cqos0);
|
||||
else
|
||||
writel(0x00820082, &s3c_qos->s3cqos0);
|
||||
writel(0x20960020, &s3c_qos->s3cqos1);
|
||||
writel(0x20302030, &s3c_qos->s3cqos2);
|
||||
writel(0x20AA20FA, &s3c_qos->s3cqos3);
|
||||
|
@ -245,9 +316,15 @@ void qos_init(void)
|
|||
|
||||
/* MXI -QoS */
|
||||
/* Transaction Control (MXI) */
|
||||
mxi = (struct rcar_mxi *)MXI_BASE;
|
||||
mxi = (struct rcar_mxi *)XI_BASE;
|
||||
writel(0x00000013, &mxi->mxrtcr);
|
||||
writel(0x00000013, &mxi->mxwtcr);
|
||||
if (IS_R8A7791_ES2()) {
|
||||
writel(0x00000016, &mxi->mxwtcr);
|
||||
writel(0x00780080, &mxi->mxsaar0);
|
||||
writel(0x02000800, &mxi->mxsaar1);
|
||||
} else {
|
||||
writel(0x00000013, &mxi->mxwtcr);
|
||||
}
|
||||
|
||||
/* QoS Control (MXI) */
|
||||
mxi_qos = (struct rcar_mxi_qos *)MXI_QOS_BASE;
|
||||
|
@ -632,7 +709,10 @@ void qos_init(void)
|
|||
|
||||
/* QoS Register (RT-AXI) */
|
||||
axi_qos = (struct rcar_axi_qos *)RT_AXI_SHX_BASE;
|
||||
writel(0x00000000, &axi_qos->qosconf);
|
||||
if (IS_R8A7791_ES2())
|
||||
writel(0x00000001, &axi_qos->qosconf);
|
||||
else
|
||||
writel(0x00000000, &axi_qos->qosconf);
|
||||
writel(0x00002053, &axi_qos->qosctset0);
|
||||
writel(0x00002096, &axi_qos->qosctset1);
|
||||
writel(0x00002030, &axi_qos->qosctset2);
|
||||
|
|
|
@ -12,7 +12,7 @@
|
|||
#include <asm/io.h>
|
||||
#include <asm/arch/rmobile.h>
|
||||
|
||||
/* QoS version 0.955 for ES1 and version 0.963 for ES2 */
|
||||
/* QoS version 0.955 for ES1 and version 0.973 for ES2 */
|
||||
#if defined(CONFIG_RMOBILE_EXTRAM_BOOT)
|
||||
enum {
|
||||
DBSC3_00, DBSC3_01, DBSC3_02, DBSC3_03, DBSC3_04,
|
||||
|
@ -1133,6 +1133,24 @@ static void qos_init_es1(void)
|
|||
writel(0x00000000, &axi_qos->qosqon);
|
||||
}
|
||||
|
||||
#if defined(CONFIG_QOS_PRI_MEDIA)
|
||||
#define is_qos_pri_media() 1
|
||||
#else
|
||||
#define is_qos_pri_media() 0
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_QOS_PRI_NORMAL)
|
||||
#define is_qos_pri_normal() 1
|
||||
#else
|
||||
#define is_qos_pri_normal() 0
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_QOS_PRI_GFX)
|
||||
#define is_qos_pri_gfx() 1
|
||||
#else
|
||||
#define is_qos_pri_gfx() 0
|
||||
#endif
|
||||
|
||||
/* QoS version 0.963 for ES2 */
|
||||
static void qos_init_es2(void)
|
||||
{
|
||||
|
@ -1150,30 +1168,57 @@ static void qos_init_es2(void)
|
|||
/* S3C -QoS */
|
||||
s3c = (struct rcar_s3c *)S3C_BASE;
|
||||
writel(0x80000000, &s3c->s3cadsplcr);
|
||||
writel(0x1F060504, &s3c->s3crorr);
|
||||
writel(0x1F060503, &s3c->s3cworr);
|
||||
|
||||
if (is_qos_pri_media()) {
|
||||
writel(0x1F060302, &s3c->s3crorr);
|
||||
writel(0x07070302, &s3c->s3cworr);
|
||||
} else if (is_qos_pri_normal()) {
|
||||
writel(0x1F060504, &s3c->s3crorr);
|
||||
writel(0x07070503, &s3c->s3cworr);
|
||||
} else if (is_qos_pri_gfx()) {
|
||||
writel(0x1F060606, &s3c->s3crorr);
|
||||
writel(0x07070606, &s3c->s3cworr);
|
||||
}
|
||||
/* QoS Control Registers */
|
||||
s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI0_BASE;
|
||||
writel(0x00890089, &s3c_qos->s3cqos0);
|
||||
writel(0x20960010, &s3c_qos->s3cqos1);
|
||||
writel(0x20302030, &s3c_qos->s3cqos2);
|
||||
writel(0x20AA2200, &s3c_qos->s3cqos3);
|
||||
if (is_qos_pri_media())
|
||||
writel(0x20AA2300, &s3c_qos->s3cqos3);
|
||||
else if (is_qos_pri_normal())
|
||||
writel(0x20AA2200, &s3c_qos->s3cqos3);
|
||||
else if (is_qos_pri_gfx())
|
||||
writel(0x20AA2100, &s3c_qos->s3cqos3);
|
||||
writel(0x00002032, &s3c_qos->s3cqos4);
|
||||
writel(0x20960010, &s3c_qos->s3cqos5);
|
||||
writel(0x20302030, &s3c_qos->s3cqos6);
|
||||
writel(0x20AA2200, &s3c_qos->s3cqos7);
|
||||
if (is_qos_pri_media())
|
||||
writel(0x20AA2300, &s3c_qos->s3cqos7);
|
||||
else if (is_qos_pri_normal())
|
||||
writel(0x20AA2200, &s3c_qos->s3cqos7);
|
||||
else if (is_qos_pri_gfx())
|
||||
writel(0x20AA2100, &s3c_qos->s3cqos7);
|
||||
writel(0x00002032, &s3c_qos->s3cqos8);
|
||||
|
||||
s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI1_BASE;
|
||||
writel(0x00890089, &s3c_qos->s3cqos0);
|
||||
writel(0x20960010, &s3c_qos->s3cqos1);
|
||||
writel(0x20302030, &s3c_qos->s3cqos2);
|
||||
writel(0x20AA2200, &s3c_qos->s3cqos3);
|
||||
if (is_qos_pri_media())
|
||||
writel(0x20AA2300, &s3c_qos->s3cqos3);
|
||||
else if (is_qos_pri_normal())
|
||||
writel(0x20AA2200, &s3c_qos->s3cqos3);
|
||||
else if (is_qos_pri_gfx())
|
||||
writel(0x20AA2100, &s3c_qos->s3cqos3);
|
||||
writel(0x00002032, &s3c_qos->s3cqos4);
|
||||
writel(0x20960010, &s3c_qos->s3cqos5);
|
||||
writel(0x20302030, &s3c_qos->s3cqos6);
|
||||
writel(0x20AA2200, &s3c_qos->s3cqos7);
|
||||
if (is_qos_pri_media())
|
||||
writel(0x20AA2300, &s3c_qos->s3cqos7);
|
||||
else if (is_qos_pri_normal())
|
||||
writel(0x20AA2200, &s3c_qos->s3cqos7);
|
||||
else if (is_qos_pri_gfx())
|
||||
writel(0x20AA2100, &s3c_qos->s3cqos7);
|
||||
writel(0x00002032, &s3c_qos->s3cqos8);
|
||||
|
||||
s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_MXI_BASE;
|
||||
|
@ -1188,7 +1233,7 @@ static void qos_init_es2(void)
|
|||
writel(0x00002032, &s3c_qos->s3cqos8);
|
||||
|
||||
s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_AXI_BASE;
|
||||
writel(0x00820082, &s3c_qos->s3cqos0);
|
||||
writel(0x00828092, &s3c_qos->s3cqos0);
|
||||
writel(0x20960020, &s3c_qos->s3cqos1);
|
||||
writel(0x20302030, &s3c_qos->s3cqos2);
|
||||
writel(0x20AA20FA, &s3c_qos->s3cqos3);
|
||||
|
@ -1198,7 +1243,7 @@ static void qos_init_es2(void)
|
|||
writel(0x20AA20FA, &s3c_qos->s3cqos7);
|
||||
writel(0x00002032, &s3c_qos->s3cqos8);
|
||||
|
||||
writel(0x00200808, &s3c->s3carcr11);
|
||||
writel(0x00310808, &s3c->s3carcr11);
|
||||
|
||||
/* DBSC -QoS */
|
||||
/* DBSC0 - Read */
|
||||
|
@ -1235,7 +1280,7 @@ static void qos_init_es2(void)
|
|||
/* Transaction Control (MXI) */
|
||||
mxi = (struct rcar_mxi *)MXI_BASE;
|
||||
writel(0x00000013, &mxi->mxrtcr);
|
||||
writel(0x00000013, &mxi->mxwtcr);
|
||||
writel(0x00000016, &mxi->mxwtcr);
|
||||
writel(0x00B800C0, &mxi->mxsaar0);
|
||||
writel(0x02000800, &mxi->mxsaar1);
|
||||
|
||||
|
@ -1622,7 +1667,7 @@ static void qos_init_es2(void)
|
|||
|
||||
/* QoS Register (RT-AXI) */
|
||||
axi_qos = (struct rcar_axi_qos *)RT_AXI_SHX_BASE;
|
||||
writel(0x00000000, &axi_qos->qosconf);
|
||||
writel(0x00000001, &axi_qos->qosconf);
|
||||
writel(0x00002053, &axi_qos->qosctset0);
|
||||
writel(0x00002096, &axi_qos->qosctset1);
|
||||
writel(0x00002030, &axi_qos->qosctset2);
|
||||
|
|
Loading…
Add table
Reference in a new issue