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Merge git://git.denx.de/u-boot-socfpga
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commit
65972a0b62
4 changed files with 31 additions and 6 deletions
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@ -0,0 +1,19 @@
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Altera SOCFPGA Arria10 FPGA Manager
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Required properties:
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- compatible : should contain "altr,socfpga-a10-fpga-mgr"
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- reg : base address and size for memory mapped io.
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- The first index is for FPGA manager register access.
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- The second index is for writing FPGA configuration data.
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- resets : Phandle and reset specifier for the device's reset.
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- clocks : Clocks used by the device.
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Example:
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fpga_mgr: fpga-mgr@ffd03000 {
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compatible = "altr,socfpga-a10-fpga-mgr";
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reg = <0xffd03000 0x100
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0xffcfe400 0x20>;
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clocks = <&l4_mp_clk>;
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resets = <&rst FPGAMGR_RESET>;
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};
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@ -1,5 +1,5 @@
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/*
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* Copyright (C) 2012 Altera Corporation <www.altera.com>
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* Copyright (C) 2012-2017 Altera Corporation <www.altera.com>
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* All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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@ -55,18 +55,20 @@ void fpgamgr_program_write(const void *rbf_data, size_t rbf_size)
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uint32_t loops4 = DIV_ROUND_UP(rbf_size % 32, 4);
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asm volatile(
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" cmp %2, #0\n"
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" beq 2f\n"
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"1: ldmia %0!, {r0-r7}\n"
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" stmia %1!, {r0-r7}\n"
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" sub %1, #32\n"
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" subs %2, #1\n"
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" bne 1b\n"
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" cmp %3, #0\n"
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" beq 3f\n"
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"2: ldr %2, [%0], #4\n"
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"2: cmp %3, #0\n"
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" beq 4f\n"
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"3: ldr %2, [%0], #4\n"
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" str %2, [%1]\n"
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" subs %3, #1\n"
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" bne 2b\n"
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"3: nop\n"
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" bne 3b\n"
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"4: nop\n"
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: "+r"(src), "+r"(dst), "+r"(loops32), "+r"(loops4) :
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: "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "cc");
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}
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@ -159,6 +159,8 @@ enum fdt_compat_id {
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COMPAT_ALTERA_SOCFPGA_F2SDR0, /* SoCFPGA fpga2SDRAM0 bridge */
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COMPAT_ALTERA_SOCFPGA_F2SDR1, /* SoCFPGA fpga2SDRAM1 bridge */
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COMPAT_ALTERA_SOCFPGA_F2SDR2, /* SoCFPGA fpga2SDRAM2 bridge */
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COMPAT_ALTERA_SOCFPGA_FPGA0, /* SOCFPGA FPGA manager */
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COMPAT_ALTERA_SOCFPGA_NOC, /* SOCFPGA Arria 10 NOC */
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COMPAT_COUNT,
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};
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@ -71,6 +71,8 @@ static const char * const compat_names[COMPAT_COUNT] = {
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COMPAT(ALTERA_SOCFPGA_F2SDR0, "altr,socfpga-fpga2sdram0-bridge"),
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COMPAT(ALTERA_SOCFPGA_F2SDR1, "altr,socfpga-fpga2sdram1-bridge"),
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COMPAT(ALTERA_SOCFPGA_F2SDR2, "altr,socfpga-fpga2sdram2-bridge"),
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COMPAT(ALTERA_SOCFPGA_FPGA0, "altr,socfpga-a10-fpga-mgr"),
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COMPAT(ALTERA_SOCFPGA_NOC, "altr,socfpga-a10-noc"),
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};
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const char *fdtdec_get_compatible(enum fdt_compat_id id)
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