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83xx: Use the proper sequence for updating IMMR.

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This ensures that subsequent accesses properly hit the new window.

The dcbi during the NAND loop was accidentally working around this;
it's no longer necessary, as the cache is not enabled.

Reported-by: Suchit Lepcha <Suchit.Lepcha@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
This commit is contained in:
Scott Wood 2009-01-20 11:56:11 -06:00 • committed by Kim Phillips
parent 8b34557c54
commit 6677876181
1 changed files with 15 additions and 3 deletions
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18
cpu/mpc83xx/start.S
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@ -200,9 +200,23 @@ boot_cold: /* time t 3 */
nop
boot_warm: /* time t 5 */
mfmsr r5 /* save msr contents */
/* 83xx manuals prescribe a specific sequence for updating IMMRBAR. */
bl 1f
1: mflr r7
lis r3, CONFIG_SYS_IMMR@h
ori r3, r3, CONFIG_SYS_IMMR@l
lwz r6, IMMRBAR(r4)
isync
stw r3, IMMRBAR(r4)
lwz r6, 0(r7) /* Arbitrary external load */
isync
lwz r6, IMMRBAR(r3)
isync
/* Initialise the E300 processor core */
/*------------------------------------------*/
@ -212,9 +226,7 @@ boot_warm: /* time t 5 */
* is loaded. Wait for the rest before branching
* to another flash page.
*/
addi r7, r3, 0x50b0
1: dcbi 0, r7
lwz r6, 0(r7)
1: lwz r6, 0x50b0(r3)
andi. r6, r6, 1
beq 1b
#endif