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davinci: remove macro CONFIG_DISPLAY_CPUINFO
remove the macro CONFIG_DISPLAY_CPUINFO as it is no longer required. This is because clock info will be printed as part 'bdinfo' command and also remove support print_cpuinfo() as it will no longer be called. Signed-off-by: Manjunath Hadli <manjunath.hadli@ti.com> Cc: Tom Rini <trini@ti.com>
This commit is contained in:
parent
fd3d28e7a6
commit
6678cebc09
11 changed files with 0 additions and 54 deletions
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@ -115,21 +115,8 @@ int clk_get(enum davinci_clk_ids id)
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out:
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out:
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return pll_out;
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return pll_out;
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}
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}
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#ifdef CONFIG_DISPLAY_CPUINFO
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int print_cpuinfo(void)
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{
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printf("Cores: ARM %d MHz",
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clk_get(DAVINCI_ARM_CLKID) / 1000000);
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printf("\nDDR: %d MHz\n",
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/* DDR PHY uses an x2 input clock */
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clk_get(0x10001) / 1000000);
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return 0;
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}
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#endif
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#else /* CONFIG_SOC_DA8XX */
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#else /* CONFIG_SOC_DA8XX */
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#ifdef CONFIG_DISPLAY_CPUINFO
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static unsigned pll_div(volatile void *pllbase, unsigned offset)
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static unsigned pll_div(volatile void *pllbase, unsigned offset)
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{
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{
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u32 div;
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u32 div;
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@ -185,36 +172,6 @@ static unsigned pll_sysclk_mhz(unsigned pll_addr, unsigned div)
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return DIV_ROUND_UP(base, 1000 * pll_div(pllbase, div));
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return DIV_ROUND_UP(base, 1000 * pll_div(pllbase, div));
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}
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}
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int print_cpuinfo(void)
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{
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/* REVISIT fetch and display CPU ID and revision information
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* too ... that will matter as more revisions appear.
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*/
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#if defined(CONFIG_SOC_DM365)
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printf("Cores: ARM %d MHz",
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pll_sysclk_mhz(DAVINCI_PLL_CNTRL1_BASE, ARM_PLLDIV));
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#else
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printf("Cores: ARM %d MHz",
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pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, ARM_PLLDIV));
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#endif
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#ifdef DSP_PLLDIV
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printf(", DSP %d MHz",
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pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, DSP_PLLDIV));
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#endif
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printf("\nDDR: %d MHz\n",
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/* DDR PHY uses an x2 input clock */
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#if defined(CONFIG_SOC_DM365)
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pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, DDR_PLLDIV)
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/ 2);
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#else
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pll_sysclk_mhz(DAVINCI_PLL_CNTRL1_BASE, DDR_PLLDIV)
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/ 2);
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#endif
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return 0;
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}
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#ifdef DAVINCI_DM6467EVM
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#ifdef DAVINCI_DM6467EVM
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unsigned int davinci_arm_clk_get()
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unsigned int davinci_arm_clk_get()
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{
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{
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@ -228,7 +185,6 @@ unsigned int davinci_clk_get(unsigned int div)
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return pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, div) * 1000000;
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return pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, div) * 1000000;
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}
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}
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#endif
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#endif
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#endif /* CONFIG_DISPLAY_CPUINFO */
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#endif /* !CONFIG_SOC_DA8XX */
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#endif /* !CONFIG_SOC_DA8XX */
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/*
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/*
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@ -264,7 +264,6 @@
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#define CONFIG_POST CONFIG_SYS_POST_MEMORY
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#define CONFIG_POST CONFIG_SYS_POST_MEMORY
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#define _POST_WORD_ADDR 0x0
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#define _POST_WORD_ADDR 0x0
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#define CONFIG_DISPLAY_CPUINFO
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#define CONFIG_DISPLAY_BOARDINFO
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#define CONFIG_DISPLAY_BOARDINFO
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#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SPL_STACK
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#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SPL_STACK
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@ -26,7 +26,6 @@
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#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is a 3rd stage loader */
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#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is a 3rd stage loader */
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#define CONFIG_SYS_NO_FLASH /* that is, no *NOR* flash */
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#define CONFIG_SYS_NO_FLASH /* that is, no *NOR* flash */
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#define CONFIG_SYS_CONSOLE_INFO_QUIET
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#define CONFIG_SYS_CONSOLE_INFO_QUIET
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#define CONFIG_DISPLAY_CPUINFO
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/* SoC Configuration */
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/* SoC Configuration */
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#define CONFIG_ARM926EJS /* arm926ejs CPU */
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#define CONFIG_ARM926EJS /* arm926ejs CPU */
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@ -25,7 +25,6 @@
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#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is a 3rd stage loader */
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#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is a 3rd stage loader */
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#define CONFIG_SYS_NO_FLASH /* that is, no *NOR* flash */
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#define CONFIG_SYS_NO_FLASH /* that is, no *NOR* flash */
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#define CONFIG_SYS_CONSOLE_INFO_QUIET
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#define CONFIG_SYS_CONSOLE_INFO_QUIET
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#define CONFIG_DISPLAY_CPUINFO
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/* SoC Configuration */
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/* SoC Configuration */
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#define CONFIG_ARM926EJS /* arm926ejs CPU */
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#define CONFIG_ARM926EJS /* arm926ejs CPU */
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@ -23,7 +23,6 @@
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/* Spectrum Digital TMS320DM6467T EVM board */
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/* Spectrum Digital TMS320DM6467T EVM board */
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#define DAVINCI_DM6467EVM
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#define DAVINCI_DM6467EVM
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#define DAVINCI_DM6467TEVM
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#define DAVINCI_DM6467TEVM
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#define CONFIG_DISPLAY_CPUINFO
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#define CONFIG_SYS_USE_NAND
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#define CONFIG_SYS_USE_NAND
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#define CONFIG_SYS_NAND_SMALLPAGE
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#define CONFIG_SYS_NAND_SMALLPAGE
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@ -22,7 +22,6 @@
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/* Spectrum Digital TMS320DM6467 EVM board */
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/* Spectrum Digital TMS320DM6467 EVM board */
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#define DAVINCI_DM6467EVM
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#define DAVINCI_DM6467EVM
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#define CONFIG_DISPLAY_CPUINFO
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#define CONFIG_SYS_USE_NAND
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#define CONFIG_SYS_USE_NAND
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#define CONFIG_SYS_NAND_SMALLPAGE
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#define CONFIG_SYS_NAND_SMALLPAGE
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@ -51,7 +51,6 @@
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#define DV_EVM
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#define DV_EVM
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#define CONFIG_SYS_NAND_SMALLPAGE
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#define CONFIG_SYS_NAND_SMALLPAGE
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#define CONFIG_SYS_USE_NAND
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#define CONFIG_SYS_USE_NAND
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#define CONFIG_DISPLAY_CPUINFO
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/*===================*/
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/*===================*/
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/* SoC Configuration */
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/* SoC Configuration */
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/*===================*/
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/*===================*/
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@ -26,7 +26,6 @@
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#define SCHMOOGIE
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#define SCHMOOGIE
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#define CONFIG_SYS_NAND_LARGEPAGE
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#define CONFIG_SYS_NAND_LARGEPAGE
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#define CONFIG_SYS_USE_NAND
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#define CONFIG_SYS_USE_NAND
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#define CONFIG_DISPLAY_CPUINFO
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#define MACH_TYPE_SCHMOOGIE 1255
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#define MACH_TYPE_SCHMOOGIE 1255
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#define CONFIG_MACH_TYPE MACH_TYPE_SCHMOOGIE
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#define CONFIG_MACH_TYPE MACH_TYPE_SCHMOOGIE
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@ -28,7 +28,6 @@
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#define CONFIG_SYS_NAND_LARGEPAGE
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#define CONFIG_SYS_NAND_LARGEPAGE
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#define CONFIG_SYS_USE_NAND
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#define CONFIG_SYS_USE_NAND
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#define CONFIG_SYS_USE_DSPLINK /* don't power up the DSP. */
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#define CONFIG_SYS_USE_DSPLINK /* don't power up the DSP. */
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#define CONFIG_DISPLAY_CPUINFO
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/* SoC Configuration */
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/* SoC Configuration */
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#define CONFIG_ARM926EJS /* arm926ejs CPU core */
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#define CONFIG_ARM926EJS /* arm926ejs CPU core */
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#define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */
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#define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */
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@ -51,7 +51,6 @@
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#define SONATA_BOARD
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#define SONATA_BOARD
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#define CONFIG_SYS_NAND_SMALLPAGE
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#define CONFIG_SYS_NAND_SMALLPAGE
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#define CONFIG_SYS_USE_NOR
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#define CONFIG_SYS_USE_NOR
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#define CONFIG_DISPLAY_CPUINFO
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#define MACH_TYPE_SONATA 1254
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#define MACH_TYPE_SONATA 1254
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#define CONFIG_MACH_TYPE MACH_TYPE_SONATA
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#define CONFIG_MACH_TYPE MACH_TYPE_SONATA
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/*===================*/
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/*===================*/
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@ -50,7 +50,6 @@
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#define CONFIG_ARCH_CPU_INIT
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#define CONFIG_ARCH_CPU_INIT
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#define CONFIG_DA8XX_GPIO
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#define CONFIG_DA8XX_GPIO
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#define CONFIG_HOSTNAME enbw_cmc
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#define CONFIG_HOSTNAME enbw_cmc
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#define CONFIG_DISPLAY_CPUINFO
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#define MACH_TYPE_ENBW_CMC 3585
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#define MACH_TYPE_ENBW_CMC 3585
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#define CONFIG_MACH_TYPE MACH_TYPE_ENBW_CMC
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#define CONFIG_MACH_TYPE MACH_TYPE_ENBW_CMC
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