mirror of
https://github.com/Fishwaldo/u-boot.git
synced 2025-03-21 06:31:31 +00:00
Merge branch 'master' of git://git.denx.de/u-boot-spi
This commit is contained in:
commit
66ddf42b0e
19 changed files with 373 additions and 59 deletions
|
@ -17,6 +17,8 @@
|
|||
#define ZYNQ_SDHCI_BASEADDR1 0xE0101000
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||||
#define ZYNQ_I2C_BASEADDR0 0xE0004000
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||||
#define ZYNQ_I2C_BASEADDR1 0xE0005000
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#define ZYNQ_SPI_BASEADDR0 0xE0006000
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#define ZYNQ_SPI_BASEADDR1 0xE0007000
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||||
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/* Reflect slcr offsets */
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struct slcr_regs {
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|
|
|
@ -16,6 +16,7 @@
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#include <stdio_dev.h>
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#include <serial.h>
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#include <net.h>
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#include <spi.h>
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#include <linux/compiler.h>
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#include <asm/processor.h>
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#include <asm/microblaze_intc.h>
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|
@ -147,6 +148,10 @@ void board_init_f(ulong not_used)
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|||
}
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#endif
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#ifdef CONFIG_SPI
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spi_init();
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#endif
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/* relocate environment function pointers etc. */
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env_relocate();
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|
|
|
@ -160,7 +160,8 @@ static const char *spi_flash_update_block(struct spi_flash *flash, u32 offset,
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*skipped += len;
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return NULL;
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}
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if (spi_flash_erase(flash, offset, len))
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/* Erase the entire sector */
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if (spi_flash_erase(flash, offset, flash->sector_size))
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return "erase";
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if (spi_flash_write(flash, offset, len, buf))
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return "write";
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|
@ -262,9 +263,9 @@ static int do_spi_flash_read_write(int argc, char * const argv[])
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return 1;
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}
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if (strcmp(argv[0], "update") == 0)
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if (strcmp(argv[0], "update") == 0) {
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ret = spi_flash_update(flash, offset, len, buf);
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else if (strncmp(argv[0], "read", 4) == 0 ||
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} else if (strncmp(argv[0], "read", 4) == 0 ||
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strncmp(argv[0], "write", 5) == 0) {
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int read;
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|
@ -470,7 +471,8 @@ static int do_spi_flash_test(int argc, char * const argv[])
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}
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#endif /* CONFIG_CMD_SF_TEST */
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static int do_spi_flash(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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static int do_spi_flash(cmd_tbl_t *cmdtp, int flag, int argc,
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char * const argv[])
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{
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const char *cmd;
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int ret;
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|
|
|
@ -54,8 +54,7 @@ struct spi_flash *spi_flash_probe_eon(struct spi_slave *spi, u8 *idcode)
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flash->page_size = 256;
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flash->sector_size = 256 * 16 * 16;
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flash->size = 256 * 16
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* params->nr_sectors;
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flash->size = 256 * 16 * params->nr_sectors;
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return flash;
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}
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|
|
|
@ -230,7 +230,8 @@ struct spi_flash *spi_fram_probe_ramtron(struct spi_slave *spi, u8 *idcode)
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/* JEDEC conformant RAMTRON id */
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for (i = 0; i < ARRAY_SIZE(ramtron_spi_fram_table); i++) {
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params = &ramtron_spi_fram_table[i];
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if (idcode[1] == params->id1 && idcode[2] == params->id2)
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if (idcode[1] == params->id1 &&
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idcode[2] == params->id2)
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goto found;
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}
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break;
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|
@ -251,7 +252,8 @@ struct spi_flash *spi_fram_probe_ramtron(struct spi_slave *spi, u8 *idcode)
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/* now find the device */
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for (i = 0; i < ARRAY_SIZE(ramtron_spi_fram_table); i++) {
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params = &ramtron_spi_fram_table[i];
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if (!strcmp(params->name, CONFIG_SPI_FRAM_RAMTRON_NON_JEDEC))
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if (!strcmp(params->name,
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CONFIG_SPI_FRAM_RAMTRON_NON_JEDEC))
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goto found;
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}
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debug("SF: Unsupported non-JEDEC RAMTRON device "
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|
|
|
@ -122,7 +122,8 @@ struct spi_flash *spi_flash_probe_spansion(struct spi_slave *spi, u8 *idcode)
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}
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if (i == ARRAY_SIZE(spansion_spi_flash_table)) {
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debug("SF: Unsupported SPANSION ID %04x %04x\n", jedec, ext_jedec);
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debug("SF: Unsupported SPANSION ID %04x %04x\n",
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jedec, ext_jedec);
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return NULL;
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}
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|
|
|
@ -42,7 +42,8 @@ static int spi_flash_read_write(struct spi_slave *spi,
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debug("SF: Failed to send command (%zu bytes): %d\n",
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cmd_len, ret);
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} else if (data_len != 0) {
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ret = spi_xfer(spi, data_len * 8, data_out, data_in, SPI_XFER_END);
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ret = spi_xfer(spi, data_len * 8, data_out, data_in,
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SPI_XFER_END);
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if (ret)
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debug("SF: Failed to transfer %zu bytes of data: %d\n",
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data_len, ret);
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|
|
|
@ -39,7 +39,7 @@ void spl_spi_load_image(void)
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|||
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/* Load u-boot, mkimage header is 64 bytes. */
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spi_flash_read(flash, CONFIG_SYS_SPI_U_BOOT_OFFS, 0x40,
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(void *) header);
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(void *)header);
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spl_parse_image_header(header);
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spi_flash_read(flash, CONFIG_SYS_SPI_U_BOOT_OFFS,
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spl_image.size, (void *)spl_image.load_addr);
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|
|
|
@ -19,7 +19,7 @@
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|||
#include "spi_flash_internal.h"
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#define CMD_SST_BP 0x02 /* Byte Program */
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#define CMD_SST_AAI_WP 0xAD /* Auto Address Increment Word Program */
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#define CMD_SST_AAI_WP 0xAD /* Auto Address Incr Word Program */
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#define SST_SR_WIP (1 << 0) /* Write-in-Progress */
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#define SST_SR_WEL (1 << 1) /* Write enable */
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|
@ -50,47 +50,61 @@ static const struct sst_spi_flash_params sst_spi_flash_table[] = {
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.flags = SST_FEAT_WP,
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.nr_sectors = 128,
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.name = "SST25VF040B",
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},{
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},
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{
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.idcode1 = 0x8e,
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.flags = SST_FEAT_WP,
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.nr_sectors = 256,
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.name = "SST25VF080B",
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},{
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},
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{
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.idcode1 = 0x41,
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.flags = SST_FEAT_WP,
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.nr_sectors = 512,
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.name = "SST25VF016B",
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},{
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},
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{
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.idcode1 = 0x4a,
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.flags = SST_FEAT_WP,
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.nr_sectors = 1024,
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.name = "SST25VF032B",
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},{
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},
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{
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.idcode1 = 0x4b,
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.flags = SST_FEAT_MBP,
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.nr_sectors = 2048,
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.name = "SST25VF064C",
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},{
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},
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{
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.idcode1 = 0x01,
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.flags = SST_FEAT_WP,
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.nr_sectors = 16,
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.name = "SST25WF512",
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},{
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},
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{
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.idcode1 = 0x02,
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.flags = SST_FEAT_WP,
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.nr_sectors = 32,
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.name = "SST25WF010",
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},{
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},
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{
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.idcode1 = 0x03,
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.flags = SST_FEAT_WP,
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.nr_sectors = 64,
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.name = "SST25WF020",
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},{
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},
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{
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.idcode1 = 0x04,
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.flags = SST_FEAT_WP,
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.nr_sectors = 128,
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.name = "SST25WF040",
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},
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{
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.idcode1 = 0x05,
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.flags = SST_FEAT_WP,
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.nr_sectors = 256,
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.name = "SST25WF080",
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},
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};
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static int
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|
@ -152,8 +166,8 @@ sst_write_wp(struct spi_flash *flash, u32 offset, size_t len, const void *buf)
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for (; actual < len - 1; actual += 2) {
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debug("WP[%02x]: 0x%p => cmd = { 0x%02x 0x%06x }\n",
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spi_w8r8(flash->spi, CMD_READ_STATUS), buf + actual, cmd[0],
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offset);
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spi_w8r8(flash->spi, CMD_READ_STATUS), buf + actual,
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cmd[0], offset);
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ret = spi_flash_cmd_write(flash->spi, cmd, cmd_len,
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buf + actual, 2);
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|
|
|
@ -150,7 +150,7 @@ static const struct stmicro_spi_flash_params stmicro_spi_flash_table[] = {
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},
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};
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struct spi_flash *spi_flash_probe_stmicro(struct spi_slave *spi, u8 * idcode)
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struct spi_flash *spi_flash_probe_stmicro(struct spi_slave *spi, u8 *idcode)
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{
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const struct stmicro_spi_flash_params *params;
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struct spi_flash *flash;
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|
@ -166,18 +166,18 @@ struct spi_flash *spi_flash_probe_stmicro(struct spi_slave *spi, u8 * idcode)
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idcode[0] = 0x20;
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idcode[1] = 0x20;
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idcode[2] = idcode[3] + 1;
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} else
|
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} else {
|
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return NULL;
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}
|
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}
|
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|
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id = ((idcode[1] << 8) | idcode[2]);
|
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|
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for (i = 0; i < ARRAY_SIZE(stmicro_spi_flash_table); i++) {
|
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params = &stmicro_spi_flash_table[i];
|
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if (params->id == id) {
|
||||
if (params->id == id)
|
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break;
|
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}
|
||||
}
|
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|
||||
if (i == ARRAY_SIZE(stmicro_spi_flash_table)) {
|
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debug("SF: Unsupported STMicro ID %04x\n", id);
|
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|
|
|
@ -39,6 +39,7 @@ COBJS-$(CONFIG_TEGRA20_SFLASH) += tegra20_sflash.o
|
|||
COBJS-$(CONFIG_TEGRA20_SLINK) += tegra20_slink.o
|
||||
COBJS-$(CONFIG_TEGRA114_SPI) += tegra114_spi.o
|
||||
COBJS-$(CONFIG_XILINX_SPI) += xilinx_spi.o
|
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COBJS-$(CONFIG_ZYNQ_SPI) += zynq_spi.o
|
||||
|
||||
COBJS := $(COBJS-y)
|
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SRCS := $(COBJS:.o=.c)
|
||||
|
|
|
@ -221,15 +221,13 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *data_out,
|
|||
slave->bus, slave->cs, *(uint *) dout,
|
||||
dout, *(uint *) din, din, len);
|
||||
|
||||
num_chunks = data_len / max_tran_len +
|
||||
(data_len % max_tran_len ? 1 : 0);
|
||||
num_chunks = DIV_ROUND_UP(data_len, max_tran_len);
|
||||
while (num_chunks--) {
|
||||
if (data_in)
|
||||
din = buffer + rx_offset;
|
||||
dout = buffer;
|
||||
tran_len = min(data_len , max_tran_len);
|
||||
num_blks = (tran_len + cmd_len) / 4 +
|
||||
((tran_len + cmd_len) % 4 ? 1 : 0);
|
||||
num_blks = DIV_ROUND_UP(tran_len + cmd_len, 4);
|
||||
num_bytes = (tran_len + cmd_len) % 4;
|
||||
fsl->data_len = tran_len + cmd_len;
|
||||
spi_cs_activate(slave);
|
||||
|
|
|
@ -77,7 +77,7 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
|
|||
{
|
||||
volatile spi8xxx_t *spi = &((immap_t *) (CONFIG_SYS_IMMR))->spi;
|
||||
unsigned int tmpdout, tmpdin, event;
|
||||
int numBlks = bitlen / 32 + (bitlen % 32 ? 1 : 0);
|
||||
int numBlks = DIV_ROUND_UP(bitlen, 32);
|
||||
int tm, isRead = 0;
|
||||
unsigned char charSize = 32;
|
||||
|
||||
|
|
280
drivers/spi/zynq_spi.c
Normal file
280
drivers/spi/zynq_spi.c
Normal file
|
@ -0,0 +1,280 @@
|
|||
/*
|
||||
* (C) Copyright 2013 Inc.
|
||||
*
|
||||
* Xilinx Zynq PS SPI controller driver (master mode only)
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <config.h>
|
||||
#include <common.h>
|
||||
#include <malloc.h>
|
||||
#include <spi.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/hardware.h>
|
||||
|
||||
/* zynq spi register bit masks ZYNQ_SPI_<REG>_<BIT>_MASK */
|
||||
#define ZYNQ_SPI_CR_MSA_MASK (1 << 15) /* Manual start enb */
|
||||
#define ZYNQ_SPI_CR_MCS_MASK (1 << 14) /* Manual chip select */
|
||||
#define ZYNQ_SPI_CR_CS_MASK (0xF << 10) /* Chip select */
|
||||
#define ZYNQ_SPI_CR_BRD_MASK (0x7 << 3) /* Baud rate div */
|
||||
#define ZYNQ_SPI_CR_CPHA_MASK (1 << 2) /* Clock phase */
|
||||
#define ZYNQ_SPI_CR_CPOL_MASK (1 << 1) /* Clock polarity */
|
||||
#define ZYNQ_SPI_CR_MSTREN_MASK (1 << 0) /* Mode select */
|
||||
#define ZYNQ_SPI_IXR_RXNEMPTY_MASK (1 << 4) /* RX_FIFO_not_empty */
|
||||
#define ZYNQ_SPI_IXR_TXOW_MASK (1 << 2) /* TX_FIFO_not_full */
|
||||
#define ZYNQ_SPI_IXR_ALL_MASK 0x7F /* All IXR bits */
|
||||
#define ZYNQ_SPI_ENR_SPI_EN_MASK (1 << 0) /* SPI Enable */
|
||||
|
||||
#define ZYNQ_SPI_FIFO_DEPTH 128
|
||||
#ifndef CONFIG_SYS_ZYNQ_SPI_WAIT
|
||||
#define CONFIG_SYS_ZYNQ_SPI_WAIT (CONFIG_SYS_HZ/100) /* 10 ms */
|
||||
#endif
|
||||
|
||||
/* zynq spi register set */
|
||||
struct zynq_spi_regs {
|
||||
u32 cr; /* 0x00 */
|
||||
u32 isr; /* 0x04 */
|
||||
u32 ier; /* 0x08 */
|
||||
u32 idr; /* 0x0C */
|
||||
u32 imr; /* 0x10 */
|
||||
u32 enr; /* 0x14 */
|
||||
u32 dr; /* 0x18 */
|
||||
u32 txdr; /* 0x1C */
|
||||
u32 rxdr; /* 0x20 */
|
||||
};
|
||||
|
||||
/* zynq spi slave */
|
||||
struct zynq_spi_slave {
|
||||
struct spi_slave slave;
|
||||
struct zynq_spi_regs *base;
|
||||
u8 mode;
|
||||
u8 fifo_depth;
|
||||
u32 speed_hz;
|
||||
u32 input_hz;
|
||||
u32 req_hz;
|
||||
};
|
||||
|
||||
static inline struct zynq_spi_slave *to_zynq_spi_slave(struct spi_slave *slave)
|
||||
{
|
||||
return container_of(slave, struct zynq_spi_slave, slave);
|
||||
}
|
||||
|
||||
static inline struct zynq_spi_regs *get_zynq_spi_base(int dev)
|
||||
{
|
||||
if (dev)
|
||||
return (struct zynq_spi_regs *)ZYNQ_SPI_BASEADDR1;
|
||||
else
|
||||
return (struct zynq_spi_regs *)ZYNQ_SPI_BASEADDR0;
|
||||
}
|
||||
|
||||
static void zynq_spi_init_hw(struct zynq_spi_slave *zslave)
|
||||
{
|
||||
u32 confr;
|
||||
|
||||
/* Disable SPI */
|
||||
writel(~ZYNQ_SPI_ENR_SPI_EN_MASK, &zslave->base->enr);
|
||||
|
||||
/* Disable Interrupts */
|
||||
writel(ZYNQ_SPI_IXR_ALL_MASK, &zslave->base->idr);
|
||||
|
||||
/* Clear RX FIFO */
|
||||
while (readl(&zslave->base->isr) &
|
||||
ZYNQ_SPI_IXR_RXNEMPTY_MASK)
|
||||
readl(&zslave->base->rxdr);
|
||||
|
||||
/* Clear Interrupts */
|
||||
writel(ZYNQ_SPI_IXR_ALL_MASK, &zslave->base->isr);
|
||||
|
||||
/* Manual slave select and Auto start */
|
||||
confr = ZYNQ_SPI_CR_MCS_MASK | ZYNQ_SPI_CR_CS_MASK |
|
||||
ZYNQ_SPI_CR_MSTREN_MASK;
|
||||
confr &= ~ZYNQ_SPI_CR_MSA_MASK;
|
||||
writel(confr, &zslave->base->cr);
|
||||
|
||||
/* Enable SPI */
|
||||
writel(ZYNQ_SPI_ENR_SPI_EN_MASK, &zslave->base->enr);
|
||||
}
|
||||
|
||||
int spi_cs_is_valid(unsigned int bus, unsigned int cs)
|
||||
{
|
||||
/* 2 bus with 3 chipselect */
|
||||
return bus < 2 && cs < 3;
|
||||
}
|
||||
|
||||
void spi_cs_activate(struct spi_slave *slave)
|
||||
{
|
||||
struct zynq_spi_slave *zslave = to_zynq_spi_slave(slave);
|
||||
u32 cr;
|
||||
|
||||
debug("spi_cs_activate: 0x%08x\n", (u32)slave);
|
||||
|
||||
clrbits_le32(&zslave->base->cr, ZYNQ_SPI_CR_CS_MASK);
|
||||
cr = readl(&zslave->base->cr);
|
||||
/*
|
||||
* CS cal logic: CS[13:10]
|
||||
* xxx0 - cs0
|
||||
* xx01 - cs1
|
||||
* x011 - cs2
|
||||
*/
|
||||
cr |= (~(0x1 << slave->cs) << 10) & ZYNQ_SPI_CR_CS_MASK;
|
||||
writel(cr, &zslave->base->cr);
|
||||
}
|
||||
|
||||
void spi_cs_deactivate(struct spi_slave *slave)
|
||||
{
|
||||
struct zynq_spi_slave *zslave = to_zynq_spi_slave(slave);
|
||||
|
||||
debug("spi_cs_deactivate: 0x%08x\n", (u32)slave);
|
||||
|
||||
setbits_le32(&zslave->base->cr, ZYNQ_SPI_CR_CS_MASK);
|
||||
}
|
||||
|
||||
void spi_init()
|
||||
{
|
||||
/* nothing to do */
|
||||
}
|
||||
|
||||
struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
|
||||
unsigned int max_hz, unsigned int mode)
|
||||
{
|
||||
struct zynq_spi_slave *zslave;
|
||||
|
||||
if (!spi_cs_is_valid(bus, cs))
|
||||
return NULL;
|
||||
|
||||
zslave = spi_alloc_slave(struct zynq_spi_slave, bus, cs);
|
||||
if (!zslave) {
|
||||
printf("SPI_error: Fail to allocate zynq_spi_slave\n");
|
||||
return NULL;
|
||||
}
|
||||
|
||||
zslave->base = get_zynq_spi_base(bus);
|
||||
zslave->mode = mode;
|
||||
zslave->fifo_depth = ZYNQ_SPI_FIFO_DEPTH;
|
||||
zslave->input_hz = 166666700;
|
||||
zslave->speed_hz = zslave->input_hz / 2;
|
||||
zslave->req_hz = max_hz;
|
||||
|
||||
/* init the zynq spi hw */
|
||||
zynq_spi_init_hw(zslave);
|
||||
|
||||
return &zslave->slave;
|
||||
}
|
||||
|
||||
void spi_free_slave(struct spi_slave *slave)
|
||||
{
|
||||
struct zynq_spi_slave *zslave = to_zynq_spi_slave(slave);
|
||||
|
||||
debug("spi_free_slave: 0x%08x\n", (u32)slave);
|
||||
free(zslave);
|
||||
}
|
||||
|
||||
int spi_claim_bus(struct spi_slave *slave)
|
||||
{
|
||||
struct zynq_spi_slave *zslave = to_zynq_spi_slave(slave);
|
||||
u32 confr = 0;
|
||||
u8 baud_rate_val = 0;
|
||||
|
||||
writel(~ZYNQ_SPI_ENR_SPI_EN_MASK, &zslave->base->enr);
|
||||
|
||||
/* Set the SPI Clock phase and polarities */
|
||||
confr = readl(&zslave->base->cr);
|
||||
confr &= ~(ZYNQ_SPI_CR_CPHA_MASK | ZYNQ_SPI_CR_CPOL_MASK);
|
||||
if (zslave->mode & SPI_CPHA)
|
||||
confr |= ZYNQ_SPI_CR_CPHA_MASK;
|
||||
if (zslave->mode & SPI_CPOL)
|
||||
confr |= ZYNQ_SPI_CR_CPOL_MASK;
|
||||
|
||||
/* Set the clock frequency */
|
||||
if (zslave->req_hz == 0) {
|
||||
/* Set baudrate x8, if the req_hz is 0 */
|
||||
baud_rate_val = 0x2;
|
||||
} else if (zslave->speed_hz != zslave->req_hz) {
|
||||
while ((baud_rate_val < 8) &&
|
||||
((zslave->input_hz /
|
||||
(2 << baud_rate_val)) > zslave->req_hz))
|
||||
baud_rate_val++;
|
||||
zslave->speed_hz = zslave->req_hz / (2 << baud_rate_val);
|
||||
}
|
||||
confr &= ~ZYNQ_SPI_CR_BRD_MASK;
|
||||
confr |= (baud_rate_val << 3);
|
||||
writel(confr, &zslave->base->cr);
|
||||
|
||||
writel(ZYNQ_SPI_ENR_SPI_EN_MASK, &zslave->base->enr);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void spi_release_bus(struct spi_slave *slave)
|
||||
{
|
||||
struct zynq_spi_slave *zslave = to_zynq_spi_slave(slave);
|
||||
|
||||
debug("spi_release_bus: 0x%08x\n", (u32)slave);
|
||||
writel(~ZYNQ_SPI_ENR_SPI_EN_MASK, &zslave->base->enr);
|
||||
}
|
||||
|
||||
int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
|
||||
void *din, unsigned long flags)
|
||||
{
|
||||
struct zynq_spi_slave *zslave = to_zynq_spi_slave(slave);
|
||||
u32 len = bitlen / 8;
|
||||
u32 tx_len = len, rx_len = len, tx_tvl;
|
||||
const u8 *tx_buf = dout;
|
||||
u8 *rx_buf = din, buf;
|
||||
u32 ts, status;
|
||||
|
||||
debug("spi_xfer: bus:%i cs:%i bitlen:%i len:%i flags:%lx\n",
|
||||
slave->bus, slave->cs, bitlen, len, flags);
|
||||
|
||||
if (bitlen == 0)
|
||||
return -1;
|
||||
|
||||
if (bitlen % 8) {
|
||||
debug("spi_xfer: Non byte aligned SPI transfer\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
if (flags & SPI_XFER_BEGIN)
|
||||
spi_cs_activate(slave);
|
||||
|
||||
while (rx_len > 0) {
|
||||
/* Write the data into TX FIFO - tx threshold is fifo_depth */
|
||||
tx_tvl = 0;
|
||||
while ((tx_tvl < zslave->fifo_depth) && tx_len) {
|
||||
if (tx_buf)
|
||||
buf = *tx_buf++;
|
||||
else
|
||||
buf = 0;
|
||||
writel(buf, &zslave->base->txdr);
|
||||
tx_len--;
|
||||
tx_tvl++;
|
||||
}
|
||||
|
||||
/* Check TX FIFO completion */
|
||||
ts = get_timer(0);
|
||||
status = readl(&zslave->base->isr);
|
||||
while (!(status & ZYNQ_SPI_IXR_TXOW_MASK)) {
|
||||
if (get_timer(ts) > CONFIG_SYS_ZYNQ_SPI_WAIT) {
|
||||
printf("spi_xfer: Timeout! TX FIFO not full\n");
|
||||
return -1;
|
||||
}
|
||||
status = readl(&zslave->base->isr);
|
||||
}
|
||||
|
||||
/* Read the data from RX FIFO */
|
||||
status = readl(&zslave->base->isr);
|
||||
while (status & ZYNQ_SPI_IXR_RXNEMPTY_MASK) {
|
||||
buf = readl(&zslave->base->rxdr);
|
||||
if (rx_buf)
|
||||
*rx_buf++ = buf;
|
||||
status = readl(&zslave->base->isr);
|
||||
rx_len--;
|
||||
}
|
||||
}
|
||||
|
||||
if (flags & SPI_XFER_END)
|
||||
spi_cs_deactivate(slave);
|
||||
|
||||
return 0;
|
||||
}
|
|
@ -72,6 +72,15 @@
|
|||
# define CONFIG_CPU_V6 /* Required by CONFIG_ARM_DCC */
|
||||
#endif
|
||||
|
||||
#define CONFIG_ZYNQ_SPI
|
||||
|
||||
/* SPI */
|
||||
#ifdef CONFIG_ZYNQ_SPI
|
||||
# define CONFIG_SPI_FLASH
|
||||
# define CONFIG_SPI_FLASH_SST
|
||||
# define CONFIG_CMD_SF
|
||||
#endif
|
||||
|
||||
/* Enable the PL to be downloaded */
|
||||
#define CONFIG_FPGA
|
||||
#define CONFIG_FPGA_XILINX
|
||||
|
|
Loading…
Add table
Reference in a new issue