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arm: Support cache invalidate
At present there is not operation to invalidate a cache range. This seems to be needed to fill out the cache operations. Add an implementation based on the flush operation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <york.sun@nxp.com>
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3 changed files with 40 additions and 1 deletions
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@ -138,6 +138,30 @@ ENTRY(__asm_flush_dcache_range)
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dsb sy
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ret
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ENDPROC(__asm_flush_dcache_range)
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/*
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* void __asm_invalidate_dcache_range(start, end)
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*
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* invalidate data cache in the range
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*
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* x0: start address
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* x1: end address
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*/
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ENTRY(__asm_invalidate_dcache_range)
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mrs x3, ctr_el0
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ubfm x3, x3, #16, #19
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mov x2, #4
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lsl x2, x2, x3 /* cache line size */
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/* x2 <- minimal cache line size in cache system */
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sub x3, x2, #1
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bic x0, x0, x3
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1: dc ivac, x0 /* invalidate data or unified cache */
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add x0, x0, x2
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cmp x0, x1
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b.lo 1b
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dsb sy
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ret
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ENDPROC(__asm_invalidate_dcache_range)
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/*
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* void __asm_invalidate_icache_all(void)
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@ -446,7 +446,7 @@ inline void flush_dcache_all(void)
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*/
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void invalidate_dcache_range(unsigned long start, unsigned long stop)
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{
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__asm_flush_dcache_range(start, stop);
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__asm_invalidate_dcache_range(start, stop);
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}
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/*
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@ -180,6 +180,21 @@ static inline unsigned long read_mpidr(void)
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void __asm_flush_dcache_all(void);
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void __asm_invalidate_dcache_all(void);
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void __asm_flush_dcache_range(u64 start, u64 end);
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/**
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* __asm_invalidate_dcache_range() - Invalidate a range of virtual addresses
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*
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* This performance an invalidate from @start to @end - 1. Both addresses
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* should be cache-aligned, otherwise this function will align the start
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* address and may continue past the end address.
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*
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* Data in the address range is evicted from the cache and is not written back
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* to memory.
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*
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* @start: Start address to invalidate
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* @end: End address to invalidate up to (exclusive)
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*/
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void __asm_invalidate_dcache_range(u64 start, u64 end);
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void __asm_invalidate_tlb_all(void);
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void __asm_invalidate_icache_all(void);
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int __asm_invalidate_l3_dcache(void);
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