mirror of
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i2c, omap24xx: convert driver to new mutlibus/mutliadapter framework
- add omap24xx driver to new multibus/multiadpater support - adapted all config files, which uses this driver Tested on the am335x based siemens boards rut, dxr2 and pxm2 posted here: http://patchwork.ozlabs.org/patch/263211/ Signed-off-by: Heiko Schocher <hs@denx.de> Tested-by: Tom Rini <trini@ti.com> Cc: Lars Poeschel <poeschel@lemonage.de> Cc: Steve Sakoman <sakoman@gmail.com> Cc: Thomas Weber <weber@corscience.de> Cc: Tom Rix <Tom.Rix@windriver.com> Cc: Grazvydas Ignotas <notasas@gmail.com> Cc: Enric Balletbo i Serra <eballetbo@iseebcn.com> Cc: Luca Ceresoli <luca.ceresoli@comelit.it> Cc: Igor Grinberg <grinberg@compulab.co.il> Cc: Ilya Yanok <yanok@emcraft.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Nishanth Menon <nm@ti.com> Cc: Pali Rohár <pali.rohar@gmail.com> Cc: Peter Barada <peter.barada@logicpd.com> Cc: Nagendra T S <nagendra@mistralsolutions.com> Cc: Michael Jones <michael.jones@matrix-vision.de> Cc: Raphael Assenat <raph@8d.com> Acked-by: Igor Grinberg <grinberg@compulab.co.il> Acked-by: Stefano Babic <sbabic@denx.de>
This commit is contained in:
parent
124913556c
commit
6789e84eca
41 changed files with 241 additions and 190 deletions
13
README
13
README
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@ -2058,6 +2058,19 @@ CBFS (Coreboot Filesystem) support
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- CONFIG_SYS_I2C_SH_SPEED5 for for the speed channel 5
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- CONFIG_SYS_I2C_SH_SPEED5 for for the speed channel 5
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- CONFIF_SYS_I2C_SH_NUM_CONTROLLERS for nummber of i2c buses
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- CONFIF_SYS_I2C_SH_NUM_CONTROLLERS for nummber of i2c buses
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- drivers/i2c/omap24xx_i2c.c
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- activate this driver with CONFIG_SYS_I2C_OMAP24XX
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- CONFIG_SYS_OMAP24_I2C_SPEED speed channel 0
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- CONFIG_SYS_OMAP24_I2C_SLAVE slave addr channel 0
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- CONFIG_SYS_OMAP24_I2C_SPEED1 speed channel 1
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- CONFIG_SYS_OMAP24_I2C_SLAVE1 slave addr channel 1
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- CONFIG_SYS_OMAP24_I2C_SPEED2 speed channel 2
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- CONFIG_SYS_OMAP24_I2C_SLAVE2 slave addr channel 2
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- CONFIG_SYS_OMAP24_I2C_SPEED3 speed channel 3
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- CONFIG_SYS_OMAP24_I2C_SLAVE3 slave addr channel 3
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- CONFIG_SYS_OMAP24_I2C_SPEED4 speed channel 4
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- CONFIG_SYS_OMAP24_I2C_SLAVE4 slave addr channel 4
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additional defines:
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additional defines:
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CONFIG_SYS_NUM_I2C_BUSES
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CONFIG_SYS_NUM_I2C_BUSES
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@ -779,7 +779,8 @@ void gpi2c_init(void)
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static int gpi2c = 1;
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static int gpi2c = 1;
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if (gpi2c) {
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if (gpi2c) {
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i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
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i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED,
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CONFIG_SYS_OMAP24_I2C_SLAVE);
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gpi2c = 0;
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gpi2c = 0;
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}
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}
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}
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}
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@ -32,6 +32,10 @@ SECTIONS
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. = ALIGN(4);
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. = ALIGN(4);
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.data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
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.data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
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. = ALIGN(4);
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.u_boot_list : {
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KEEP(*(SORT(.u_boot_list*)));
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} >.sram
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. = ALIGN(4);
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. = ALIGN(4);
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__image_copy_end = .;
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__image_copy_end = .;
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_end = .;
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_end = .;
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@ -98,7 +98,7 @@ void spl_board_init(void)
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gpmc_init();
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gpmc_init();
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#endif
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#endif
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#ifdef CONFIG_SPL_I2C_SUPPORT
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#ifdef CONFIG_SPL_I2C_SUPPORT
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i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
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i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
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#endif
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#endif
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}
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}
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#endif /* CONFIG_SPL_BUILD */
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#endif /* CONFIG_SPL_BUILD */
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@ -708,7 +708,7 @@ void per_clocks_enable(void)
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sr32(&prcm_base->iclken_per, 17, 1, 1);
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sr32(&prcm_base->iclken_per, 17, 1, 1);
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#endif
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#endif
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#ifdef CONFIG_DRIVER_OMAP34XX_I2C
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#ifdef CONFIG_SYS_I2C_OMAP34XX
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/* Turn on all 3 I2C clocks */
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/* Turn on all 3 I2C clocks */
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sr32(&prcm_base->fclken1_core, 15, 3, 0x7);
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sr32(&prcm_base->fclken1_core, 15, 3, 0x7);
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sr32(&prcm_base->iclken1_core, 15, 3, 0x7); /* I2C1,2,3 = on */
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sr32(&prcm_base->iclken1_core, 15, 3, 0x7); /* I2C1,2,3 = on */
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@ -4,8 +4,8 @@
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*
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*
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* SPDX-License-Identifier: GPL-2.0+
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* SPDX-License-Identifier: GPL-2.0+
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*/
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*/
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#ifndef _I2C_H_
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#ifndef _I2C_AM33XX_H_
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#define _I2C_H_
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#define _I2C_AM33XX_H_
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#define I2C_BASE1 0x44E0B000
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#define I2C_BASE1 0x44E0B000
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#define I2C_BASE2 0x4802A000
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#define I2C_BASE2 0x4802A000
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@ -62,4 +62,4 @@ struct i2c {
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#define I2C_IP_CLK 48000000
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#define I2C_IP_CLK 48000000
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#define I2C_INTERNAL_SAMPLING_CLK 12000000
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#define I2C_INTERNAL_SAMPLING_CLK 12000000
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#endif /* _I2C_H_ */
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#endif /* _I2C_AM33XX_H_ */
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@ -482,7 +482,7 @@ static void setup_net_chip_gmpc(void)
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&ctrl_base->gpmc_nadv_ale);
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&ctrl_base->gpmc_nadv_ale);
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}
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}
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#ifdef CONFIG_DRIVER_OMAP34XX_I2C
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#ifdef CONFIG_SYS_I2C_OMAP34XX
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/*
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/*
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* Routine: reset_net_chip
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* Routine: reset_net_chip
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* Description: reset the Ethernet controller via TPS65930 GPIO
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* Description: reset the Ethernet controller via TPS65930 GPIO
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@ -6,5 +6,5 @@
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# SPDX-License-Identifier: GPL-2.0+
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# SPDX-License-Identifier: GPL-2.0+
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#
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#
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obj-$(CONFIG_DRIVER_OMAP34XX_I2C) += eeprom.o
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obj-$(CONFIG_SYS_I2C_OMAP34XX) += eeprom.o
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obj-$(CONFIG_LCD) += omap3_display.o
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obj-$(CONFIG_LCD) += omap3_display.o
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@ -10,7 +10,7 @@
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#ifndef _EEPROM_
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#ifndef _EEPROM_
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#define _EEPROM_
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#define _EEPROM_
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#ifdef CONFIG_DRIVER_OMAP34XX_I2C
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#ifdef CONFIG_SYS_I2C_OMAP34XX
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int cl_eeprom_read_mac_addr(uchar *buf);
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int cl_eeprom_read_mac_addr(uchar *buf);
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u32 cl_eeprom_get_board_rev(void);
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u32 cl_eeprom_get_board_rev(void);
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#else
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#else
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@ -98,8 +98,8 @@ static void am3517_evm_musb_init(void)
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*/
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*/
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int misc_init_r(void)
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int misc_init_r(void)
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{
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{
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#ifdef CONFIG_DRIVER_OMAP34XX_I2C
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#ifdef CONFIG_SYS_I2C_OMAP34XX
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i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
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i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
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#endif
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#endif
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dieid_num_r();
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dieid_num_r();
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@ -92,7 +92,7 @@ int get_board_revision(void)
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{
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{
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int revision;
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int revision;
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#ifdef CONFIG_DRIVER_OMAP34XX_I2C
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#ifdef CONFIG_SYS_I2C_OMAP34XX
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unsigned char data;
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unsigned char data;
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/* board revisions <= R2410 connect 4030 irq_1 to gpio112 */
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/* board revisions <= R2410 connect 4030 irq_1 to gpio112 */
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@ -91,7 +91,7 @@ void set_mux_conf_regs(void)
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{
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{
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/* Initalize the board header */
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/* Initalize the board header */
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enable_i2c0_pin_mux();
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enable_i2c0_pin_mux();
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i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
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i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
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enable_board_pin_mux();
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enable_board_pin_mux();
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}
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}
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@ -108,7 +108,7 @@ void sdram_init(void)
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*/
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*/
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int board_init(void)
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int board_init(void)
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{
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{
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i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
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i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
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gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
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gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
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{
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{
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/* Initalize the board header */
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/* Initalize the board header */
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enable_i2c0_pin_mux();
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enable_i2c0_pin_mux();
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i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
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i2c_set_bus_num(0);
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if (read_eeprom() < 0)
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if (read_eeprom() < 0)
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puts("Could not get board ID.\n");
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puts("Could not get board ID.\n");
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@ -67,7 +67,7 @@ int board_init(void)
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#if defined(CONFIG_HW_WATCHDOG)
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#if defined(CONFIG_HW_WATCHDOG)
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hw_watchdog_init();
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hw_watchdog_init();
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#endif /* defined(CONFIG_HW_WATCHDOG) */
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#endif /* defined(CONFIG_HW_WATCHDOG) */
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i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
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i2c_set_bus_num(0);
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if (read_eeprom() < 0)
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if (read_eeprom() < 0)
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puts("Could not get board ID.\n");
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puts("Could not get board ID.\n");
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@ -397,7 +397,7 @@ const struct dpll_params *get_dpll_ddr_params(void)
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struct am335x_baseboard_id header;
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struct am335x_baseboard_id header;
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enable_i2c0_pin_mux();
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enable_i2c0_pin_mux();
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i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
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i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
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if (read_eeprom(&header) < 0)
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if (read_eeprom(&header) < 0)
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puts("Could not get board ID.\n");
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puts("Could not get board ID.\n");
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*/
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*/
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int misc_init_r(void)
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int misc_init_r(void)
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{
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{
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#ifdef CONFIG_DRIVER_OMAP34XX_I2C
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#ifdef CONFIG_SYS_I2C_OMAP34XX
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i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
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i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
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#endif
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#endif
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dieid_num_r();
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dieid_num_r();
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@ -146,8 +146,8 @@ void get_board_mem_timings(struct board_sdrc_timings *timings)
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int misc_init_r(void)
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int misc_init_r(void)
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{
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{
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#ifdef CONFIG_DRIVER_OMAP34XX_I2C
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#ifdef CONFIG_SYS_I2C_OMAP34XX
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i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
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i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
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#endif
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#endif
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#if defined(CONFIG_CMD_NET)
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#if defined(CONFIG_CMD_NET)
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@ -12,8 +12,6 @@ obj-$(CONFIG_I2C_MVTWSI) += mvtwsi.o
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obj-$(CONFIG_I2C_MV) += mv_i2c.o
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obj-$(CONFIG_I2C_MV) += mv_i2c.o
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obj-$(CONFIG_I2C_MXS) += mxs_i2c.o
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obj-$(CONFIG_I2C_MXS) += mxs_i2c.o
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obj-$(CONFIG_DRIVER_OMAP1510_I2C) += omap1510_i2c.o
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obj-$(CONFIG_DRIVER_OMAP1510_I2C) += omap1510_i2c.o
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obj-$(CONFIG_DRIVER_OMAP24XX_I2C) += omap24xx_i2c.o
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obj-$(CONFIG_DRIVER_OMAP34XX_I2C) += omap24xx_i2c.o
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obj-$(CONFIG_PCA9564_I2C) += pca9564_i2c.o
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obj-$(CONFIG_PCA9564_I2C) += pca9564_i2c.o
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obj-$(CONFIG_DRIVER_S3C24X0_I2C) += s3c24x0_i2c.o
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obj-$(CONFIG_DRIVER_S3C24X0_I2C) += s3c24x0_i2c.o
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obj-$(CONFIG_TSI108_I2C) += tsi108_i2c.o
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obj-$(CONFIG_TSI108_I2C) += tsi108_i2c.o
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@ -23,6 +21,8 @@ obj-$(CONFIG_SYS_I2C) += i2c_core.o
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obj-$(CONFIG_SYS_I2C_FSL) += fsl_i2c.o
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obj-$(CONFIG_SYS_I2C_FSL) += fsl_i2c.o
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obj-$(CONFIG_SYS_I2C_FTI2C010) += fti2c010.o
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obj-$(CONFIG_SYS_I2C_FTI2C010) += fti2c010.o
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obj-$(CONFIG_SYS_I2C_MXC) += mxc_i2c.o
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obj-$(CONFIG_SYS_I2C_MXC) += mxc_i2c.o
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obj-$(CONFIG_SYS_I2C_OMAP24XX) += omap24xx_i2c.o
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obj-$(CONFIG_SYS_I2C_OMAP34XX) += omap24xx_i2c.o
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obj-$(CONFIG_SYS_I2C_PPC4XX) += ppc4xx_i2c.o
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obj-$(CONFIG_SYS_I2C_PPC4XX) += ppc4xx_i2c.o
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obj-$(CONFIG_SYS_I2C_RCAR) += rcar_i2c.o
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obj-$(CONFIG_SYS_I2C_RCAR) += rcar_i2c.o
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obj-$(CONFIG_SYS_I2C_SH) += sh_i2c.o
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obj-$(CONFIG_SYS_I2C_SH) += sh_i2c.o
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*/
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*/
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#include <common.h>
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#include <common.h>
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#include <i2c.h>
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#include <asm/arch/i2c.h>
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#include <asm/arch/i2c.h>
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#include <asm/io.h>
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#include <asm/io.h>
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/* Absolutely safe for status update at 100 kHz I2C: */
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/* Absolutely safe for status update at 100 kHz I2C: */
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#define I2C_WAIT 200
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#define I2C_WAIT 200
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static int wait_for_bb(void);
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static int wait_for_bb(struct i2c_adapter *adap);
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static u16 wait_for_event(void);
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static struct i2c *omap24_get_base(struct i2c_adapter *adap);
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static void flush_fifo(void);
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static u16 wait_for_event(struct i2c_adapter *adap);
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static void flush_fifo(struct i2c_adapter *adap);
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/*
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static void omap24_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
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* For SPL boot some boards need i2c before SDRAM is initialised so force
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* variables to live in SRAM
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*/
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static struct i2c __attribute__((section (".data"))) *i2c_base =
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(struct i2c *)I2C_DEFAULT_BASE;
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static unsigned int __attribute__((section (".data"))) bus_initialized[I2C_BUS_MAX] =
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{ [0 ... (I2C_BUS_MAX-1)] = 0 };
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static unsigned int __attribute__((section (".data"))) current_bus = 0;
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void i2c_init(int speed, int slaveadd)
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{
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{
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struct i2c *i2c_base = omap24_get_base(adap);
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int psc, fsscll, fssclh;
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int psc, fsscll, fssclh;
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int hsscll = 0, hssclh = 0;
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int hsscll = 0, hssclh = 0;
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u32 scll, sclh;
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u32 scll, sclh;
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@ -163,16 +156,15 @@ void i2c_init(int speed, int slaveadd)
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I2C_IE_NACK_IE | I2C_IE_AL_IE, &i2c_base->ie);
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I2C_IE_NACK_IE | I2C_IE_AL_IE, &i2c_base->ie);
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#endif
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#endif
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udelay(1000);
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udelay(1000);
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flush_fifo();
|
flush_fifo(adap);
|
||||||
writew(0xFFFF, &i2c_base->stat);
|
writew(0xFFFF, &i2c_base->stat);
|
||||||
writew(0, &i2c_base->cnt);
|
writew(0, &i2c_base->cnt);
|
||||||
|
|
||||||
if (gd->flags & GD_FLG_RELOC)
|
|
||||||
bus_initialized[current_bus] = 1;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
static void flush_fifo(void)
|
static void flush_fifo(struct i2c_adapter *adap)
|
||||||
{ u16 stat;
|
{
|
||||||
|
struct i2c *i2c_base = omap24_get_base(adap);
|
||||||
|
u16 stat;
|
||||||
|
|
||||||
/* note: if you try and read data when its not there or ready
|
/* note: if you try and read data when its not there or ready
|
||||||
* you get a bus error
|
* you get a bus error
|
||||||
|
@ -192,8 +184,9 @@ static void flush_fifo(void)
|
||||||
* i2c_probe: Use write access. Allows to identify addresses that are
|
* i2c_probe: Use write access. Allows to identify addresses that are
|
||||||
* write-only (like the config register of dual-port EEPROMs)
|
* write-only (like the config register of dual-port EEPROMs)
|
||||||
*/
|
*/
|
||||||
int i2c_probe(uchar chip)
|
static int omap24_i2c_probe(struct i2c_adapter *adap, uchar chip)
|
||||||
{
|
{
|
||||||
|
struct i2c *i2c_base = omap24_get_base(adap);
|
||||||
u16 status;
|
u16 status;
|
||||||
int res = 1; /* default = fail */
|
int res = 1; /* default = fail */
|
||||||
|
|
||||||
|
@ -201,7 +194,7 @@ int i2c_probe(uchar chip)
|
||||||
return res;
|
return res;
|
||||||
|
|
||||||
/* Wait until bus is free */
|
/* Wait until bus is free */
|
||||||
if (wait_for_bb())
|
if (wait_for_bb(adap))
|
||||||
return res;
|
return res;
|
||||||
|
|
||||||
/* No data transfer, slave addr only */
|
/* No data transfer, slave addr only */
|
||||||
|
@ -212,7 +205,7 @@ int i2c_probe(uchar chip)
|
||||||
writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX |
|
writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX |
|
||||||
I2C_CON_STP, &i2c_base->con);
|
I2C_CON_STP, &i2c_base->con);
|
||||||
|
|
||||||
status = wait_for_event();
|
status = wait_for_event(adap);
|
||||||
|
|
||||||
if ((status & ~I2C_STAT_XRDY) == 0 || (status & I2C_STAT_AL)) {
|
if ((status & ~I2C_STAT_XRDY) == 0 || (status & I2C_STAT_AL)) {
|
||||||
/*
|
/*
|
||||||
|
@ -223,7 +216,7 @@ int i2c_probe(uchar chip)
|
||||||
*/
|
*/
|
||||||
if (status == I2C_STAT_XRDY)
|
if (status == I2C_STAT_XRDY)
|
||||||
printf("i2c_probe: pads on bus %d probably not configured (status=0x%x)\n",
|
printf("i2c_probe: pads on bus %d probably not configured (status=0x%x)\n",
|
||||||
current_bus, status);
|
adap->hwadapnr, status);
|
||||||
|
|
||||||
goto pr_exit;
|
goto pr_exit;
|
||||||
}
|
}
|
||||||
|
@ -239,7 +232,7 @@ int i2c_probe(uchar chip)
|
||||||
I2C_CON_STP, &i2c_base->con); /* STP */
|
I2C_CON_STP, &i2c_base->con); /* STP */
|
||||||
}
|
}
|
||||||
pr_exit:
|
pr_exit:
|
||||||
flush_fifo();
|
flush_fifo(adap);
|
||||||
writew(0xFFFF, &i2c_base->stat);
|
writew(0xFFFF, &i2c_base->stat);
|
||||||
writew(0, &i2c_base->cnt);
|
writew(0, &i2c_base->cnt);
|
||||||
return res;
|
return res;
|
||||||
|
@ -258,8 +251,10 @@ pr_exit:
|
||||||
* or that do not need a register address at all (such as some clock
|
* or that do not need a register address at all (such as some clock
|
||||||
* distributors).
|
* distributors).
|
||||||
*/
|
*/
|
||||||
int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
|
static int omap24_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
|
||||||
|
int alen, uchar *buffer, int len)
|
||||||
{
|
{
|
||||||
|
struct i2c *i2c_base = omap24_get_base(adap);
|
||||||
int i2c_error = 0;
|
int i2c_error = 0;
|
||||||
u16 status;
|
u16 status;
|
||||||
|
|
||||||
|
@ -287,7 +282,7 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
|
||||||
}
|
}
|
||||||
|
|
||||||
/* Wait until bus not busy */
|
/* Wait until bus not busy */
|
||||||
if (wait_for_bb())
|
if (wait_for_bb(adap))
|
||||||
return 1;
|
return 1;
|
||||||
|
|
||||||
/* Zero, one or two bytes reg address (offset) */
|
/* Zero, one or two bytes reg address (offset) */
|
||||||
|
@ -308,12 +303,12 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
|
||||||
#endif
|
#endif
|
||||||
/* Send register offset */
|
/* Send register offset */
|
||||||
while (1) {
|
while (1) {
|
||||||
status = wait_for_event();
|
status = wait_for_event(adap);
|
||||||
/* Try to identify bus that is not padconf'd for I2C */
|
/* Try to identify bus that is not padconf'd for I2C */
|
||||||
if (status == I2C_STAT_XRDY) {
|
if (status == I2C_STAT_XRDY) {
|
||||||
i2c_error = 2;
|
i2c_error = 2;
|
||||||
printf("i2c_read (addr phase): pads on bus %d probably not configured (status=0x%x)\n",
|
printf("i2c_read (addr phase): pads on bus %d probably not configured (status=0x%x)\n",
|
||||||
current_bus, status);
|
adap->hwadapnr, status);
|
||||||
goto rd_exit;
|
goto rd_exit;
|
||||||
}
|
}
|
||||||
if (status == 0 || status & I2C_STAT_NACK) {
|
if (status == 0 || status & I2C_STAT_NACK) {
|
||||||
|
@ -348,7 +343,7 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
|
||||||
|
|
||||||
/* Receive data */
|
/* Receive data */
|
||||||
while (1) {
|
while (1) {
|
||||||
status = wait_for_event();
|
status = wait_for_event(adap);
|
||||||
/*
|
/*
|
||||||
* Try to identify bus that is not padconf'd for I2C. This
|
* Try to identify bus that is not padconf'd for I2C. This
|
||||||
* state could be left over from previous transactions if
|
* state could be left over from previous transactions if
|
||||||
|
@ -357,7 +352,7 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
|
||||||
if (status == I2C_STAT_XRDY) {
|
if (status == I2C_STAT_XRDY) {
|
||||||
i2c_error = 2;
|
i2c_error = 2;
|
||||||
printf("i2c_read (data phase): pads on bus %d probably not configured (status=0x%x)\n",
|
printf("i2c_read (data phase): pads on bus %d probably not configured (status=0x%x)\n",
|
||||||
current_bus, status);
|
adap->hwadapnr, status);
|
||||||
goto rd_exit;
|
goto rd_exit;
|
||||||
}
|
}
|
||||||
if (status == 0 || status & I2C_STAT_NACK) {
|
if (status == 0 || status & I2C_STAT_NACK) {
|
||||||
|
@ -375,15 +370,17 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
|
||||||
}
|
}
|
||||||
|
|
||||||
rd_exit:
|
rd_exit:
|
||||||
flush_fifo();
|
flush_fifo(adap);
|
||||||
writew(0xFFFF, &i2c_base->stat);
|
writew(0xFFFF, &i2c_base->stat);
|
||||||
writew(0, &i2c_base->cnt);
|
writew(0, &i2c_base->cnt);
|
||||||
return i2c_error;
|
return i2c_error;
|
||||||
}
|
}
|
||||||
|
|
||||||
/* i2c_write: Address (reg offset) may be 0, 1 or 2 bytes long. */
|
/* i2c_write: Address (reg offset) may be 0, 1 or 2 bytes long. */
|
||||||
int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
|
static int omap24_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
|
||||||
|
int alen, uchar *buffer, int len)
|
||||||
{
|
{
|
||||||
|
struct i2c *i2c_base = omap24_get_base(adap);
|
||||||
int i;
|
int i;
|
||||||
u16 status;
|
u16 status;
|
||||||
int i2c_error = 0;
|
int i2c_error = 0;
|
||||||
|
@ -415,7 +412,7 @@ int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
|
||||||
}
|
}
|
||||||
|
|
||||||
/* Wait until bus not busy */
|
/* Wait until bus not busy */
|
||||||
if (wait_for_bb())
|
if (wait_for_bb(adap))
|
||||||
return 1;
|
return 1;
|
||||||
|
|
||||||
/* Start address phase - will write regoffset + len bytes data */
|
/* Start address phase - will write regoffset + len bytes data */
|
||||||
|
@ -428,12 +425,12 @@ int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
|
||||||
|
|
||||||
while (alen) {
|
while (alen) {
|
||||||
/* Must write reg offset (one or two bytes) */
|
/* Must write reg offset (one or two bytes) */
|
||||||
status = wait_for_event();
|
status = wait_for_event(adap);
|
||||||
/* Try to identify bus that is not padconf'd for I2C */
|
/* Try to identify bus that is not padconf'd for I2C */
|
||||||
if (status == I2C_STAT_XRDY) {
|
if (status == I2C_STAT_XRDY) {
|
||||||
i2c_error = 2;
|
i2c_error = 2;
|
||||||
printf("i2c_write: pads on bus %d probably not configured (status=0x%x)\n",
|
printf("i2c_write: pads on bus %d probably not configured (status=0x%x)\n",
|
||||||
current_bus, status);
|
adap->hwadapnr, status);
|
||||||
goto wr_exit;
|
goto wr_exit;
|
||||||
}
|
}
|
||||||
if (status == 0 || status & I2C_STAT_NACK) {
|
if (status == 0 || status & I2C_STAT_NACK) {
|
||||||
|
@ -455,7 +452,7 @@ int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
|
||||||
}
|
}
|
||||||
/* Address phase is over, now write data */
|
/* Address phase is over, now write data */
|
||||||
for (i = 0; i < len; i++) {
|
for (i = 0; i < len; i++) {
|
||||||
status = wait_for_event();
|
status = wait_for_event(adap);
|
||||||
if (status == 0 || status & I2C_STAT_NACK) {
|
if (status == 0 || status & I2C_STAT_NACK) {
|
||||||
i2c_error = 1;
|
i2c_error = 1;
|
||||||
printf("i2c_write: error waiting for data ACK (status=0x%x)\n",
|
printf("i2c_write: error waiting for data ACK (status=0x%x)\n",
|
||||||
|
@ -474,7 +471,7 @@ int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
|
||||||
}
|
}
|
||||||
|
|
||||||
wr_exit:
|
wr_exit:
|
||||||
flush_fifo();
|
flush_fifo(adap);
|
||||||
writew(0xFFFF, &i2c_base->stat);
|
writew(0xFFFF, &i2c_base->stat);
|
||||||
writew(0, &i2c_base->cnt);
|
writew(0, &i2c_base->cnt);
|
||||||
return i2c_error;
|
return i2c_error;
|
||||||
|
@ -484,8 +481,9 @@ wr_exit:
|
||||||
* Wait for the bus to be free by checking the Bus Busy (BB)
|
* Wait for the bus to be free by checking the Bus Busy (BB)
|
||||||
* bit to become clear
|
* bit to become clear
|
||||||
*/
|
*/
|
||||||
static int wait_for_bb(void)
|
static int wait_for_bb(struct i2c_adapter *adap)
|
||||||
{
|
{
|
||||||
|
struct i2c *i2c_base = omap24_get_base(adap);
|
||||||
int timeout = I2C_TIMEOUT;
|
int timeout = I2C_TIMEOUT;
|
||||||
u16 stat;
|
u16 stat;
|
||||||
|
|
||||||
|
@ -514,8 +512,9 @@ static int wait_for_bb(void)
|
||||||
* Wait for the I2C controller to complete current action
|
* Wait for the I2C controller to complete current action
|
||||||
* and update status
|
* and update status
|
||||||
*/
|
*/
|
||||||
static u16 wait_for_event(void)
|
static u16 wait_for_event(struct i2c_adapter *adap)
|
||||||
{
|
{
|
||||||
|
struct i2c *i2c_base = omap24_get_base(adap);
|
||||||
u16 status;
|
u16 status;
|
||||||
int timeout = I2C_TIMEOUT;
|
int timeout = I2C_TIMEOUT;
|
||||||
|
|
||||||
|
@ -540,7 +539,7 @@ static u16 wait_for_event(void)
|
||||||
* not been configured for I2C, and/or pull-ups are missing.
|
* not been configured for I2C, and/or pull-ups are missing.
|
||||||
*/
|
*/
|
||||||
printf("Check if pads/pull-ups of bus %d are properly configured\n",
|
printf("Check if pads/pull-ups of bus %d are properly configured\n",
|
||||||
current_bus);
|
adap->hwadapnr);
|
||||||
writew(0xFFFF, &i2c_base->stat);
|
writew(0xFFFF, &i2c_base->stat);
|
||||||
status = 0;
|
status = 0;
|
||||||
}
|
}
|
||||||
|
@ -548,48 +547,93 @@ static u16 wait_for_event(void)
|
||||||
return status;
|
return status;
|
||||||
}
|
}
|
||||||
|
|
||||||
int i2c_set_bus_num(unsigned int bus)
|
static struct i2c *omap24_get_base(struct i2c_adapter *adap)
|
||||||
{
|
{
|
||||||
if (bus >= I2C_BUS_MAX) {
|
switch (adap->hwadapnr) {
|
||||||
printf("Bad bus: %x\n", bus);
|
|
||||||
return -1;
|
|
||||||
}
|
|
||||||
|
|
||||||
switch (bus) {
|
|
||||||
default:
|
|
||||||
bus = 0; /* Fall through */
|
|
||||||
case 0:
|
case 0:
|
||||||
i2c_base = (struct i2c *)I2C_BASE1;
|
return (struct i2c *)I2C_BASE1;
|
||||||
break;
|
break;
|
||||||
case 1:
|
case 1:
|
||||||
i2c_base = (struct i2c *)I2C_BASE2;
|
return (struct i2c *)I2C_BASE2;
|
||||||
break;
|
break;
|
||||||
#if (I2C_BUS_MAX > 2)
|
#if (I2C_BUS_MAX > 2)
|
||||||
case 2:
|
case 2:
|
||||||
i2c_base = (struct i2c *)I2C_BASE3;
|
return (struct i2c *)I2C_BASE3;
|
||||||
break;
|
break;
|
||||||
#if (I2C_BUS_MAX > 3)
|
#if (I2C_BUS_MAX > 3)
|
||||||
case 3:
|
case 3:
|
||||||
i2c_base = (struct i2c *)I2C_BASE4;
|
return (struct i2c *)I2C_BASE4;
|
||||||
break;
|
break;
|
||||||
#if (I2C_BUS_MAX > 4)
|
#if (I2C_BUS_MAX > 4)
|
||||||
case 4:
|
case 4:
|
||||||
i2c_base = (struct i2c *)I2C_BASE5;
|
return (struct i2c *)I2C_BASE5;
|
||||||
break;
|
break;
|
||||||
#endif
|
#endif
|
||||||
#endif
|
#endif
|
||||||
#endif
|
#endif
|
||||||
|
default:
|
||||||
|
printf("wrong hwadapnr: %d\n", adap->hwadapnr);
|
||||||
|
break;
|
||||||
}
|
}
|
||||||
|
return NULL;
|
||||||
current_bus = bus;
|
|
||||||
|
|
||||||
if (!bus_initialized[current_bus])
|
|
||||||
i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
|
|
||||||
|
|
||||||
return 0;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
int i2c_get_bus_num(void)
|
#if !defined(CONFIG_SYS_OMAP24_I2C_SPEED1)
|
||||||
{
|
#define CONFIG_SYS_OMAP24_I2C_SPEED1 CONFIG_SYS_OMAP24_I2C_SPEED
|
||||||
return (int) current_bus;
|
#endif
|
||||||
}
|
#if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE1)
|
||||||
|
#define CONFIG_SYS_OMAP24_I2C_SLAVE1 CONFIG_SYS_OMAP24_I2C_SLAVE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
U_BOOT_I2C_ADAP_COMPLETE(omap24_0, omap24_i2c_init, omap24_i2c_probe,
|
||||||
|
omap24_i2c_read, omap24_i2c_write, NULL,
|
||||||
|
CONFIG_SYS_OMAP24_I2C_SPEED,
|
||||||
|
CONFIG_SYS_OMAP24_I2C_SLAVE,
|
||||||
|
0)
|
||||||
|
U_BOOT_I2C_ADAP_COMPLETE(omap24_1, omap24_i2c_init, omap24_i2c_probe,
|
||||||
|
omap24_i2c_read, omap24_i2c_write, NULL,
|
||||||
|
CONFIG_SYS_OMAP24_I2C_SPEED1,
|
||||||
|
CONFIG_SYS_OMAP24_I2C_SLAVE1,
|
||||||
|
1)
|
||||||
|
#if (I2C_BUS_MAX > 2)
|
||||||
|
#if !defined(CONFIG_SYS_OMAP24_I2C_SPEED2)
|
||||||
|
#define CONFIG_SYS_OMAP24_I2C_SPEED2 CONFIG_SYS_OMAP24_I2C_SPEED
|
||||||
|
#endif
|
||||||
|
#if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE2)
|
||||||
|
#define CONFIG_SYS_OMAP24_I2C_SLAVE2 CONFIG_SYS_OMAP24_I2C_SLAVE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
U_BOOT_I2C_ADAP_COMPLETE(omap24_2, omap24_i2c_init, omap24_i2c_probe,
|
||||||
|
omap24_i2c_read, omap24_i2c_write, NULL,
|
||||||
|
CONFIG_SYS_OMAP24_I2C_SPEED2,
|
||||||
|
CONFIG_SYS_OMAP24_I2C_SLAVE2,
|
||||||
|
2)
|
||||||
|
#if (I2C_BUS_MAX > 3)
|
||||||
|
#if !defined(CONFIG_SYS_OMAP24_I2C_SPEED3)
|
||||||
|
#define CONFIG_SYS_OMAP24_I2C_SPEED3 CONFIG_SYS_OMAP24_I2C_SPEED
|
||||||
|
#endif
|
||||||
|
#if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE3)
|
||||||
|
#define CONFIG_SYS_OMAP24_I2C_SLAVE3 CONFIG_SYS_OMAP24_I2C_SLAVE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
U_BOOT_I2C_ADAP_COMPLETE(omap24_3, omap24_i2c_init, omap24_i2c_probe,
|
||||||
|
omap24_i2c_read, omap24_i2c_write, NULL,
|
||||||
|
CONFIG_SYS_OMAP24_I2C_SPEED3,
|
||||||
|
CONFIG_SYS_OMAP24_I2C_SLAVE3,
|
||||||
|
3)
|
||||||
|
#if (I2C_BUS_MAX > 4)
|
||||||
|
#if !defined(CONFIG_SYS_OMAP24_I2C_SPEED4)
|
||||||
|
#define CONFIG_SYS_OMAP24_I2C_SPEED4 CONFIG_SYS_OMAP24_I2C_SPEED
|
||||||
|
#endif
|
||||||
|
#if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE4)
|
||||||
|
#define CONFIG_SYS_OMAP24_I2C_SLAVE4 CONFIG_SYS_OMAP24_I2C_SLAVE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
U_BOOT_I2C_ADAP_COMPLETE(omap24_4, omap24_i2c_init, omap24_i2c_probe,
|
||||||
|
omap24_i2c_read, omap24_i2c_write, NULL,
|
||||||
|
CONFIG_SYS_OMAP24_I2C_SPEED4,
|
||||||
|
CONFIG_SYS_OMAP24_I2C_SLAVE4,
|
||||||
|
4)
|
||||||
|
#endif
|
||||||
|
#endif
|
||||||
|
#endif
|
||||||
|
|
|
@ -183,7 +183,6 @@
|
||||||
#define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */
|
#define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */
|
||||||
#define CONFIG_BAUDRATE 115200
|
#define CONFIG_BAUDRATE 115200
|
||||||
|
|
||||||
/* I2C Configuration */
|
|
||||||
#define CONFIG_CMD_EEPROM
|
#define CONFIG_CMD_EEPROM
|
||||||
#define CONFIG_ENV_EEPROM_IS_ON_I2C
|
#define CONFIG_ENV_EEPROM_IS_ON_I2C
|
||||||
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */
|
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */
|
||||||
|
|
|
@ -142,10 +142,10 @@
|
||||||
#undef CONFIG_CMD_IMLS /* List all found images */
|
#undef CONFIG_CMD_IMLS /* List all found images */
|
||||||
|
|
||||||
#define CONFIG_SYS_NO_FLASH
|
#define CONFIG_SYS_NO_FLASH
|
||||||
#define CONFIG_HARD_I2C 1
|
#define CONFIG_SYS_I2C
|
||||||
#define CONFIG_SYS_I2C_SPEED 100000
|
#define CONFIG_SYS_OMAP24_I2C_SPEED 100000
|
||||||
#define CONFIG_SYS_I2C_SLAVE 1
|
#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
|
||||||
#define CONFIG_DRIVER_OMAP34XX_I2C 1
|
#define CONFIG_SYS_I2C_OMAP34XX
|
||||||
|
|
||||||
#undef CONFIG_CMD_NET
|
#undef CONFIG_CMD_NET
|
||||||
#undef CONFIG_CMD_NFS
|
#undef CONFIG_CMD_NFS
|
||||||
|
|
|
@ -136,10 +136,10 @@
|
||||||
#undef CONFIG_CMD_IMLS /* List all found images */
|
#undef CONFIG_CMD_IMLS /* List all found images */
|
||||||
|
|
||||||
#define CONFIG_SYS_NO_FLASH
|
#define CONFIG_SYS_NO_FLASH
|
||||||
#define CONFIG_HARD_I2C 1
|
#define CONFIG_SYS_I2C
|
||||||
#define CONFIG_SYS_I2C_SPEED 100000
|
#define CONFIG_SYS_OMAP24_I2C_SPEED 100000
|
||||||
#define CONFIG_SYS_I2C_SLAVE 1
|
#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
|
||||||
#define CONFIG_DRIVER_OMAP34XX_I2C 1
|
#define CONFIG_SYS_I2C_OMAP34XX
|
||||||
|
|
||||||
#undef CONFIG_CMD_NET
|
#undef CONFIG_CMD_NET
|
||||||
#undef CONFIG_CMD_NFS
|
#undef CONFIG_CMD_NFS
|
||||||
|
|
|
@ -141,10 +141,10 @@
|
||||||
#undef CONFIG_CMD_IMLS /* List all found images */
|
#undef CONFIG_CMD_IMLS /* List all found images */
|
||||||
|
|
||||||
#define CONFIG_SYS_NO_FLASH
|
#define CONFIG_SYS_NO_FLASH
|
||||||
#define CONFIG_HARD_I2C
|
#define CONFIG_SYS_I2C
|
||||||
#define CONFIG_SYS_I2C_SPEED 100000
|
#define CONFIG_SYS_OMAP24_I2C_SPEED 100000
|
||||||
#define CONFIG_SYS_I2C_SLAVE 1
|
#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
|
||||||
#define CONFIG_DRIVER_OMAP34XX_I2C
|
#define CONFIG_SYS_I2C_OMAP34XX
|
||||||
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
|
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
|
||||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
|
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
|
||||||
#define CONFIG_I2C_MULTI_BUS
|
#define CONFIG_I2C_MULTI_BUS
|
||||||
|
|
|
@ -90,10 +90,10 @@
|
||||||
#define CONFIG_DOS_PARTITION 1
|
#define CONFIG_DOS_PARTITION 1
|
||||||
|
|
||||||
/* I2C */
|
/* I2C */
|
||||||
#define CONFIG_HARD_I2C 1
|
#define CONFIG_SYS_I2C
|
||||||
#define CONFIG_SYS_I2C_SPEED 100000
|
#define CONFIG_SYS_OMAP24_I2C_SPEED 100000
|
||||||
#define CONFIG_SYS_I2C_SLAVE 1
|
#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
|
||||||
#define CONFIG_DRIVER_OMAP34XX_I2C 1
|
#define CONFIG_SYS_I2C_OMAP34XX
|
||||||
|
|
||||||
/* TWL4030 */
|
/* TWL4030 */
|
||||||
#define CONFIG_TWL4030_POWER 1
|
#define CONFIG_TWL4030_POWER 1
|
||||||
|
|
|
@ -123,10 +123,10 @@
|
||||||
#undef CONFIG_CMD_NFS /* NFS support */
|
#undef CONFIG_CMD_NFS /* NFS support */
|
||||||
|
|
||||||
#define CONFIG_SYS_NO_FLASH
|
#define CONFIG_SYS_NO_FLASH
|
||||||
#define CONFIG_HARD_I2C
|
#define CONFIG_SYS_I2C
|
||||||
#define CONFIG_SYS_I2C_SPEED 100000
|
#define CONFIG_SYS_OMAP24_I2C_SPEED 100000
|
||||||
#define CONFIG_SYS_I2C_SLAVE 1
|
#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
|
||||||
#define CONFIG_DRIVER_OMAP34XX_I2C 1
|
#define CONFIG_SYS_I2C_OMAP34XX
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* TWL4030
|
* TWL4030
|
||||||
|
|
|
@ -137,10 +137,10 @@
|
||||||
#undef CONFIG_CMD_IMLS /* List all found images */
|
#undef CONFIG_CMD_IMLS /* List all found images */
|
||||||
|
|
||||||
#define CONFIG_SYS_NO_FLASH
|
#define CONFIG_SYS_NO_FLASH
|
||||||
#define CONFIG_HARD_I2C
|
#define CONFIG_SYS_I2C
|
||||||
#define CONFIG_SYS_I2C_SPEED 100000
|
#define CONFIG_SYS_OMAP24_I2C_SPEED 100000
|
||||||
#define CONFIG_SYS_I2C_SLAVE 1
|
#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
|
||||||
#define CONFIG_DRIVER_OMAP34XX_I2C
|
#define CONFIG_SYS_I2C_OMAP34XX
|
||||||
|
|
||||||
/* RTC */
|
/* RTC */
|
||||||
#define CONFIG_RTC_DS1337
|
#define CONFIG_RTC_DS1337
|
||||||
|
|
|
@ -157,10 +157,10 @@
|
||||||
#undef CONFIG_CMD_SETGETDCR /* DCR support on 4xx */
|
#undef CONFIG_CMD_SETGETDCR /* DCR support on 4xx */
|
||||||
|
|
||||||
#define CONFIG_OMAP3_SPI
|
#define CONFIG_OMAP3_SPI
|
||||||
#define CONFIG_HARD_I2C
|
#define CONFIG_SYS_I2C
|
||||||
#define CONFIG_SYS_I2C_SPEED 100000
|
#define CONFIG_SYS_OMAP24_I2C_SPEED 100000
|
||||||
#define CONFIG_SYS_I2C_SLAVE 1
|
#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
|
||||||
#define CONFIG_DRIVER_OMAP34XX_I2C
|
#define CONFIG_SYS_I2C_OMAP34XX
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* TWL4030
|
* TWL4030
|
||||||
|
|
|
@ -161,11 +161,10 @@
|
||||||
#undef CONFIG_CMD_IMLS /* List all found images */
|
#undef CONFIG_CMD_IMLS /* List all found images */
|
||||||
|
|
||||||
#define CONFIG_SYS_NO_FLASH
|
#define CONFIG_SYS_NO_FLASH
|
||||||
#define CONFIG_HARD_I2C 1
|
#define CONFIG_SYS_I2C
|
||||||
#define CONFIG_SYS_I2C_SPEED 100000
|
#define CONFIG_SYS_OMAP24_I2C_SPEED 100000
|
||||||
#define CONFIG_SYS_I2C_SLAVE 1
|
#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
|
||||||
#define CONFIG_I2C_MULTI_BUS 1
|
#define CONFIG_SYS_I2C_OMAP34XX
|
||||||
#define CONFIG_DRIVER_OMAP34XX_I2C 1
|
|
||||||
#define CONFIG_VIDEO_OMAP3 /* DSS Support */
|
#define CONFIG_VIDEO_OMAP3 /* DSS Support */
|
||||||
|
|
||||||
/*
|
/*
|
||||||
|
|
|
@ -87,11 +87,10 @@
|
||||||
/*
|
/*
|
||||||
* I2C
|
* I2C
|
||||||
*/
|
*/
|
||||||
#define CONFIG_HARD_I2C
|
#define CONFIG_SYS_I2C
|
||||||
#define CONFIG_DRIVER_OMAP34XX_I2C
|
#define CONFIG_SYS_OMAP24_I2C_SPEED 100000
|
||||||
|
#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
|
||||||
#define CONFIG_SYS_I2C_SPEED 100000
|
#define CONFIG_SYS_I2C_OMAP34XX
|
||||||
#define CONFIG_SYS_I2C_SLAVE 1
|
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* PISMO support
|
* PISMO support
|
||||||
|
|
|
@ -124,10 +124,10 @@
|
||||||
#undef CONFIG_CMD_IMLS /* List all found images */
|
#undef CONFIG_CMD_IMLS /* List all found images */
|
||||||
|
|
||||||
#define CONFIG_SYS_NO_FLASH
|
#define CONFIG_SYS_NO_FLASH
|
||||||
#define CONFIG_HARD_I2C 1
|
#define CONFIG_SYS_I2C
|
||||||
#define CONFIG_SYS_I2C_SPEED 100000
|
#define CONFIG_SYS_I2C_OMAP34XX
|
||||||
#define CONFIG_SYS_I2C_SLAVE 1
|
#define CONFIG_SYS_OMAP24_I2C_SPEED 100000
|
||||||
#define CONFIG_DRIVER_OMAP34XX_I2C 1
|
#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* TWL4030
|
* TWL4030
|
||||||
|
|
|
@ -118,12 +118,10 @@
|
||||||
/*
|
/*
|
||||||
* I2C
|
* I2C
|
||||||
*/
|
*/
|
||||||
#define CONFIG_HARD_I2C
|
#define CONFIG_SYS_I2C
|
||||||
#define CONFIG_DRIVER_OMAP34XX_I2C
|
#define CONFIG_SYS_OMAP24_I2C_SPEED 100000
|
||||||
|
#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
|
||||||
#define CONFIG_SYS_I2C_SPEED 100000
|
#define CONFIG_SYS_I2C_OMAP34XX
|
||||||
#define CONFIG_SYS_I2C_SLAVE 1
|
|
||||||
#define CONFIG_I2C_MULTI_BUS
|
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* TWL4030
|
* TWL4030
|
||||||
|
|
|
@ -128,11 +128,10 @@
|
||||||
#define CONFIG_CMD_PING
|
#define CONFIG_CMD_PING
|
||||||
#define CONFIG_CMD_FPGA
|
#define CONFIG_CMD_FPGA
|
||||||
|
|
||||||
#define CONFIG_HARD_I2C 1
|
#define CONFIG_SYS_I2C
|
||||||
#define CONFIG_SYS_I2C_SPEED 100000
|
#define CONFIG_SYS_OMAP24_I2C_SPEED 100000
|
||||||
#define CONFIG_SYS_I2C_SLAVE 0
|
#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
|
||||||
#define CONFIG_DRIVER_OMAP34XX_I2C 1
|
#define CONFIG_SYS_I2C_OMAP34XX
|
||||||
#define CONFIG_I2C_MULTI_BUS 1
|
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* TWL4030
|
* TWL4030
|
||||||
|
|
|
@ -98,11 +98,10 @@
|
||||||
#define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */
|
#define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */
|
||||||
|
|
||||||
#define CONFIG_SYS_NO_FLASH
|
#define CONFIG_SYS_NO_FLASH
|
||||||
#define CONFIG_HARD_I2C
|
#define CONFIG_SYS_I2C
|
||||||
#define CONFIG_SYS_I2C_SPEED 100000
|
#define CONFIG_SYS_OMAP24_I2C_SPEED 100000
|
||||||
#define CONFIG_SYS_I2C_SLAVE 1
|
#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
|
||||||
#define CONFIG_I2C_MULTI_BUS
|
#define CONFIG_SYS_I2C_OMAP34XX
|
||||||
#define CONFIG_DRIVER_OMAP34XX_I2C
|
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* TWL4030
|
* TWL4030
|
||||||
|
|
|
@ -111,10 +111,10 @@
|
||||||
#undef CONFIG_CMD_NFS /* NFS support */
|
#undef CONFIG_CMD_NFS /* NFS support */
|
||||||
|
|
||||||
#define CONFIG_SYS_NO_FLASH
|
#define CONFIG_SYS_NO_FLASH
|
||||||
#define CONFIG_HARD_I2C 1
|
#define CONFIG_SYS_I2C
|
||||||
#define CONFIG_SYS_I2C_SPEED 100000
|
#define CONFIG_SYS_OMAP24_I2C_SPEED 100000
|
||||||
#define CONFIG_SYS_I2C_SLAVE 1
|
#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
|
||||||
#define CONFIG_DRIVER_OMAP34XX_I2C 1
|
#define CONFIG_SYS_I2C_OMAP34XX
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* TWL4030
|
* TWL4030
|
||||||
|
|
|
@ -114,10 +114,10 @@
|
||||||
/*
|
/*
|
||||||
* I2C for power management setup
|
* I2C for power management setup
|
||||||
*/
|
*/
|
||||||
#define CONFIG_HARD_I2C 1
|
#define CONFIG_SYS_I2C
|
||||||
#define CONFIG_SYS_I2C_SPEED 100000
|
#define CONFIG_SYS_OMAP24_I2C_SPEED 100000
|
||||||
#define CONFIG_SYS_I2C_SLAVE 1
|
#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
|
||||||
#define CONFIG_DRIVER_OMAP34XX_I2C 1
|
#define CONFIG_SYS_I2C_OMAP34XX
|
||||||
|
|
||||||
/* OMITTED: single 1 Gbit MT29F1G NAND flash */
|
/* OMITTED: single 1 Gbit MT29F1G NAND flash */
|
||||||
|
|
||||||
|
|
|
@ -118,10 +118,10 @@
|
||||||
#undef CONFIG_CMD_NFS /* NFS support */
|
#undef CONFIG_CMD_NFS /* NFS support */
|
||||||
|
|
||||||
#define CONFIG_SYS_NO_FLASH
|
#define CONFIG_SYS_NO_FLASH
|
||||||
#define CONFIG_HARD_I2C 1
|
#define CONFIG_SYS_I2C
|
||||||
#define CONFIG_SYS_I2C_SPEED 100000
|
#define CONFIG_SYS_OMAP24_I2C_SPEED 100000
|
||||||
#define CONFIG_SYS_I2C_SLAVE 1
|
#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
|
||||||
#define CONFIG_DRIVER_OMAP34XX_I2C 1
|
#define CONFIG_SYS_I2C_OMAP34XX
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* TWL4030
|
* TWL4030
|
||||||
|
|
|
@ -138,10 +138,10 @@
|
||||||
#undef CONFIG_CMD_NFS /* NFS support */
|
#undef CONFIG_CMD_NFS /* NFS support */
|
||||||
|
|
||||||
#define CONFIG_SYS_NO_FLASH
|
#define CONFIG_SYS_NO_FLASH
|
||||||
#define CONFIG_HARD_I2C 1
|
#define CONFIG_SYS_I2C
|
||||||
#define CONFIG_SYS_I2C_SPEED 100000
|
#define CONFIG_SYS_OMAP24_I2C_SPEED 100000
|
||||||
#define CONFIG_SYS_I2C_SLAVE 1
|
#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
|
||||||
#define CONFIG_DRIVER_OMAP34XX_I2C 1
|
#define CONFIG_SYS_I2C_OMAP34XX
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* TWL4030
|
* TWL4030
|
||||||
|
|
|
@ -172,11 +172,10 @@
|
||||||
/* I2C Configuration */
|
/* I2C Configuration */
|
||||||
#define CONFIG_I2C
|
#define CONFIG_I2C
|
||||||
#define CONFIG_CMD_I2C
|
#define CONFIG_CMD_I2C
|
||||||
#define CONFIG_HARD_I2C
|
#define CONFIG_SYS_I2C
|
||||||
#define CONFIG_SYS_I2C_SPEED 100000
|
#define CONFIG_SYS_OMAP24_I2C_SPEED 100000
|
||||||
#define CONFIG_SYS_I2C_SLAVE 1
|
#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
|
||||||
#define CONFIG_I2C_MULTI_BUS
|
#define CONFIG_SYS_I2C_OMAP24XX
|
||||||
#define CONFIG_DRIVER_OMAP24XX_I2C
|
|
||||||
#define CONFIG_CMD_EEPROM
|
#define CONFIG_CMD_EEPROM
|
||||||
#define CONFIG_ENV_EEPROM_IS_ON_I2C
|
#define CONFIG_ENV_EEPROM_IS_ON_I2C
|
||||||
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */
|
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */
|
||||||
|
|
|
@ -131,11 +131,10 @@
|
||||||
/* I2C Configuration */
|
/* I2C Configuration */
|
||||||
#define CONFIG_I2C
|
#define CONFIG_I2C
|
||||||
#define CONFIG_CMD_I2C
|
#define CONFIG_CMD_I2C
|
||||||
#define CONFIG_HARD_I2C
|
#define CONFIG_SYS_I2C
|
||||||
#define CONFIG_SYS_I2C_SLAVE 1
|
#define CONFIG_SYS_OMAP24_I2C_SPEED OMAP_I2C_STANDARD
|
||||||
#define CONFIG_I2C_MULTI_BUS
|
#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
|
||||||
#define CONFIG_DRIVER_OMAP24XX_I2C
|
#define CONFIG_SYS_I2C_OMAP24XX
|
||||||
|
|
||||||
|
|
||||||
/* Defines for SPL */
|
/* Defines for SPL */
|
||||||
#define CONFIG_SPL
|
#define CONFIG_SPL
|
||||||
|
|
|
@ -117,14 +117,13 @@
|
||||||
#undef CONFIG_CMD_IMLS
|
#undef CONFIG_CMD_IMLS
|
||||||
|
|
||||||
#define CONFIG_SYS_NO_FLASH
|
#define CONFIG_SYS_NO_FLASH
|
||||||
#define CONFIG_HARD_I2C
|
#define CONFIG_SYS_I2C
|
||||||
#define CONFIG_SYS_I2C_SPEED 400000
|
#define CONFIG_SYS_OMAP24_I2C_SPEED 400000
|
||||||
#define CONFIG_SYS_I2C_SLAVE 1
|
#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
|
||||||
|
#define CONFIG_SYS_I2C_OMAP34XX
|
||||||
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* base address */
|
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* base address */
|
||||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */
|
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */
|
||||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
|
#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
|
||||||
#define CONFIG_DRIVER_OMAP34XX_I2C
|
|
||||||
|
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Board NAND Info.
|
* Board NAND Info.
|
||||||
|
@ -369,7 +368,7 @@ struct tam3517_module_info {
|
||||||
|
|
||||||
#define TAM3517_READ_EEPROM(info, ret) \
|
#define TAM3517_READ_EEPROM(info, ret) \
|
||||||
do { \
|
do { \
|
||||||
i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); \
|
i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); \
|
||||||
if (eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, \
|
if (eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, \
|
||||||
(void *)info, sizeof(*info))) \
|
(void *)info, sizeof(*info))) \
|
||||||
ret = 1; \
|
ret = 1; \
|
||||||
|
|
|
@ -59,12 +59,11 @@
|
||||||
|
|
||||||
/* I2C IP block */
|
/* I2C IP block */
|
||||||
#define CONFIG_I2C
|
#define CONFIG_I2C
|
||||||
#define CONFIG_HARD_I2C
|
|
||||||
#define CONFIG_SYS_I2C_SPEED 100000
|
|
||||||
#define CONFIG_SYS_I2C_SLAVE 1
|
|
||||||
#define CONFIG_I2C_MULTI_BUS
|
|
||||||
#define CONFIG_DRIVER_OMAP24XX_I2C
|
|
||||||
#define CONFIG_CMD_I2C
|
#define CONFIG_CMD_I2C
|
||||||
|
#define CONFIG_SYS_I2C
|
||||||
|
#define CONFIG_SYS_OMAP24_I2C_SPEED 100000
|
||||||
|
#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
|
||||||
|
#define CONFIG_SYS_I2C_OMAP24XX
|
||||||
|
|
||||||
/* MMC/SD IP block */
|
/* MMC/SD IP block */
|
||||||
#define CONFIG_MMC
|
#define CONFIG_MMC
|
||||||
|
|
|
@ -98,11 +98,11 @@
|
||||||
#define CONFIG_DOS_PARTITION
|
#define CONFIG_DOS_PARTITION
|
||||||
|
|
||||||
/* I2C */
|
/* I2C */
|
||||||
#define CONFIG_HARD_I2C
|
#define CONFIG_SYS_I2C
|
||||||
#define CONFIG_SYS_I2C_SPEED 100000
|
#define CONFIG_SYS_OMAP24_I2C_SPEED 100000
|
||||||
#define CONFIG_SYS_I2C_SLAVE 1
|
#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
|
||||||
#define CONFIG_DRIVER_OMAP34XX_I2C 1
|
#define CONFIG_SYS_I2C_OMAP34XX
|
||||||
#define CONFIG_I2C_MULTI_BUS
|
|
||||||
|
|
||||||
/* EEPROM */
|
/* EEPROM */
|
||||||
#define CONFIG_SYS_I2C_MULTI_EEPROMS
|
#define CONFIG_SYS_I2C_MULTI_EEPROMS
|
||||||
|
|
Loading…
Add table
Reference in a new issue